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  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno
  • Date: 2011-06-07 12:14:05 UTC
  • mfrom: (43.1.9 sid)
  • Revision ID: james.westby@ubuntu.com-20110607121405-i3h1rd7nrnd2b73h
Tags: 2.6.39-2
http://bugs.debian.org/627492
http://bugs.debian.org/596626
http://bugs.debian.org/628932
http://bugs.debian.org/628191
http://bugs.debian.org/627837
http://bugs.debian.org/622997
http://bugs.debian.org/622745
http://bugs.debian.org/619827
http://bugs.debian.org/629401
[ Ben Hutchings ]
* [x86] Enable BACKLIGHT_APPLE, replacing BACKLIGHT_MBP_NVIDIA
  (Closes: #627492)
* cgroups: Disable memory resource controller by default. Allow it
  to be enabled using kernel parameter 'cgroup_enable=memory'.
* rt2800usb: Enable support for more USB devices including
  Linksys WUSB600N (Closes: #596626) (this change was accidentally
  omitted from 2.6.39-1)
* [x86] Remove Celeron from list of processors supporting PAE. Most
  'Celeron M' models do not.
* Update debconf template translations:
  - Swedish (Martin Bagge) (Closes: #628932)
  - French (David Prévot) (Closes: #628191)
* aufs: Update for 2.6.39 (Closes: #627837)
* Add stable 2.6.39.1, including:
  - ext4: dont set PageUptodate in ext4_end_bio()
  - pata_cmd64x: fix boot crash on parisc (Closes: #622997, #622745)
  - ext3: Fix fs corruption when make_indexed_dir() fails
  - netfilter: nf_ct_sip: validate Content-Length in TCP SIP messages
  - sctp: fix race between sctp_bind_addr_free() and
    sctp_bind_addr_conflict()
  - sctp: fix memory leak of the ASCONF queue when free asoc
  - md/bitmap: fix saving of events_cleared and other state
  - cdc_acm: Fix oops when Droids MuIn LCD is connected
  - cx88: Fix conversion from BKL to fine-grained locks (Closes: #619827)
  - keys: Set cred->user_ns in key_replace_session_keyring (CVE-2011-2184)
  - tmpfs: fix race between truncate and writepage
  - nfs41: Correct offset for LAYOUTCOMMIT
  - xen/mmu: fix a race window causing leave_mm BUG()
  - ext4: fix possible use-after-free in ext4_remove_li_request()
  For the complete list of changes, see:
   http://www.kernel.org/pub/linux/kernel/v2.6/ChangeLog-2.6.39.1
* Bump ABI to 2
* netfilter: Enable IP_SET, IP_SET_BITMAP_IP, IP_SET_BITMAP_IPMAC,
  IP_SET_BITMAP_PORT, IP_SET_HASH_IP, IP_SET_HASH_IPPORT,
  IP_SET_HASH_IPPORTIP, IP_SET_HASH_IPPORTNET, IP_SET_HASH_NET,
  IP_SET_HASH_NETPORT, IP_SET_LIST_SET, NETFILTER_XT_SET as modules
  (Closes: #629401)

[ Aurelien Jarno ]
* [mipsel/loongson-2f] Disable_SCSI_LPFC to workaround GCC ICE.

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Lines of Context:
arch/mips/include/asm/mach-cavium-octeon/irq.h
11
11
#define NR_IRQS OCTEON_IRQ_LAST
12
12
#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13
13
 
14
 
/* 0 - 7 represent the i8259 master */
15
 
#define OCTEON_IRQ_I8259M0      0
16
 
#define OCTEON_IRQ_I8259M1      1
17
 
#define OCTEON_IRQ_I8259M2      2
18
 
#define OCTEON_IRQ_I8259M3      3
19
 
#define OCTEON_IRQ_I8259M4      4
20
 
#define OCTEON_IRQ_I8259M5      5
21
 
#define OCTEON_IRQ_I8259M6      6
22
 
#define OCTEON_IRQ_I8259M7      7
23
 
/* 8 - 15 represent the i8259 slave */
24
 
#define OCTEON_IRQ_I8259S0      8
25
 
#define OCTEON_IRQ_I8259S1      9
26
 
#define OCTEON_IRQ_I8259S2      10
27
 
#define OCTEON_IRQ_I8259S3      11
28
 
#define OCTEON_IRQ_I8259S4      12
29
 
#define OCTEON_IRQ_I8259S5      13
30
 
#define OCTEON_IRQ_I8259S6      14
31
 
#define OCTEON_IRQ_I8259S7      15
32
 
/* 16 - 23 represent the 8 MIPS standard interrupt sources */
33
 
#define OCTEON_IRQ_SW0          16
34
 
#define OCTEON_IRQ_SW1          17
35
 
#define OCTEON_IRQ_CIU0         18
36
 
#define OCTEON_IRQ_CIU1         19
37
 
#define OCTEON_IRQ_CIU4         20
38
 
#define OCTEON_IRQ_5            21
39
 
#define OCTEON_IRQ_PERF         22
40
 
#define OCTEON_IRQ_TIMER        23
41
 
/* 24 - 87 represent the sources in CIU_INTX_EN0 */
42
 
#define OCTEON_IRQ_WORKQ0       24
43
 
#define OCTEON_IRQ_WORKQ1       25
44
 
#define OCTEON_IRQ_WORKQ2       26
45
 
#define OCTEON_IRQ_WORKQ3       27
46
 
#define OCTEON_IRQ_WORKQ4       28
47
 
#define OCTEON_IRQ_WORKQ5       29
48
 
#define OCTEON_IRQ_WORKQ6       30
49
 
#define OCTEON_IRQ_WORKQ7       31
50
 
#define OCTEON_IRQ_WORKQ8       32
51
 
#define OCTEON_IRQ_WORKQ9       33
52
 
#define OCTEON_IRQ_WORKQ10      34
53
 
#define OCTEON_IRQ_WORKQ11      35
54
 
#define OCTEON_IRQ_WORKQ12      36
55
 
#define OCTEON_IRQ_WORKQ13      37
56
 
#define OCTEON_IRQ_WORKQ14      38
57
 
#define OCTEON_IRQ_WORKQ15      39
58
 
#define OCTEON_IRQ_GPIO0        40
59
 
#define OCTEON_IRQ_GPIO1        41
60
 
#define OCTEON_IRQ_GPIO2        42
61
 
#define OCTEON_IRQ_GPIO3        43
62
 
#define OCTEON_IRQ_GPIO4        44
63
 
#define OCTEON_IRQ_GPIO5        45
64
 
#define OCTEON_IRQ_GPIO6        46
65
 
#define OCTEON_IRQ_GPIO7        47
66
 
#define OCTEON_IRQ_GPIO8        48
67
 
#define OCTEON_IRQ_GPIO9        49
68
 
#define OCTEON_IRQ_GPIO10       50
69
 
#define OCTEON_IRQ_GPIO11       51
70
 
#define OCTEON_IRQ_GPIO12       52
71
 
#define OCTEON_IRQ_GPIO13       53
72
 
#define OCTEON_IRQ_GPIO14       54
73
 
#define OCTEON_IRQ_GPIO15       55
74
 
#define OCTEON_IRQ_MBOX0        56
75
 
#define OCTEON_IRQ_MBOX1        57
76
 
#define OCTEON_IRQ_UART0        58
77
 
#define OCTEON_IRQ_UART1        59
78
 
#define OCTEON_IRQ_PCI_INT0     60
79
 
#define OCTEON_IRQ_PCI_INT1     61
80
 
#define OCTEON_IRQ_PCI_INT2     62
81
 
#define OCTEON_IRQ_PCI_INT3     63
82
 
#define OCTEON_IRQ_PCI_MSI0     64
83
 
#define OCTEON_IRQ_PCI_MSI1     65
84
 
#define OCTEON_IRQ_PCI_MSI2     66
85
 
#define OCTEON_IRQ_PCI_MSI3     67
86
 
#define OCTEON_IRQ_RESERVED68   68      /* Summary of CIU_INT_SUM1 */
87
 
#define OCTEON_IRQ_TWSI         69
88
 
#define OCTEON_IRQ_RML          70
89
 
#define OCTEON_IRQ_TRACE        71
90
 
#define OCTEON_IRQ_GMX_DRP0     72
91
 
#define OCTEON_IRQ_GMX_DRP1     73
92
 
#define OCTEON_IRQ_IPD_DRP      74
93
 
#define OCTEON_IRQ_KEY_ZERO     75
94
 
#define OCTEON_IRQ_TIMER0       76
95
 
#define OCTEON_IRQ_TIMER1       77
96
 
#define OCTEON_IRQ_TIMER2       78
97
 
#define OCTEON_IRQ_TIMER3       79
98
 
#define OCTEON_IRQ_USB0         80
99
 
#define OCTEON_IRQ_PCM          81
100
 
#define OCTEON_IRQ_MPI          82
101
 
#define OCTEON_IRQ_TWSI2        83
102
 
#define OCTEON_IRQ_POWIQ        84
103
 
#define OCTEON_IRQ_IPDPPTHR     85
104
 
#define OCTEON_IRQ_MII0         86
105
 
#define OCTEON_IRQ_BOOTDMA      87
106
 
/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107
 
#define OCTEON_IRQ_WDOG0        88
108
 
#define OCTEON_IRQ_WDOG1        89
109
 
#define OCTEON_IRQ_WDOG2        90
110
 
#define OCTEON_IRQ_WDOG3        91
111
 
#define OCTEON_IRQ_WDOG4        92
112
 
#define OCTEON_IRQ_WDOG5        93
113
 
#define OCTEON_IRQ_WDOG6        94
114
 
#define OCTEON_IRQ_WDOG7        95
115
 
#define OCTEON_IRQ_WDOG8        96
116
 
#define OCTEON_IRQ_WDOG9        97
117
 
#define OCTEON_IRQ_WDOG10       98
118
 
#define OCTEON_IRQ_WDOG11       99
119
 
#define OCTEON_IRQ_WDOG12       100
120
 
#define OCTEON_IRQ_WDOG13       101
121
 
#define OCTEON_IRQ_WDOG14       102
122
 
#define OCTEON_IRQ_WDOG15       103
123
 
#define OCTEON_IRQ_UART2        104
124
 
#define OCTEON_IRQ_USB1         105
125
 
#define OCTEON_IRQ_MII1         106
126
 
#define OCTEON_IRQ_RESERVED107  107
127
 
#define OCTEON_IRQ_RESERVED108  108
128
 
#define OCTEON_IRQ_RESERVED109  109
129
 
#define OCTEON_IRQ_RESERVED110  110
130
 
#define OCTEON_IRQ_RESERVED111  111
131
 
#define OCTEON_IRQ_RESERVED112  112
132
 
#define OCTEON_IRQ_RESERVED113  113
133
 
#define OCTEON_IRQ_RESERVED114  114
134
 
#define OCTEON_IRQ_RESERVED115  115
135
 
#define OCTEON_IRQ_RESERVED116  116
136
 
#define OCTEON_IRQ_RESERVED117  117
137
 
#define OCTEON_IRQ_RESERVED118  118
138
 
#define OCTEON_IRQ_RESERVED119  119
139
 
#define OCTEON_IRQ_RESERVED120  120
140
 
#define OCTEON_IRQ_RESERVED121  121
141
 
#define OCTEON_IRQ_RESERVED122  122
142
 
#define OCTEON_IRQ_RESERVED123  123
143
 
#define OCTEON_IRQ_RESERVED124  124
144
 
#define OCTEON_IRQ_RESERVED125  125
145
 
#define OCTEON_IRQ_RESERVED126  126
146
 
#define OCTEON_IRQ_RESERVED127  127
147
 
#define OCTEON_IRQ_RESERVED128  128
148
 
#define OCTEON_IRQ_RESERVED129  129
149
 
#define OCTEON_IRQ_RESERVED130  130
150
 
#define OCTEON_IRQ_RESERVED131  131
151
 
#define OCTEON_IRQ_RESERVED132  132
152
 
#define OCTEON_IRQ_RESERVED133  133
153
 
#define OCTEON_IRQ_RESERVED134  134
154
 
#define OCTEON_IRQ_RESERVED135  135
155
 
#define OCTEON_IRQ_RESERVED136  136
156
 
#define OCTEON_IRQ_RESERVED137  137
157
 
#define OCTEON_IRQ_RESERVED138  138
158
 
#define OCTEON_IRQ_RESERVED139  139
159
 
#define OCTEON_IRQ_RESERVED140  140
160
 
#define OCTEON_IRQ_RESERVED141  141
161
 
#define OCTEON_IRQ_RESERVED142  142
162
 
#define OCTEON_IRQ_RESERVED143  143
163
 
#define OCTEON_IRQ_RESERVED144  144
164
 
#define OCTEON_IRQ_RESERVED145  145
165
 
#define OCTEON_IRQ_RESERVED146  146
166
 
#define OCTEON_IRQ_RESERVED147  147
167
 
#define OCTEON_IRQ_RESERVED148  148
168
 
#define OCTEON_IRQ_RESERVED149  149
169
 
#define OCTEON_IRQ_RESERVED150  150
170
 
#define OCTEON_IRQ_RESERVED151  151
 
14
enum octeon_irq {
 
15
/* 1 - 8 represent the 8 MIPS standard interrupt sources */
 
16
        OCTEON_IRQ_SW0 = 1,
 
17
        OCTEON_IRQ_SW1,
 
18
/* CIU0, CUI2, CIU4 are 3, 4, 5 */
 
19
        OCTEON_IRQ_5 = 6,
 
20
        OCTEON_IRQ_PERF,
 
21
        OCTEON_IRQ_TIMER,
 
22
/* sources in CIU_INTX_EN0 */
 
23
        OCTEON_IRQ_WORKQ0,
 
24
        OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
 
25
        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
 
26
        OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
 
27
        OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
 
28
        OCTEON_IRQ_MBOX1,
 
29
        OCTEON_IRQ_UART0,
 
30
        OCTEON_IRQ_UART1,
 
31
        OCTEON_IRQ_UART2,
 
32
        OCTEON_IRQ_PCI_INT0,
 
33
        OCTEON_IRQ_PCI_INT1,
 
34
        OCTEON_IRQ_PCI_INT2,
 
35
        OCTEON_IRQ_PCI_INT3,
 
36
        OCTEON_IRQ_PCI_MSI0,
 
37
        OCTEON_IRQ_PCI_MSI1,
 
38
        OCTEON_IRQ_PCI_MSI2,
 
39
        OCTEON_IRQ_PCI_MSI3,
 
40
 
 
41
        OCTEON_IRQ_TWSI,
 
42
        OCTEON_IRQ_TWSI2,
 
43
        OCTEON_IRQ_RML,
 
44
        OCTEON_IRQ_TRACE0,
 
45
        OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
 
46
        OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
 
47
        OCTEON_IRQ_KEY_ZERO,
 
48
        OCTEON_IRQ_TIMER0,
 
49
        OCTEON_IRQ_TIMER1,
 
50
        OCTEON_IRQ_TIMER2,
 
51
        OCTEON_IRQ_TIMER3,
 
52
        OCTEON_IRQ_USB0,
 
53
        OCTEON_IRQ_USB1,
 
54
        OCTEON_IRQ_PCM,
 
55
        OCTEON_IRQ_MPI,
 
56
        OCTEON_IRQ_POWIQ,
 
57
        OCTEON_IRQ_IPDPPTHR,
 
58
        OCTEON_IRQ_MII0,
 
59
        OCTEON_IRQ_MII1,
 
60
        OCTEON_IRQ_BOOTDMA,
 
61
 
 
62
        OCTEON_IRQ_NAND,
 
63
        OCTEON_IRQ_MIO,         /* Summary of MIO_BOOT_ERR */
 
64
        OCTEON_IRQ_IOB,         /* Summary of IOB_INT_SUM */
 
65
        OCTEON_IRQ_FPA,         /* Summary of FPA_INT_SUM */
 
66
        OCTEON_IRQ_POW,         /* Summary of POW_ECC_ERR */
 
67
        OCTEON_IRQ_L2C,         /* Summary of L2C_INT_STAT */
 
68
        OCTEON_IRQ_IPD,         /* Summary of IPD_INT_SUM */
 
69
        OCTEON_IRQ_PIP,         /* Summary of PIP_INT_REG */
 
70
        OCTEON_IRQ_PKO,         /* Summary of PKO_REG_ERROR */
 
71
        OCTEON_IRQ_ZIP,         /* Summary of ZIP_ERROR */
 
72
        OCTEON_IRQ_TIM,         /* Summary of TIM_REG_ERROR */
 
73
        OCTEON_IRQ_RAD,         /* Summary of RAD_REG_ERROR */
 
74
        OCTEON_IRQ_KEY,         /* Summary of KEY_INT_SUM */
 
75
        OCTEON_IRQ_DFA,         /* Summary of DFA */
 
76
        OCTEON_IRQ_USBCTL,      /* Summary of USBN0_INT_SUM */
 
77
        OCTEON_IRQ_SLI,         /* Summary of SLI_INT_SUM */
 
78
        OCTEON_IRQ_DPI,         /* Summary of DPI_INT_SUM */
 
79
        OCTEON_IRQ_AGX0,        /* Summary of GMX0*+PCS0_INT*_REG */
 
80
        OCTEON_IRQ_AGL  = OCTEON_IRQ_AGX0 + 5,
 
81
        OCTEON_IRQ_PTP,
 
82
        OCTEON_IRQ_PEM0,
 
83
        OCTEON_IRQ_PEM1,
 
84
        OCTEON_IRQ_SRIO0,
 
85
        OCTEON_IRQ_SRIO1,
 
86
        OCTEON_IRQ_LMC0,
 
87
        OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4,           /* Summary of DFM */
 
88
        OCTEON_IRQ_RST,
 
89
};
171
90
 
172
91
#ifdef CONFIG_PCI_MSI
173
 
/* 152 - 215 represent the MSI interrupts 0-63 */
174
 
#define OCTEON_IRQ_MSI_BIT0     152
175
 
#define OCTEON_IRQ_MSI_LAST     (OCTEON_IRQ_MSI_BIT0 + 255)
 
92
/* 152 - 407 represent the MSI interrupts 0-255 */
 
93
#define OCTEON_IRQ_MSI_BIT0     (OCTEON_IRQ_RST + 1)
176
94
 
177
 
#define OCTEON_IRQ_LAST         (OCTEON_IRQ_MSI_LAST + 1)
 
95
#define OCTEON_IRQ_MSI_LAST      (OCTEON_IRQ_MSI_BIT0 + 255)
 
96
#define OCTEON_IRQ_LAST          (OCTEON_IRQ_MSI_LAST + 1)
178
97
#else
179
 
#define OCTEON_IRQ_LAST         152
 
98
#define OCTEON_IRQ_LAST         (OCTEON_IRQ_RST + 1)
180
99
#endif
181
100
 
182
101
#endif