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  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno
  • Date: 2011-06-07 12:14:05 UTC
  • mfrom: (43.1.9 sid)
  • Revision ID: james.westby@ubuntu.com-20110607121405-i3h1rd7nrnd2b73h
Tags: 2.6.39-2
http://bugs.debian.org/627492
http://bugs.debian.org/596626
http://bugs.debian.org/628932
http://bugs.debian.org/628191
http://bugs.debian.org/627837
http://bugs.debian.org/622997
http://bugs.debian.org/622745
http://bugs.debian.org/619827
http://bugs.debian.org/629401
[ Ben Hutchings ]
* [x86] Enable BACKLIGHT_APPLE, replacing BACKLIGHT_MBP_NVIDIA
  (Closes: #627492)
* cgroups: Disable memory resource controller by default. Allow it
  to be enabled using kernel parameter 'cgroup_enable=memory'.
* rt2800usb: Enable support for more USB devices including
  Linksys WUSB600N (Closes: #596626) (this change was accidentally
  omitted from 2.6.39-1)
* [x86] Remove Celeron from list of processors supporting PAE. Most
  'Celeron M' models do not.
* Update debconf template translations:
  - Swedish (Martin Bagge) (Closes: #628932)
  - French (David Prévot) (Closes: #628191)
* aufs: Update for 2.6.39 (Closes: #627837)
* Add stable 2.6.39.1, including:
  - ext4: dont set PageUptodate in ext4_end_bio()
  - pata_cmd64x: fix boot crash on parisc (Closes: #622997, #622745)
  - ext3: Fix fs corruption when make_indexed_dir() fails
  - netfilter: nf_ct_sip: validate Content-Length in TCP SIP messages
  - sctp: fix race between sctp_bind_addr_free() and
    sctp_bind_addr_conflict()
  - sctp: fix memory leak of the ASCONF queue when free asoc
  - md/bitmap: fix saving of events_cleared and other state
  - cdc_acm: Fix oops when Droids MuIn LCD is connected
  - cx88: Fix conversion from BKL to fine-grained locks (Closes: #619827)
  - keys: Set cred->user_ns in key_replace_session_keyring (CVE-2011-2184)
  - tmpfs: fix race between truncate and writepage
  - nfs41: Correct offset for LAYOUTCOMMIT
  - xen/mmu: fix a race window causing leave_mm BUG()
  - ext4: fix possible use-after-free in ext4_remove_li_request()
  For the complete list of changes, see:
   http://www.kernel.org/pub/linux/kernel/v2.6/ChangeLog-2.6.39.1
* Bump ABI to 2
* netfilter: Enable IP_SET, IP_SET_BITMAP_IP, IP_SET_BITMAP_IPMAC,
  IP_SET_BITMAP_PORT, IP_SET_HASH_IP, IP_SET_HASH_IPPORT,
  IP_SET_HASH_IPPORTIP, IP_SET_HASH_IPPORTNET, IP_SET_HASH_NET,
  IP_SET_HASH_NETPORT, IP_SET_LIST_SET, NETFILTER_XT_SET as modules
  (Closes: #629401)

[ Aurelien Jarno ]
* [mipsel/loongson-2f] Disable_SCSI_LPFC to workaround GCC ICE.

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Lines of Context:
drivers/net/jme.c
161
161
}
162
162
 
163
163
static inline void
 
164
jme_mac_rxclk_off(struct jme_adapter *jme)
 
165
{
 
166
        jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
 
167
        jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 
168
}
 
169
 
 
170
static inline void
 
171
jme_mac_rxclk_on(struct jme_adapter *jme)
 
172
{
 
173
        jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
 
174
        jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 
175
}
 
176
 
 
177
static inline void
 
178
jme_mac_txclk_off(struct jme_adapter *jme)
 
179
{
 
180
        jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
 
181
        jwrite32f(jme, JME_GHC, jme->reg_ghc);
 
182
}
 
183
 
 
184
static inline void
 
185
jme_mac_txclk_on(struct jme_adapter *jme)
 
186
{
 
187
        u32 speed = jme->reg_ghc & GHC_SPEED;
 
188
        if (speed == GHC_SPEED_1000M)
 
189
                jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 
190
        else
 
191
                jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 
192
        jwrite32f(jme, JME_GHC, jme->reg_ghc);
 
193
}
 
194
 
 
195
static inline void
 
196
jme_reset_ghc_speed(struct jme_adapter *jme)
 
197
{
 
198
        jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
 
199
        jwrite32f(jme, JME_GHC, jme->reg_ghc);
 
200
}
 
201
 
 
202
static inline void
 
203
jme_reset_250A2_workaround(struct jme_adapter *jme)
 
204
{
 
205
        jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 
206
                             GPREG1_RSSPATCH);
 
207
        jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 
208
}
 
209
 
 
210
static inline void
 
211
jme_assert_ghc_reset(struct jme_adapter *jme)
 
212
{
 
213
        jme->reg_ghc |= GHC_SWRST;
 
214
        jwrite32f(jme, JME_GHC, jme->reg_ghc);
 
215
}
 
216
 
 
217
static inline void
 
218
jme_clear_ghc_reset(struct jme_adapter *jme)
 
219
{
 
220
        jme->reg_ghc &= ~GHC_SWRST;
 
221
        jwrite32f(jme, JME_GHC, jme->reg_ghc);
 
222
}
 
223
 
 
224
static inline void
164
225
jme_reset_mac_processor(struct jme_adapter *jme)
165
226
{
166
227
        static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
168
229
        u32 gpreg0;
169
230
        int i;
170
231
 
171
 
        jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172
 
        udelay(2);
173
 
        jwrite32(jme, JME_GHC, jme->reg_ghc);
 
232
        jme_reset_ghc_speed(jme);
 
233
        jme_reset_250A2_workaround(jme);
 
234
 
 
235
        jme_mac_rxclk_on(jme);
 
236
        jme_mac_txclk_on(jme);
 
237
        udelay(1);
 
238
        jme_assert_ghc_reset(jme);
 
239
        udelay(1);
 
240
        jme_mac_rxclk_off(jme);
 
241
        jme_mac_txclk_off(jme);
 
242
        udelay(1);
 
243
        jme_clear_ghc_reset(jme);
 
244
        udelay(1);
 
245
        jme_mac_rxclk_on(jme);
 
246
        jme_mac_txclk_on(jme);
 
247
        udelay(1);
 
248
        jme_mac_rxclk_off(jme);
 
249
        jme_mac_txclk_off(jme);
174
250
 
175
251
        jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176
252
        jwrite32(jme, JME_RXDBA_HI, 0x00000000);
190
266
        else
191
267
                gpreg0 = GPREG0_DEFAULT;
192
268
        jwrite32(jme, JME_GPREG0, gpreg0);
193
 
        jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194
 
}
195
 
 
196
 
static inline void
197
 
jme_reset_ghc_speed(struct jme_adapter *jme)
198
 
{
199
 
        jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200
 
        jwrite32(jme, JME_GHC, jme->reg_ghc);
201
269
}
202
270
 
203
271
static inline void
205
273
{
206
274
        jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207
275
        pci_set_power_state(jme->pdev, PCI_D0);
208
 
        pci_enable_wake(jme->pdev, PCI_D0, false);
 
276
        device_set_wakeup_enable(&jme->pdev->dev, false);
209
277
}
210
278
 
211
279
static int
336
404
}
337
405
 
338
406
static inline void
339
 
jme_set_phyfifoa(struct jme_adapter *jme)
 
407
jme_set_phyfifo_5level(struct jme_adapter *jme)
340
408
{
341
409
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342
410
}
343
411
 
344
412
static inline void
345
 
jme_set_phyfifob(struct jme_adapter *jme)
 
413
jme_set_phyfifo_8level(struct jme_adapter *jme)
346
414
{
347
415
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348
416
}
351
419
jme_check_link(struct net_device *netdev, int testonly)
352
420
{
353
421
        struct jme_adapter *jme = netdev_priv(netdev);
354
 
        u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
 
422
        u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
355
423
        char linkmsg[64];
356
424
        int rc = 0;
357
425
 
414
482
 
415
483
                jme->phylink = phylink;
416
484
 
417
 
                ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
418
 
                                GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
419
 
                                GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
 
485
                /*
 
486
                 * The speed/duplex setting of jme->reg_ghc already cleared
 
487
                 * by jme_reset_mac_processor()
 
488
                 */
420
489
                switch (phylink & PHY_LINK_SPEED_MASK) {
421
490
                case PHY_LINK_SPEED_10M:
422
 
                        ghc |= GHC_SPEED_10M |
423
 
                                GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 
491
                        jme->reg_ghc |= GHC_SPEED_10M;
424
492
                        strcat(linkmsg, "10 Mbps, ");
425
493
                        break;
426
494
                case PHY_LINK_SPEED_100M:
427
 
                        ghc |= GHC_SPEED_100M |
428
 
                                GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 
495
                        jme->reg_ghc |= GHC_SPEED_100M;
429
496
                        strcat(linkmsg, "100 Mbps, ");
430
497
                        break;
431
498
                case PHY_LINK_SPEED_1000M:
432
 
                        ghc |= GHC_SPEED_1000M |
433
 
                                GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 
499
                        jme->reg_ghc |= GHC_SPEED_1000M;
434
500
                        strcat(linkmsg, "1000 Mbps, ");
435
501
                        break;
436
502
                default:
439
505
 
440
506
                if (phylink & PHY_LINK_DUPLEX) {
441
507
                        jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
442
 
                        ghc |= GHC_DPX;
 
508
                        jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
 
509
                        jme->reg_ghc |= GHC_DPX;
443
510
                } else {
444
511
                        jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
445
512
                                                TXMCS_BACKOFF |
446
513
                                                TXMCS_CARRIERSENSE |
447
514
                                                TXMCS_COLLISION);
448
 
                        jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
449
 
                                ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450
 
                                TXTRHD_TXREN |
451
 
                                ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
 
515
                        jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
452
516
                }
453
517
 
454
 
                gpreg1 = GPREG1_DEFAULT;
 
518
                jwrite32(jme, JME_GHC, jme->reg_ghc);
 
519
 
455
520
                if (is_buggy250(jme->pdev->device, jme->chiprev)) {
 
521
                        jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 
522
                                             GPREG1_RSSPATCH);
456
523
                        if (!(phylink & PHY_LINK_DUPLEX))
457
 
                                gpreg1 |= GPREG1_HALFMODEPATCH;
 
524
                                jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
458
525
                        switch (phylink & PHY_LINK_SPEED_MASK) {
459
526
                        case PHY_LINK_SPEED_10M:
460
 
                                jme_set_phyfifoa(jme);
461
 
                                gpreg1 |= GPREG1_RSSPATCH;
 
527
                                jme_set_phyfifo_8level(jme);
 
528
                                jme->reg_gpreg1 |= GPREG1_RSSPATCH;
462
529
                                break;
463
530
                        case PHY_LINK_SPEED_100M:
464
 
                                jme_set_phyfifob(jme);
465
 
                                gpreg1 |= GPREG1_RSSPATCH;
 
531
                                jme_set_phyfifo_5level(jme);
 
532
                                jme->reg_gpreg1 |= GPREG1_RSSPATCH;
466
533
                                break;
467
534
                        case PHY_LINK_SPEED_1000M:
468
 
                                jme_set_phyfifoa(jme);
 
535
                                jme_set_phyfifo_8level(jme);
469
536
                                break;
470
537
                        default:
471
538
                                break;
472
539
                        }
473
540
                }
474
 
 
475
 
                jwrite32(jme, JME_GPREG1, gpreg1);
476
 
                jwrite32(jme, JME_GHC, ghc);
477
 
                jme->reg_ghc = ghc;
 
541
                jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
478
542
 
479
543
                strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
480
544
                                        "Full-Duplex, " :
613
677
         * Enable TX Engine
614
678
         */
615
679
        wmb();
616
 
        jwrite32(jme, JME_TXCS, jme->reg_txcs |
 
680
        jwrite32f(jme, JME_TXCS, jme->reg_txcs |
617
681
                                TXCS_SELECT_QUEUE0 |
618
682
                                TXCS_ENABLE);
619
683
 
 
684
        /*
 
685
         * Start clock for TX MAC Processor
 
686
         */
 
687
        jme_mac_txclk_on(jme);
620
688
}
621
689
 
622
690
static inline void
651
719
 
652
720
        if (!i)
653
721
                pr_err("Disable TX engine timeout\n");
 
722
 
 
723
        /*
 
724
         * Stop clock for TX MAC Processor
 
725
         */
 
726
        jme_mac_txclk_off(jme);
654
727
}
655
728
 
656
729
static void
825
898
        /*
826
899
         * Setup Unicast Filter
827
900
         */
 
901
        jme_set_unicastaddr(jme->dev);
828
902
        jme_set_multi(jme->dev);
829
903
 
830
904
        /*
831
905
         * Enable RX Engine
832
906
         */
833
907
        wmb();
834
 
        jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 
908
        jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
835
909
                                RXCS_QUEUESEL_Q0 |
836
910
                                RXCS_ENABLE |
837
911
                                RXCS_QST);
 
912
 
 
913
        /*
 
914
         * Start clock for RX MAC Processor
 
915
         */
 
916
        jme_mac_rxclk_on(jme);
838
917
}
839
918
 
840
919
static inline void
871
950
        if (!i)
872
951
                pr_err("Disable RX engine timeout\n");
873
952
 
 
953
        /*
 
954
         * Stop clock for RX MAC Processor
 
955
         */
 
956
        jme_mac_rxclk_off(jme);
 
957
}
 
958
 
 
959
static u16
 
960
jme_udpsum(struct sk_buff *skb)
 
961
{
 
962
        u16 csum = 0xFFFFu;
 
963
 
 
964
        if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
 
965
                return csum;
 
966
        if (skb->protocol != htons(ETH_P_IP))
 
967
                return csum;
 
968
        skb_set_network_header(skb, ETH_HLEN);
 
969
        if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
 
970
            (skb->len < (ETH_HLEN +
 
971
                        (ip_hdr(skb)->ihl << 2) +
 
972
                        sizeof(struct udphdr)))) {
 
973
                skb_reset_network_header(skb);
 
974
                return csum;
 
975
        }
 
976
        skb_set_transport_header(skb,
 
977
                        ETH_HLEN + (ip_hdr(skb)->ihl << 2));
 
978
        csum = udp_hdr(skb)->check;
 
979
        skb_reset_transport_header(skb);
 
980
        skb_reset_network_header(skb);
 
981
 
 
982
        return csum;
874
983
}
875
984
 
876
985
static int
877
 
jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
 
986
jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
878
987
{
879
988
        if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
880
989
                return false;
887
996
        }
888
997
 
889
998
        if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
890
 
                        == RXWBFLAG_UDPON)) {
 
999
                        == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
891
1000
                if (flags & RXWBFLAG_IPV4)
892
1001
                        netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
893
1002
                return false;
935
1044
                skb_put(skb, framesize);
936
1045
                skb->protocol = eth_type_trans(skb, jme->dev);
937
1046
 
938
 
                if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
 
1047
                if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
939
1048
                        skb->ip_summed = CHECKSUM_UNNECESSARY;
940
1049
                else
941
1050
                        skb_checksum_none_assert(skb);
1207
1316
        tasklet_disable(&jme->rxempty_task);
1208
1317
 
1209
1318
        if (netif_carrier_ok(netdev)) {
1210
 
                jme_reset_ghc_speed(jme);
1211
1319
                jme_disable_rx_engine(jme);
1212
1320
                jme_disable_tx_engine(jme);
1213
1321
                jme_reset_mac_processor(jme);
1577
1685
}
1578
1686
 
1579
1687
static inline void
 
1688
jme_new_phy_on(struct jme_adapter *jme)
 
1689
{
 
1690
        u32 reg;
 
1691
 
 
1692
        reg = jread32(jme, JME_PHY_PWR);
 
1693
        reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
 
1694
                 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
 
1695
        jwrite32(jme, JME_PHY_PWR, reg);
 
1696
 
 
1697
        pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
 
1698
        reg &= ~PE1_GPREG0_PBG;
 
1699
        reg |= PE1_GPREG0_ENBG;
 
1700
        pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
 
1701
}
 
1702
 
 
1703
static inline void
 
1704
jme_new_phy_off(struct jme_adapter *jme)
 
1705
{
 
1706
        u32 reg;
 
1707
 
 
1708
        reg = jread32(jme, JME_PHY_PWR);
 
1709
        reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
 
1710
               PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
 
1711
        jwrite32(jme, JME_PHY_PWR, reg);
 
1712
 
 
1713
        pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
 
1714
        reg &= ~PE1_GPREG0_PBG;
 
1715
        reg |= PE1_GPREG0_PDD3COLD;
 
1716
        pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
 
1717
}
 
1718
 
 
1719
static inline void
1580
1720
jme_phy_on(struct jme_adapter *jme)
1581
1721
{
1582
1722
        u32 bmcr;
1584
1724
        bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1585
1725
        bmcr &= ~BMCR_PDOWN;
1586
1726
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
 
1727
 
 
1728
        if (new_phy_power_ctrl(jme->chip_main_rev))
 
1729
                jme_new_phy_on(jme);
 
1730
}
 
1731
 
 
1732
static inline void
 
1733
jme_phy_off(struct jme_adapter *jme)
 
1734
{
 
1735
        u32 bmcr;
 
1736
 
 
1737
        bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
 
1738
        bmcr |= BMCR_PDOWN;
 
1739
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
 
1740
 
 
1741
        if (new_phy_power_ctrl(jme->chip_main_rev))
 
1742
                jme_new_phy_off(jme);
1587
1743
}
1588
1744
 
1589
1745
static int
1606
1762
 
1607
1763
        jme_start_irq(jme);
1608
1764
 
1609
 
        if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1610
 
                jme_phy_on(jme);
 
1765
        jme_phy_on(jme);
 
1766
        if (test_bit(JME_FLAG_SSET, &jme->flags))
1611
1767
                jme_set_settings(netdev, &jme->old_ecmd);
1612
 
        } else {
 
1768
        else
1613
1769
                jme_reset_phy_processor(jme);
1614
 
        }
1615
1770
 
1616
1771
        jme_reset_link(jme);
1617
1772
 
1657
1812
        }
1658
1813
}
1659
1814
 
1660
 
static inline void
1661
 
jme_phy_off(struct jme_adapter *jme)
1662
 
{
1663
 
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1664
 
}
1665
 
 
1666
1815
static void
1667
1816
jme_powersave_phy(struct jme_adapter *jme)
1668
1817
{
1696
1845
        tasklet_disable(&jme->rxclean_task);
1697
1846
        tasklet_disable(&jme->rxempty_task);
1698
1847
 
1699
 
        jme_reset_ghc_speed(jme);
1700
1848
        jme_disable_rx_engine(jme);
1701
1849
        jme_disable_tx_engine(jme);
1702
1850
        jme_reset_mac_processor(jme);
1993
2141
        return NETDEV_TX_OK;
1994
2142
}
1995
2143
 
 
2144
static void
 
2145
jme_set_unicastaddr(struct net_device *netdev)
 
2146
{
 
2147
        struct jme_adapter *jme = netdev_priv(netdev);
 
2148
        u32 val;
 
2149
 
 
2150
        val = (netdev->dev_addr[3] & 0xff) << 24 |
 
2151
              (netdev->dev_addr[2] & 0xff) << 16 |
 
2152
              (netdev->dev_addr[1] & 0xff) <<  8 |
 
2153
              (netdev->dev_addr[0] & 0xff);
 
2154
        jwrite32(jme, JME_RXUMA_LO, val);
 
2155
        val = (netdev->dev_addr[5] & 0xff) << 8 |
 
2156
              (netdev->dev_addr[4] & 0xff);
 
2157
        jwrite32(jme, JME_RXUMA_HI, val);
 
2158
}
 
2159
 
1996
2160
static int
1997
2161
jme_set_macaddr(struct net_device *netdev, void *p)
1998
2162
{
1999
2163
        struct jme_adapter *jme = netdev_priv(netdev);
2000
2164
        struct sockaddr *addr = p;
2001
 
        u32 val;
2002
2165
 
2003
2166
        if (netif_running(netdev))
2004
2167
                return -EBUSY;
2005
2168
 
2006
2169
        spin_lock_bh(&jme->macaddr_lock);
2007
2170
        memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2008
 
 
2009
 
        val = (addr->sa_data[3] & 0xff) << 24 |
2010
 
              (addr->sa_data[2] & 0xff) << 16 |
2011
 
              (addr->sa_data[1] & 0xff) <<  8 |
2012
 
              (addr->sa_data[0] & 0xff);
2013
 
        jwrite32(jme, JME_RXUMA_LO, val);
2014
 
        val = (addr->sa_data[5] & 0xff) << 8 |
2015
 
              (addr->sa_data[4] & 0xff);
2016
 
        jwrite32(jme, JME_RXUMA_HI, val);
 
2171
        jme_set_unicastaddr(netdev);
2017
2172
        spin_unlock_bh(&jme->macaddr_lock);
2018
2173
 
2019
2174
        return 0;
2383
2538
 
2384
2539
        jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2385
2540
 
 
2541
        device_set_wakeup_enable(&jme->pdev->dev, jme->reg_pmcs);
 
2542
 
2386
2543
        return 0;
2387
2544
}
2388
2545
 
2731
2888
 
2732
2889
        jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2733
2890
        jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
 
2891
        jme->chip_main_rev = jme->chiprev & 0xF;
 
2892
        jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2734
2893
}
2735
2894
 
2736
2895
static const struct net_device_ops jme_netdev_ops = {
2880
3039
        jme->reg_rxmcs = RXMCS_DEFAULT;
2881
3040
        jme->reg_txpfc = 0;
2882
3041
        jme->reg_pmcs = PMCS_MFEN;
 
3042
        jme->reg_gpreg1 = GPREG1_DEFAULT;
2883
3043
        set_bit(JME_FLAG_TXCSUM, &jme->flags);
2884
3044
        set_bit(JME_FLAG_TSO, &jme->flags);
2885
3045
 
2936
3096
        jme->mii_if.mdio_write = jme_mdio_write;
2937
3097
 
2938
3098
        jme_clear_pm(jme);
2939
 
        jme_set_phyfifoa(jme);
2940
 
        pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
 
3099
        jme_set_phyfifo_5level(jme);
 
3100
        jme->pcirev = pdev->revision;
2941
3101
        if (!jme->fpgaver)
2942
3102
                jme_phy_init(jme);
2943
3103
        jme_phy_off(jme);
2964
3124
                goto err_out_unmap;
2965
3125
        }
2966
3126
 
2967
 
        netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
 
3127
        netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
2968
3128
                   (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2969
3129
                   "JMC250 Gigabit Ethernet" :
2970
3130
                   (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2971
3131
                   "JMC260 Fast Ethernet" : "Unknown",
2972
3132
                   (jme->fpgaver != 0) ? " (FPGA)" : "",
2973
3133
                   (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2974
 
                   jme->rev, netdev->dev_addr);
 
3134
                   jme->pcirev, netdev->dev_addr);
2975
3135
 
2976
3136
        return 0;
2977
3137
 
3014
3174
}
3015
3175
 
3016
3176
#ifdef CONFIG_PM
3017
 
static int
3018
 
jme_suspend(struct pci_dev *pdev, pm_message_t state)
 
3177
static int jme_suspend(struct device *dev)
3019
3178
{
 
3179
        struct pci_dev *pdev = to_pci_dev(dev);
3020
3180
        struct net_device *netdev = pci_get_drvdata(pdev);
3021
3181
        struct jme_adapter *jme = netdev_priv(netdev);
3022
3182
 
3035
3195
                        jme_polling_mode(jme);
3036
3196
 
3037
3197
                jme_stop_pcc_timer(jme);
3038
 
                jme_reset_ghc_speed(jme);
3039
3198
                jme_disable_rx_engine(jme);
3040
3199
                jme_disable_tx_engine(jme);
3041
3200
                jme_reset_mac_processor(jme);
3049
3208
        tasklet_hi_enable(&jme->rxclean_task);
3050
3209
        tasklet_hi_enable(&jme->rxempty_task);
3051
3210
 
3052
 
        pci_save_state(pdev);
3053
3211
        jme_powersave_phy(jme);
3054
 
        pci_enable_wake(jme->pdev, PCI_D3hot, true);
3055
 
        pci_set_power_state(pdev, PCI_D3hot);
3056
3212
 
3057
3213
        return 0;
3058
3214
}
3059
3215
 
3060
 
static int
3061
 
jme_resume(struct pci_dev *pdev)
 
3216
static int jme_resume(struct device *dev)
3062
3217
{
 
3218
        struct pci_dev *pdev = to_pci_dev(dev);
3063
3219
        struct net_device *netdev = pci_get_drvdata(pdev);
3064
3220
        struct jme_adapter *jme = netdev_priv(netdev);
3065
3221
 
3066
 
        jme_clear_pm(jme);
3067
 
        pci_restore_state(pdev);
 
3222
        jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
3068
3223
 
3069
 
        if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3070
 
                jme_phy_on(jme);
 
3224
        jme_phy_on(jme);
 
3225
        if (test_bit(JME_FLAG_SSET, &jme->flags))
3071
3226
                jme_set_settings(netdev, &jme->old_ecmd);
3072
 
        } else {
 
3227
        else
3073
3228
                jme_reset_phy_processor(jme);
3074
 
        }
3075
3229
 
3076
3230
        jme_start_irq(jme);
3077
3231
        netif_device_attach(netdev);
3082
3236
 
3083
3237
        return 0;
3084
3238
}
 
3239
 
 
3240
static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
 
3241
#define JME_PM_OPS (&jme_pm_ops)
 
3242
 
 
3243
#else
 
3244
 
 
3245
#define JME_PM_OPS NULL
3085
3246
#endif
3086
3247
 
3087
3248
static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3095
3256
        .id_table       = jme_pci_tbl,
3096
3257
        .probe          = jme_init_one,
3097
3258
        .remove         = __devexit_p(jme_remove_one),
3098
 
#ifdef CONFIG_PM
3099
 
        .suspend        = jme_suspend,
3100
 
        .resume         = jme_resume,
3101
 
#endif /* CONFIG_PM */
3102
3259
        .shutdown       = jme_shutdown,
 
3260
        .driver.pm      = JME_PM_OPS,
3103
3261
};
3104
3262
 
3105
3263
static int __init