35
38
#define TEGRA_ARM_INT_DIST_BASE 0x50041000
36
39
#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
38
50
#define TEGRA_DISPLAY_BASE 0x54200000
39
51
#define TEGRA_DISPLAY_SIZE SZ_256K
41
53
#define TEGRA_DISPLAY2_BASE 0x54240000
42
54
#define TEGRA_DISPLAY2_SIZE SZ_256K
44
65
#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
45
66
#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64