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  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno
  • Date: 2011-06-07 12:14:05 UTC
  • mfrom: (43.1.9 sid)
  • Revision ID: james.westby@ubuntu.com-20110607121405-i3h1rd7nrnd2b73h
Tags: 2.6.39-2
http://bugs.debian.org/627492
http://bugs.debian.org/596626
http://bugs.debian.org/628932
http://bugs.debian.org/628191
http://bugs.debian.org/627837
http://bugs.debian.org/622997
http://bugs.debian.org/622745
http://bugs.debian.org/619827
http://bugs.debian.org/629401
[ Ben Hutchings ]
* [x86] Enable BACKLIGHT_APPLE, replacing BACKLIGHT_MBP_NVIDIA
  (Closes: #627492)
* cgroups: Disable memory resource controller by default. Allow it
  to be enabled using kernel parameter 'cgroup_enable=memory'.
* rt2800usb: Enable support for more USB devices including
  Linksys WUSB600N (Closes: #596626) (this change was accidentally
  omitted from 2.6.39-1)
* [x86] Remove Celeron from list of processors supporting PAE. Most
  'Celeron M' models do not.
* Update debconf template translations:
  - Swedish (Martin Bagge) (Closes: #628932)
  - French (David Prévot) (Closes: #628191)
* aufs: Update for 2.6.39 (Closes: #627837)
* Add stable 2.6.39.1, including:
  - ext4: dont set PageUptodate in ext4_end_bio()
  - pata_cmd64x: fix boot crash on parisc (Closes: #622997, #622745)
  - ext3: Fix fs corruption when make_indexed_dir() fails
  - netfilter: nf_ct_sip: validate Content-Length in TCP SIP messages
  - sctp: fix race between sctp_bind_addr_free() and
    sctp_bind_addr_conflict()
  - sctp: fix memory leak of the ASCONF queue when free asoc
  - md/bitmap: fix saving of events_cleared and other state
  - cdc_acm: Fix oops when Droids MuIn LCD is connected
  - cx88: Fix conversion from BKL to fine-grained locks (Closes: #619827)
  - keys: Set cred->user_ns in key_replace_session_keyring (CVE-2011-2184)
  - tmpfs: fix race between truncate and writepage
  - nfs41: Correct offset for LAYOUTCOMMIT
  - xen/mmu: fix a race window causing leave_mm BUG()
  - ext4: fix possible use-after-free in ext4_remove_li_request()
  For the complete list of changes, see:
   http://www.kernel.org/pub/linux/kernel/v2.6/ChangeLog-2.6.39.1
* Bump ABI to 2
* netfilter: Enable IP_SET, IP_SET_BITMAP_IP, IP_SET_BITMAP_IPMAC,
  IP_SET_BITMAP_PORT, IP_SET_HASH_IP, IP_SET_HASH_IPPORT,
  IP_SET_HASH_IPPORTIP, IP_SET_HASH_IPPORTNET, IP_SET_HASH_NET,
  IP_SET_HASH_NETPORT, IP_SET_LIST_SET, NETFILTER_XT_SET as modules
  (Closes: #629401)

[ Aurelien Jarno ]
* [mipsel/loongson-2f] Disable_SCSI_LPFC to workaround GCC ICE.

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Lines of Context:
arch/mips/sgi-ip32/ip32-irq.c
130
130
 
131
131
static uint64_t crime_mask;
132
132
 
133
 
static inline void crime_enable_irq(unsigned int irq)
 
133
static inline void crime_enable_irq(struct irq_data *d)
134
134
{
135
 
        unsigned int bit = irq - CRIME_IRQ_BASE;
 
135
        unsigned int bit = d->irq - CRIME_IRQ_BASE;
136
136
 
137
137
        crime_mask |= 1 << bit;
138
138
        crime->imask = crime_mask;
139
139
}
140
140
 
141
 
static inline void crime_disable_irq(unsigned int irq)
 
141
static inline void crime_disable_irq(struct irq_data *d)
142
142
{
143
 
        unsigned int bit = irq - CRIME_IRQ_BASE;
 
143
        unsigned int bit = d->irq - CRIME_IRQ_BASE;
144
144
 
145
145
        crime_mask &= ~(1 << bit);
146
146
        crime->imask = crime_mask;
147
147
        flush_crime_bus();
148
148
}
149
149
 
150
 
static void crime_level_mask_and_ack_irq(unsigned int irq)
151
 
{
152
 
        crime_disable_irq(irq);
153
 
}
154
 
 
155
 
static void crime_level_end_irq(unsigned int irq)
156
 
{
157
 
        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
158
 
                crime_enable_irq(irq);
159
 
}
160
 
 
161
150
static struct irq_chip crime_level_interrupt = {
162
151
        .name           = "IP32 CRIME",
163
 
        .ack            = crime_level_mask_and_ack_irq,
164
 
        .mask           = crime_disable_irq,
165
 
        .mask_ack       = crime_level_mask_and_ack_irq,
166
 
        .unmask         = crime_enable_irq,
167
 
        .end            = crime_level_end_irq,
 
152
        .irq_mask       = crime_disable_irq,
 
153
        .irq_unmask     = crime_enable_irq,
168
154
};
169
155
 
170
 
static void crime_edge_mask_and_ack_irq(unsigned int irq)
 
156
static void crime_edge_mask_and_ack_irq(struct irq_data *d)
171
157
{
172
 
        unsigned int bit = irq - CRIME_IRQ_BASE;
 
158
        unsigned int bit = d->irq - CRIME_IRQ_BASE;
173
159
        uint64_t crime_int;
174
160
 
175
161
        /* Edge triggered interrupts must be cleared. */
176
 
 
177
162
        crime_int = crime->hard_int;
178
163
        crime_int &= ~(1 << bit);
179
164
        crime->hard_int = crime_int;
180
165
 
181
 
        crime_disable_irq(irq);
182
 
}
183
 
 
184
 
static void crime_edge_end_irq(unsigned int irq)
185
 
{
186
 
        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
187
 
                crime_enable_irq(irq);
 
166
        crime_disable_irq(d);
188
167
}
189
168
 
190
169
static struct irq_chip crime_edge_interrupt = {
191
170
        .name           = "IP32 CRIME",
192
 
        .ack            = crime_edge_mask_and_ack_irq,
193
 
        .mask           = crime_disable_irq,
194
 
        .mask_ack       = crime_edge_mask_and_ack_irq,
195
 
        .unmask         = crime_enable_irq,
196
 
        .end            = crime_edge_end_irq,
 
171
        .irq_ack        = crime_edge_mask_and_ack_irq,
 
172
        .irq_mask       = crime_disable_irq,
 
173
        .irq_mask_ack   = crime_edge_mask_and_ack_irq,
 
174
        .irq_unmask     = crime_enable_irq,
197
175
};
198
176
 
199
177
/*
204
182
 
205
183
static unsigned long macepci_mask;
206
184
 
207
 
static void enable_macepci_irq(unsigned int irq)
 
185
static void enable_macepci_irq(struct irq_data *d)
208
186
{
209
 
        macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
 
187
        macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
210
188
        mace->pci.control = macepci_mask;
211
 
        crime_mask |= 1 << (irq - CRIME_IRQ_BASE);
 
189
        crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
212
190
        crime->imask = crime_mask;
213
191
}
214
192
 
215
 
static void disable_macepci_irq(unsigned int irq)
 
193
static void disable_macepci_irq(struct irq_data *d)
216
194
{
217
 
        crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
 
195
        crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
218
196
        crime->imask = crime_mask;
219
197
        flush_crime_bus();
220
 
        macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
 
198
        macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
221
199
        mace->pci.control = macepci_mask;
222
200
        flush_mace_bus();
223
201
}
224
202
 
225
 
static void end_macepci_irq(unsigned int irq)
226
 
{
227
 
        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
228
 
                enable_macepci_irq(irq);
229
 
}
230
 
 
231
203
static struct irq_chip ip32_macepci_interrupt = {
232
204
        .name = "IP32 MACE PCI",
233
 
        .ack = disable_macepci_irq,
234
 
        .mask = disable_macepci_irq,
235
 
        .mask_ack = disable_macepci_irq,
236
 
        .unmask = enable_macepci_irq,
237
 
        .end = end_macepci_irq,
 
205
        .irq_mask = disable_macepci_irq,
 
206
        .irq_unmask = enable_macepci_irq,
238
207
};
239
208
 
240
209
/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
276
245
 
277
246
static unsigned long maceisa_mask;
278
247
 
279
 
static void enable_maceisa_irq(unsigned int irq)
 
248
static void enable_maceisa_irq(struct irq_data *d)
280
249
{
281
250
        unsigned int crime_int = 0;
282
251
 
283
 
        pr_debug("maceisa enable: %u\n", irq);
 
252
        pr_debug("maceisa enable: %u\n", d->irq);
284
253
 
285
 
        switch (irq) {
 
254
        switch (d->irq) {
286
255
        case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
287
256
                crime_int = MACE_AUDIO_INT;
288
257
                break;
296
265
        pr_debug("crime_int %08x enabled\n", crime_int);
297
266
        crime_mask |= crime_int;
298
267
        crime->imask = crime_mask;
299
 
        maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
 
268
        maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
300
269
        mace->perif.ctrl.imask = maceisa_mask;
301
270
}
302
271
 
303
 
static void disable_maceisa_irq(unsigned int irq)
 
272
static void disable_maceisa_irq(struct irq_data *d)
304
273
{
305
274
        unsigned int crime_int = 0;
306
275
 
307
 
        maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
 
276
        maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
308
277
        if (!(maceisa_mask & MACEISA_AUDIO_INT))
309
278
                crime_int |= MACE_AUDIO_INT;
310
279
        if (!(maceisa_mask & MACEISA_MISC_INT))
318
287
        flush_mace_bus();
319
288
}
320
289
 
321
 
static void mask_and_ack_maceisa_irq(unsigned int irq)
 
290
static void mask_and_ack_maceisa_irq(struct irq_data *d)
322
291
{
323
292
        unsigned long mace_int;
324
293
 
325
294
        /* edge triggered */
326
295
        mace_int = mace->perif.ctrl.istat;
327
 
        mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
 
296
        mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
328
297
        mace->perif.ctrl.istat = mace_int;
329
298
 
330
 
        disable_maceisa_irq(irq);
331
 
}
332
 
 
333
 
static void end_maceisa_irq(unsigned irq)
334
 
{
335
 
        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
336
 
                enable_maceisa_irq(irq);
 
299
        disable_maceisa_irq(d);
337
300
}
338
301
 
339
302
static struct irq_chip ip32_maceisa_level_interrupt = {
340
303
        .name           = "IP32 MACE ISA",
341
 
        .ack            = disable_maceisa_irq,
342
 
        .mask           = disable_maceisa_irq,
343
 
        .mask_ack       = disable_maceisa_irq,
344
 
        .unmask         = enable_maceisa_irq,
345
 
        .end            = end_maceisa_irq,
 
304
        .irq_mask       = disable_maceisa_irq,
 
305
        .irq_unmask     = enable_maceisa_irq,
346
306
};
347
307
 
348
308
static struct irq_chip ip32_maceisa_edge_interrupt = {
349
309
        .name           = "IP32 MACE ISA",
350
 
        .ack            = mask_and_ack_maceisa_irq,
351
 
        .mask           = disable_maceisa_irq,
352
 
        .mask_ack       = mask_and_ack_maceisa_irq,
353
 
        .unmask         = enable_maceisa_irq,
354
 
        .end            = end_maceisa_irq,
 
310
        .irq_ack        = mask_and_ack_maceisa_irq,
 
311
        .irq_mask       = disable_maceisa_irq,
 
312
        .irq_mask_ack   = mask_and_ack_maceisa_irq,
 
313
        .irq_unmask     = enable_maceisa_irq,
355
314
};
356
315
 
357
316
/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
358
317
 * bits 0-3 and 7 in the CRIME register.
359
318
 */
360
319
 
361
 
static void enable_mace_irq(unsigned int irq)
 
320
static void enable_mace_irq(struct irq_data *d)
362
321
{
363
 
        unsigned int bit = irq - CRIME_IRQ_BASE;
 
322
        unsigned int bit = d->irq - CRIME_IRQ_BASE;
364
323
 
365
324
        crime_mask |= (1 << bit);
366
325
        crime->imask = crime_mask;
367
326
}
368
327
 
369
 
static void disable_mace_irq(unsigned int irq)
 
328
static void disable_mace_irq(struct irq_data *d)
370
329
{
371
 
        unsigned int bit = irq - CRIME_IRQ_BASE;
 
330
        unsigned int bit = d->irq - CRIME_IRQ_BASE;
372
331
 
373
332
        crime_mask &= ~(1 << bit);
374
333
        crime->imask = crime_mask;
375
334
        flush_crime_bus();
376
335
}
377
336
 
378
 
static void end_mace_irq(unsigned int irq)
379
 
{
380
 
        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
381
 
                enable_mace_irq(irq);
382
 
}
383
 
 
384
337
static struct irq_chip ip32_mace_interrupt = {
385
338
        .name = "IP32 MACE",
386
 
        .ack = disable_mace_irq,
387
 
        .mask = disable_mace_irq,
388
 
        .mask_ack = disable_mace_irq,
389
 
        .unmask = enable_mace_irq,
390
 
        .end = end_mace_irq,
 
339
        .irq_mask = disable_mace_irq,
 
340
        .irq_unmask = enable_mace_irq,
391
341
};
392
342
 
393
343
static void ip32_unknown_interrupt(void)
501
451
        for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
502
452
                switch (irq) {
503
453
                case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
504
 
                        set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
505
 
                                handle_level_irq, "level");
 
454
                        irq_set_chip_and_handler_name(irq,
 
455
                                                      &ip32_mace_interrupt,
 
456
                                                      handle_level_irq,
 
457
                                                      "level");
506
458
                        break;
507
459
 
508
460
                case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
509
 
                        set_irq_chip_and_handler_name(irq,
510
 
                                &ip32_macepci_interrupt, handle_level_irq,
511
 
                                "level");
 
461
                        irq_set_chip_and_handler_name(irq,
 
462
                                                      &ip32_macepci_interrupt,
 
463
                                                      handle_level_irq,
 
464
                                                      "level");
512
465
                        break;
513
466
 
514
467
                case CRIME_CPUERR_IRQ:
515
468
                case CRIME_MEMERR_IRQ:
516
 
                        set_irq_chip_and_handler_name(irq,
517
 
                                &crime_level_interrupt, handle_level_irq,
518
 
                                "level");
 
469
                        irq_set_chip_and_handler_name(irq,
 
470
                                                      &crime_level_interrupt,
 
471
                                                      handle_level_irq,
 
472
                                                      "level");
519
473
                        break;
520
474
 
521
475
                case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
522
476
                case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
523
477
                case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
524
478
                case CRIME_VICE_IRQ:
525
 
                        set_irq_chip_and_handler_name(irq,
526
 
                                &crime_edge_interrupt, handle_edge_irq, "edge");
 
479
                        irq_set_chip_and_handler_name(irq,
 
480
                                                      &crime_edge_interrupt,
 
481
                                                      handle_edge_irq,
 
482
                                                      "edge");
527
483
                        break;
528
484
 
529
485
                case MACEISA_PARALLEL_IRQ:
530
486
                case MACEISA_SERIAL1_TDMAPR_IRQ:
531
487
                case MACEISA_SERIAL2_TDMAPR_IRQ:
532
 
                        set_irq_chip_and_handler_name(irq,
533
 
                                &ip32_maceisa_edge_interrupt, handle_edge_irq,
534
 
                                "edge");
 
488
                        irq_set_chip_and_handler_name(irq,
 
489
                                                      &ip32_maceisa_edge_interrupt,
 
490
                                                      handle_edge_irq,
 
491
                                                      "edge");
535
492
                        break;
536
493
 
537
494
                default:
538
 
                        set_irq_chip_and_handler_name(irq,
539
 
                                &ip32_maceisa_level_interrupt, handle_level_irq,
540
 
                                "level");
 
495
                        irq_set_chip_and_handler_name(irq,
 
496
                                                      &ip32_maceisa_level_interrupt,
 
497
                                                      handle_level_irq,
 
498
                                                      "level");
541
499
                        break;
542
500
                }
543
501
        }