211
221
static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
213
unsigned int cpu = 0;
223
unsigned int cpu = mpic_processor_id(mpic);
215
if (mpic->flags & MPIC_PRIMARY)
216
cpu = hard_smp_processor_id();
217
225
return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
220
228
static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
222
unsigned int cpu = 0;
224
if (mpic->flags & MPIC_PRIMARY)
225
cpu = hard_smp_processor_id();
230
unsigned int cpu = mpic_processor_id(mpic);
227
232
_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
365
370
if (fixup->base == NULL)
368
DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
369
source, irqflags, fixup->index);
373
DBG("startup_ht_interrupt(0x%x) index: %d\n",
374
source, fixup->index);
370
375
raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
371
376
/* Enable and configure */
372
377
writeb(0x10 + 2 * fixup->index, fixup->base + 2);
373
378
tmp = readl(fixup->base + 4);
375
if (irqflags & IRQ_LEVEL)
377
382
writel(tmp, fixup->base + 4);
378
383
raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
637
641
#ifdef CONFIG_SMP
638
642
/* Get the mpic structure from the IPI number */
639
static inline struct mpic * mpic_from_ipi(unsigned int ipi)
643
static inline struct mpic * mpic_from_ipi(struct irq_data *d)
641
return irq_to_desc(ipi)->chip_data;
645
return irq_data_get_irq_chip_data(d);
645
649
/* Get the mpic structure from the irq number */
646
650
static inline struct mpic * mpic_from_irq(unsigned int irq)
648
return irq_to_desc(irq)->chip_data;
652
return irq_get_chip_data(irq);
655
/* Get the mpic structure from the irq data */
656
static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
658
return irq_data_get_irq_chip_data(d);
651
661
/* Send an EOI */
663
void mpic_unmask_irq(unsigned int irq)
673
void mpic_unmask_irq(struct irq_data *d)
665
675
unsigned int loops = 100000;
666
struct mpic *mpic = mpic_from_irq(irq);
667
unsigned int src = mpic_irq_to_hw(irq);
676
struct mpic *mpic = mpic_from_irq_data(d);
677
unsigned int src = mpic_irq_to_hw(d->irq);
669
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
679
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
671
681
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
672
682
mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
681
691
} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
684
void mpic_mask_irq(unsigned int irq)
694
void mpic_mask_irq(struct irq_data *d)
686
696
unsigned int loops = 100000;
687
struct mpic *mpic = mpic_from_irq(irq);
688
unsigned int src = mpic_irq_to_hw(irq);
697
struct mpic *mpic = mpic_from_irq_data(d);
698
unsigned int src = mpic_irq_to_hw(d->irq);
690
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
700
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
692
702
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
693
703
mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
703
713
} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
706
void mpic_end_irq(unsigned int irq)
716
void mpic_end_irq(struct irq_data *d)
708
struct mpic *mpic = mpic_from_irq(irq);
718
struct mpic *mpic = mpic_from_irq_data(d);
711
DBG("%s: end_irq: %d\n", mpic->name, irq);
721
DBG("%s: end_irq: %d\n", mpic->name, d->irq);
713
723
/* We always EOI on end_irq() even for edge interrupts since that
714
724
* should only lower the priority, the MPIC should have properly
721
731
#ifdef CONFIG_MPIC_U3_HT_IRQS
723
static void mpic_unmask_ht_irq(unsigned int irq)
733
static void mpic_unmask_ht_irq(struct irq_data *d)
725
struct mpic *mpic = mpic_from_irq(irq);
726
unsigned int src = mpic_irq_to_hw(irq);
728
mpic_unmask_irq(irq);
730
if (irq_to_desc(irq)->status & IRQ_LEVEL)
735
struct mpic *mpic = mpic_from_irq_data(d);
736
unsigned int src = mpic_irq_to_hw(d->irq);
740
if (irqd_is_level_type(d))
731
741
mpic_ht_end_irq(mpic, src);
734
static unsigned int mpic_startup_ht_irq(unsigned int irq)
744
static unsigned int mpic_startup_ht_irq(struct irq_data *d)
736
struct mpic *mpic = mpic_from_irq(irq);
737
unsigned int src = mpic_irq_to_hw(irq);
746
struct mpic *mpic = mpic_from_irq_data(d);
747
unsigned int src = mpic_irq_to_hw(d->irq);
739
mpic_unmask_irq(irq);
740
mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
750
mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
745
static void mpic_shutdown_ht_irq(unsigned int irq)
755
static void mpic_shutdown_ht_irq(struct irq_data *d)
747
struct mpic *mpic = mpic_from_irq(irq);
748
unsigned int src = mpic_irq_to_hw(irq);
757
struct mpic *mpic = mpic_from_irq_data(d);
758
unsigned int src = mpic_irq_to_hw(d->irq);
750
mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
760
mpic_shutdown_ht_interrupt(mpic, src);
754
static void mpic_end_ht_irq(unsigned int irq)
764
static void mpic_end_ht_irq(struct irq_data *d)
756
struct mpic *mpic = mpic_from_irq(irq);
757
unsigned int src = mpic_irq_to_hw(irq);
766
struct mpic *mpic = mpic_from_irq_data(d);
767
unsigned int src = mpic_irq_to_hw(d->irq);
760
DBG("%s: end_irq: %d\n", mpic->name, irq);
770
DBG("%s: end_irq: %d\n", mpic->name, d->irq);
762
772
/* We always EOI on end_irq() even for edge interrupts since that
763
773
* should only lower the priority, the MPIC should have properly
764
774
* latched another edge interrupt coming in anyway
767
if (irq_to_desc(irq)->status & IRQ_LEVEL)
777
if (irqd_is_level_type(d))
768
778
mpic_ht_end_irq(mpic, src);
773
783
#ifdef CONFIG_SMP
775
static void mpic_unmask_ipi(unsigned int irq)
785
static void mpic_unmask_ipi(struct irq_data *d)
777
struct mpic *mpic = mpic_from_ipi(irq);
778
unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
787
struct mpic *mpic = mpic_from_ipi(d);
788
unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0];
780
DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
790
DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
781
791
mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
784
static void mpic_mask_ipi(unsigned int irq)
794
static void mpic_mask_ipi(struct irq_data *d)
786
796
/* NEVER disable an IPI... that's just plain wrong! */
789
static void mpic_end_ipi(unsigned int irq)
799
static void mpic_end_ipi(struct irq_data *d)
791
struct mpic *mpic = mpic_from_ipi(irq);
801
struct mpic *mpic = mpic_from_ipi(d);
794
804
* IPIs are marked IRQ_PER_CPU. This has the side effect of
803
813
#endif /* CONFIG_SMP */
805
int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
815
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
807
struct mpic *mpic = mpic_from_irq(irq);
808
unsigned int src = mpic_irq_to_hw(irq);
818
struct mpic *mpic = mpic_from_irq_data(d);
819
unsigned int src = mpic_irq_to_hw(d->irq);
810
821
if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
811
822
int cpuid = irq_choose_cpu(cpumask);
851
int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
862
int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
853
struct mpic *mpic = mpic_from_irq(virq);
854
unsigned int src = mpic_irq_to_hw(virq);
855
struct irq_desc *desc = irq_to_desc(virq);
864
struct mpic *mpic = mpic_from_irq_data(d);
865
unsigned int src = mpic_irq_to_hw(d->irq);
856
866
unsigned int vecpri, vold, vnew;
858
868
DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
859
mpic, virq, src, flow_type);
869
mpic, d->irq, src, flow_type);
861
871
if (src >= mpic->irq_count)
867
877
if (flow_type == IRQ_TYPE_NONE)
868
878
flow_type = IRQ_TYPE_LEVEL_LOW;
870
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
871
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
872
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
873
desc->status |= IRQ_LEVEL;
880
irqd_set_trigger_type(d, flow_type);
875
882
if (mpic_is_ht_interrupt(mpic, src))
876
883
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
906
913
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
916
void mpic_set_destination(unsigned int virq, unsigned int cpuid)
918
struct mpic *mpic = mpic_from_irq(virq);
919
unsigned int src = mpic_irq_to_hw(virq);
921
DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
922
mpic, virq, src, cpuid);
924
if (src >= mpic->irq_count)
927
mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
909
930
static struct irq_chip mpic_irq_chip = {
910
.mask = mpic_mask_irq,
911
.unmask = mpic_unmask_irq,
913
.set_type = mpic_set_irq_type,
931
.irq_mask = mpic_mask_irq,
932
.irq_unmask = mpic_unmask_irq,
933
.irq_eoi = mpic_end_irq,
934
.irq_set_type = mpic_set_irq_type,
916
937
#ifdef CONFIG_SMP
917
938
static struct irq_chip mpic_ipi_chip = {
918
.mask = mpic_mask_ipi,
919
.unmask = mpic_unmask_ipi,
939
.irq_mask = mpic_mask_ipi,
940
.irq_unmask = mpic_unmask_ipi,
941
.irq_eoi = mpic_end_ipi,
922
943
#endif /* CONFIG_SMP */
924
945
#ifdef CONFIG_MPIC_U3_HT_IRQS
925
946
static struct irq_chip mpic_irq_ht_chip = {
926
.startup = mpic_startup_ht_irq,
927
.shutdown = mpic_shutdown_ht_irq,
928
.mask = mpic_mask_irq,
929
.unmask = mpic_unmask_ht_irq,
930
.eoi = mpic_end_ht_irq,
931
.set_type = mpic_set_irq_type,
947
.irq_startup = mpic_startup_ht_irq,
948
.irq_shutdown = mpic_shutdown_ht_irq,
949
.irq_mask = mpic_mask_irq,
950
.irq_unmask = mpic_unmask_ht_irq,
951
.irq_eoi = mpic_end_ht_irq,
952
.irq_set_type = mpic_set_irq_type,
933
954
#endif /* CONFIG_MPIC_U3_HT_IRQS */
957
978
WARN_ON(!(mpic->flags & MPIC_PRIMARY));
959
980
DBG("mpic: mapping as IPI\n");
960
set_irq_chip_data(virq, mpic);
961
set_irq_chip_and_handler(virq, &mpic->hc_ipi,
981
irq_set_chip_data(virq, mpic);
982
irq_set_chip_and_handler(virq, &mpic->hc_ipi,
962
983
handle_percpu_irq);
981
1002
DBG("mpic: mapping to irq chip @%p\n", chip);
983
set_irq_chip_data(virq, mpic);
984
set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
1004
irq_set_chip_data(virq, mpic);
1005
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
986
1007
/* Set default irq type */
987
set_irq_type(virq, IRQ_TYPE_NONE);
1008
irq_set_irq_type(virq, IRQ_TYPE_NONE);
1010
/* If the MPIC was reset, then all vectors have already been
1011
* initialized. Otherwise, a per source lazy initialization
1014
if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1015
mpic_set_vector(virq, hw);
1016
mpic_set_destination(virq, mpic_processor_id(mpic));
1017
mpic_irq_set_priority(virq, 8);
1060
1096
mpic->hc_irq = mpic_irq_chip;
1061
1097
mpic->hc_irq.name = name;
1062
1098
if (flags & MPIC_PRIMARY)
1063
mpic->hc_irq.set_affinity = mpic_set_affinity;
1099
mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1064
1100
#ifdef CONFIG_MPIC_U3_HT_IRQS
1065
1101
mpic->hc_ht_irq = mpic_irq_ht_chip;
1066
1102
mpic->hc_ht_irq.name = name;
1067
1103
if (flags & MPIC_PRIMARY)
1068
mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1104
mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1069
1105
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1071
1107
#ifdef CONFIG_SMP
1153
1189
mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1156
if (flags & MPIC_WANTS_RESET) {
1193
/* When using a device-node, reset requests are only honored if the MPIC
1194
* is allowed to reset.
1196
if (mpic_reset_prohibited(node))
1197
mpic->flags |= MPIC_NO_RESET;
1199
if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1200
printk(KERN_DEBUG "mpic: Resetting\n");
1157
1201
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1158
1202
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1159
1203
| MPIC_GREG_GCONF_RESET);
1314
1358
mpic_pasemi_msi_init(mpic);
1316
if (mpic->flags & MPIC_PRIMARY)
1317
cpu = hard_smp_processor_id();
1360
cpu = mpic_processor_id(mpic);
1321
for (i = 0; i < mpic->num_sources; i++) {
1322
/* start with vector = source number, and masked */
1323
u32 vecpri = MPIC_VECPRI_MASK | i |
1324
(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1362
if (!(mpic->flags & MPIC_NO_RESET)) {
1363
for (i = 0; i < mpic->num_sources; i++) {
1364
/* start with vector = source number, and masked */
1365
u32 vecpri = MPIC_VECPRI_MASK | i |
1366
(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1326
/* check if protected */
1327
if (mpic->protected && test_bit(i, mpic->protected))
1330
mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1331
mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1368
/* check if protected */
1369
if (mpic->protected && test_bit(i, mpic->protected))
1372
mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1373
mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1334
1377
/* Init spurious vector */