221
void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo)
223
struct vxge_hw_vpath_reg __iomem *vp_reg;
224
struct vxge_hw_vp_config *config;
227
if (fifo->config->enable != VXGE_HW_FIFO_ENABLE)
230
vp_reg = fifo->vp_reg;
231
config = container_of(fifo->config, struct vxge_hw_vp_config, fifo);
233
if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
234
config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
235
val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
236
val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
237
fifo->tim_tti_cfg1_saved = val64;
238
writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
242
void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring)
244
u64 val64 = ring->tim_rti_cfg1_saved;
246
val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
247
ring->tim_rti_cfg1_saved = val64;
248
writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
251
void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo)
253
u64 val64 = fifo->tim_tti_cfg3_saved;
254
u64 timer = (fifo->rtimer * 1000) / 272;
256
val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
258
val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
259
VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
261
writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
262
/* tti_cfg3_saved is not updated again because it is
263
* initialized at one place only - init time.
267
void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring)
269
u64 val64 = ring->tim_rti_cfg3_saved;
270
u64 timer = (ring->rtimer * 1000) / 272;
272
val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
274
val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
275
VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
277
writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
278
/* rti_cfg3_saved is not updated again because it is
279
* initialized at one place only - init time.
222
284
* vxge_hw_channel_msix_mask - Mask MSIX Vector.
223
285
* @channeh: Channel for rx or tx handle
319
* vxge_hw_channel_msix_clear - Unmask the MSIX Vector.
320
* @channel: Channel for rx or tx handle
323
* The function unmasks the msix interrupt for the given msix_id
324
* if configured in MSIX oneshot mode
328
void vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channel, int msix_id)
330
__vxge_hw_pio_mem_write32_upper(
331
(u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
332
&channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
257
336
* vxge_hw_device_set_intr_type - Updates the configuration
258
337
* with new interrupt type.
259
338
* @hldev: HW device handle.
1032
1111
* vxge_hw_channel_dtr_count
1033
1112
* @channel: Channel handle. Obtained via vxge_hw_channel_open().
1035
* Retreive number of DTRs available. This function can not be called
1114
* Retrieve number of DTRs available. This function can not be called
1036
1115
* from data path. ring_initial_replenishi() is the only user.
1038
1117
int vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel)
2191
2270
if (vpath->hldev->config.intr_mode ==
2192
2271
VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
2193
2272
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2273
VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN,
2274
0, 32), &vp_reg->one_shot_vect0_en);
2275
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2194
2276
VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN,
2195
2277
0, 32), &vp_reg->one_shot_vect1_en);
2198
if (vpath->hldev->config.intr_mode ==
2199
VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
2200
2278
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2201
2279
VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN,
2202
2280
0, 32), &vp_reg->one_shot_vect2_en);
2204
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2205
VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN,
2206
0, 32), &vp_reg->one_shot_vect3_en);
2306
* vxge_hw_vpath_msix_clear - Clear MSIX Vector.
2307
* @vp: Virtual Path handle.
2310
* The function clears the msix interrupt for the given msix_id
2313
* Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2317
void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
2319
struct __vxge_hw_device *hldev = vp->vpath->hldev;
2321
if ((hldev->config.intr_mode == VXGE_HW_INTR_MODE_MSIX_ONE_SHOT))
2322
__vxge_hw_pio_mem_write32_upper(
2323
(u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2324
&hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
2326
__vxge_hw_pio_mem_write32_upper(
2327
(u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2328
&hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
2232
2332
* vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector.
2233
2333
* @vp: Virtual Path handle.
2234
2334
* @msix_id: MSI ID