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/* linux/arch/arm/mach-s5pv310/cpu.c
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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#include <linux/sched.h>
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#include <linux/sysdev.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/proc-fns.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <plat/clock.h>
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#include <plat/s5pv310.h>
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#include <plat/sdhci.h>
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#include <mach/regs-irq.h>
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extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start);
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extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
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/* Initial IO mappings */
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static struct map_desc s5pv310_iodesc[] __initdata = {
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.virtual = (unsigned long)S5P_VA_SYSRAM,
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.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(S5PV310_PA_CMU),
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(S5PV310_PA_PMU),
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.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
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.pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
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.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
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.pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
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.virtual = (unsigned long)S5P_VA_L2CC,
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.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
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.virtual = (unsigned long)S5P_VA_GPIO1,
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.pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
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.virtual = (unsigned long)S5P_VA_GPIO2,
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.pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
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.virtual = (unsigned long)S5P_VA_GPIO3,
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.pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
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.virtual = (unsigned long)S5P_VA_DMC0,
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.pfn = __phys_to_pfn(S5PV310_PA_DMC0),
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(S5PV310_PA_SROMC),
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static void s5pv310_idle(void)
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* register the standard cpu IO areas
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void __init s5pv310_map_io(void)
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iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
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/* initialize device information early */
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s5pv310_default_sdhci0();
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s5pv310_default_sdhci1();
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s5pv310_default_sdhci2();
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s5pv310_default_sdhci3();
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void __init s5pv310_init_clocks(int xtal)
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s5p_register_clocks(xtal);
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s5pv310_register_clocks();
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s5pv310_setup_clocks();
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void __init s5pv310_init_irq(void)
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gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
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for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
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* From SPI(0) to SPI(39) and SPI(51), SPI(53) are
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* connected to the interrupt combiner. These irqs
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* should be initialized to support cascade interrupt.
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if ((irq >= 40) && !(irq == 51) && !(irq == 53))
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combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
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COMBINER_IRQ(irq, 0));
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combiner_cascade_irq(irq, IRQ_SPI(irq));
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/* The parameters of s5p_init_irq() are for VIC init.
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* Theses parameters should be NULL and 0 because S5PV310
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* uses GIC instead of VIC.
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s5p_init_irq(NULL, 0);
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struct sysdev_class s5pv310_sysclass = {
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.name = "s5pv310-core",
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static struct sys_device s5pv310_sysdev = {
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.cls = &s5pv310_sysclass,
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static int __init s5pv310_core_init(void)
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return sysdev_class_register(&s5pv310_sysclass);
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core_initcall(s5pv310_core_init);
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#ifdef CONFIG_CACHE_L2X0
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static int __init s5pv310_l2x0_cache_init(void)
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/* TAG, Data Latency Control: 2cycle */
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__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
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__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
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/* L2X0 Prefetch Control */
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__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
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/* L2X0 Power Control */
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__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
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S5P_VA_L2CC + L2X0_POWER_CTRL);
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l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
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early_initcall(s5pv310_l2x0_cache_init);
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int __init s5pv310_init(void)
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printk(KERN_INFO "S5PV310: Initializing architecture\n");
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/* set idle function */
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pm_idle = s5pv310_idle;
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return sysdev_register(&s5pv310_sysdev);