13
13
9. start_thread must turn off UX64 ... and define tlb_refill_debug.
14
14
10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable
15
15
does not agree with pgd_bad/pmd_bad.
17
17
This might need to change later. Only the timer intr is set up to be
18
18
received on both Cpu A and B. (ip27_do_irq()/bridge_startup())
19
19
13. Cache flushing (specially the SMP version) has to be investigated.