1251
static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1243
static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1244
unsigned long trigger)
1246
struct irq_chip *chip = &ioapic_chip;
1247
irq_flow_handler_t hdl;
1254
1250
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1255
trigger == IOAPIC_LEVEL)
1251
trigger == IOAPIC_LEVEL) {
1256
1252
irq_set_status_flags(irq, IRQ_LEVEL);
1258
1255
irq_clear_status_flags(irq, IRQ_LEVEL);
1260
if (irq_remapped(get_irq_chip_data(irq))) {
1259
if (irq_remapped(cfg)) {
1261
1260
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1263
set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1267
set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1268
handle_edge_irq, "edge");
1261
chip = &ir_ioapic_chip;
1262
fasteoi = trigger != 0;
1272
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1273
trigger == IOAPIC_LEVEL)
1274
set_irq_chip_and_handler_name(irq, &ioapic_chip,
1278
set_irq_chip_and_handler_name(irq, &ioapic_chip,
1279
handle_edge_irq, "edge");
1265
hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1266
irq_set_chip_and_handler_name(irq, chip, hdl,
1267
fasteoi ? "fasteoi" : "edge");
1282
1270
static int setup_ioapic_entry(int apic_id, int irq,
1385
1373
DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1386
1374
} mp_ioapic_routing[MAX_IO_APICS];
1388
static void __init setup_IO_APIC_irqs(void)
1390
int apic_id, pin, idx, irq, notcon = 0;
1391
int node = cpu_to_node(0);
1392
struct irq_cfg *cfg;
1394
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1396
for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1376
static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1381
apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1382
mp_ioapics[apic_id].apicid, pin);
1386
static void __init __io_apic_setup_irqs(unsigned int apic_id)
1388
int idx, node = cpu_to_node(0);
1389
struct io_apic_irq_attr attr;
1390
unsigned int pin, irq;
1397
1392
for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1398
1393
idx = find_irq_entry(apic_id, pin, mp_INT);
1402
apic_printk(APIC_VERBOSE,
1403
KERN_DEBUG " %d-%d",
1404
mp_ioapics[apic_id].apicid, pin);
1406
apic_printk(APIC_VERBOSE, " %d-%d",
1407
mp_ioapics[apic_id].apicid, pin);
1394
if (io_apic_pin_not_connected(idx, apic_id, pin))
1411
apic_printk(APIC_VERBOSE,
1412
" (apicid-pin) not connected\n");
1416
1397
irq = pin_2_irq(idx, apic_id, pin);
1423
1404
* installed and if it returns 1:
1425
1406
if (apic->multi_timer_check &&
1426
apic->multi_timer_check(apic_id, irq))
1429
cfg = alloc_irq_and_cfg_at(irq, node);
1433
add_pin_to_irq_node(cfg, node, apic_id, pin);
1435
* don't mark it in pin_programmed, so later acpi could
1436
* set it correctly when irq < 16
1438
setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
1407
apic->multi_timer_check(apic_id, irq))
1410
set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1413
io_apic_setup_irq_pin(irq, node, &attr);
1443
apic_printk(APIC_VERBOSE,
1444
" (apicid-pin) not connected\n");
1417
static void __init setup_IO_APIC_irqs(void)
1419
unsigned int apic_id;
1421
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1423
for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1424
__io_apic_setup_irqs(apic_id);
1472
1452
if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1475
cfg = alloc_irq_and_cfg_at(irq, node);
1479
add_pin_to_irq_node(cfg, node, apic_id, pin);
1481
if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1482
pr_debug("Pin %d-%d already programmed\n",
1483
mp_ioapics[apic_id].apicid, pin);
1486
set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1488
setup_ioapic_irq(apic_id, pin, irq, cfg,
1489
irq_trigger(idx), irq_polarity(idx));
1455
set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1458
io_apic_setup_irq_pin_once(irq, node, &attr);
2949
2919
late_initcall(io_apic_bug_finalize);
2951
struct sysfs_ioapic_data {
2952
struct sys_device dev;
2953
struct IO_APIC_route_entry entry[0];
2955
static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2921
static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS];
2957
static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2923
static void suspend_ioapic(int ioapic_id)
2959
struct IO_APIC_route_entry *entry;
2960
struct sysfs_ioapic_data *data;
2925
struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id];
2963
data = container_of(dev, struct sysfs_ioapic_data, dev);
2964
entry = data->entry;
2965
for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2966
*entry = ioapic_read_entry(dev->id, i);
2931
for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++)
2932
saved_data[i] = ioapic_read_entry(ioapic_id, i);
2935
static int ioapic_suspend(void)
2939
for (ioapic_id = 0; ioapic_id < nr_ioapics; ioapic_id++)
2940
suspend_ioapic(ioapic_id);
2971
static int ioapic_resume(struct sys_device *dev)
2945
static void resume_ioapic(int ioapic_id)
2973
struct IO_APIC_route_entry *entry;
2974
struct sysfs_ioapic_data *data;
2947
struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id];
2975
2948
unsigned long flags;
2976
2949
union IO_APIC_reg_00 reg_00;
2979
data = container_of(dev, struct sysfs_ioapic_data, dev);
2980
entry = data->entry;
2982
2955
raw_spin_lock_irqsave(&ioapic_lock, flags);
2983
reg_00.raw = io_apic_read(dev->id, 0);
2984
if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
2985
reg_00.bits.ID = mp_ioapics[dev->id].apicid;
2986
io_apic_write(dev->id, 0, reg_00.raw);
2956
reg_00.raw = io_apic_read(ioapic_id, 0);
2957
if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) {
2958
reg_00.bits.ID = mp_ioapics[ioapic_id].apicid;
2959
io_apic_write(ioapic_id, 0, reg_00.raw);
2988
2961
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2989
for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2990
ioapic_write_entry(dev->id, i, entry[i]);
2995
static struct sysdev_class ioapic_sysdev_class = {
2962
for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++)
2963
ioapic_write_entry(ioapic_id, i, saved_data[i]);
2966
static void ioapic_resume(void)
2970
for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
2971
resume_ioapic(ioapic_id);
2974
static struct syscore_ops ioapic_syscore_ops = {
2997
2975
.suspend = ioapic_suspend,
2998
2976
.resume = ioapic_resume,
3001
static int __init ioapic_init_sysfs(void)
2979
static int __init ioapic_init_ops(void)
3003
struct sys_device * dev;
3006
error = sysdev_class_register(&ioapic_sysdev_class);
3010
for (i = 0; i < nr_ioapics; i++ ) {
3011
size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2983
for (i = 0; i < nr_ioapics; i++) {
2986
size = nr_ioapic_registers[i]
3012
2987
* sizeof(struct IO_APIC_route_entry);
3013
mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3014
if (!mp_ioapic_data[i]) {
3015
printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3018
dev = &mp_ioapic_data[i]->dev;
3020
dev->cls = &ioapic_sysdev_class;
3021
error = sysdev_register(dev);
3023
kfree(mp_ioapic_data[i]);
3024
mp_ioapic_data[i] = NULL;
3025
printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2988
ioapic_saved_data[i] = kzalloc(size, GFP_KERNEL);
2989
if (!ioapic_saved_data[i])
2990
pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
2993
register_syscore_ops(&ioapic_syscore_ops);
3033
device_initcall(ioapic_init_sysfs);
2998
device_initcall(ioapic_init_ops);
3036
3001
* Dynamic irq allocate and deallocation
3301
set_irq_msi(irq, msidesc);
3267
irq_set_msi_desc(irq, msidesc);
3302
3268
write_msi_msg(irq, &msg);
3304
if (irq_remapped(get_irq_chip_data(irq))) {
3270
if (irq_remapped(irq_get_chip_data(irq))) {
3305
3271
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3306
set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3308
set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3272
chip = &msi_ir_chip;
3275
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3310
3277
dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3504
hpet_msi_write(get_irq_data(irq), &msg);
3472
hpet_msi_write(irq_get_handler_data(irq), &msg);
3505
3473
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3506
if (irq_remapped(get_irq_chip_data(irq)))
3507
set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3508
handle_edge_irq, "edge");
3510
set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3511
handle_edge_irq, "edge");
3474
if (irq_remapped(irq_get_chip_data(irq)))
3475
chip = &ir_hpet_msi_type;
3477
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3606
3571
#endif /* CONFIG_HT_IRQ */
3608
int __init io_apic_get_redir_entries (int ioapic)
3574
io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3576
struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3581
ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3583
setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
3584
attr->trigger, attr->polarity);
3588
int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3589
struct io_apic_irq_attr *attr)
3591
unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
3594
/* Avoid redundant programming */
3595
if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) {
3596
pr_debug("Pin %d-%d already programmed\n",
3597
mp_ioapics[id].apicid, pin);
3600
ret = io_apic_setup_irq_pin(irq, node, attr);
3602
set_bit(pin, mp_ioapic_routing[id].pin_programmed);
3606
static int __init io_apic_get_redir_entries(int ioapic)
3610
3608
union IO_APIC_reg_01 reg_01;
3611
3609
unsigned long flags;
3662
static int __io_apic_set_pci_routing(struct device *dev, int irq,
3663
struct io_apic_irq_attr *irq_attr)
3660
int io_apic_set_pci_routing(struct device *dev, int irq,
3661
struct io_apic_irq_attr *irq_attr)
3665
struct irq_cfg *cfg;
3668
int trigger, polarity;
3670
ioapic = irq_attr->ioapic;
3671
3665
if (!IO_APIC_IRQ(irq)) {
3672
3666
apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3674
3668
return -EINVAL;
3678
node = dev_to_node(dev);
3680
node = cpu_to_node(0);
3682
cfg = alloc_irq_and_cfg_at(irq, node);
3686
pin = irq_attr->ioapic_pin;
3687
trigger = irq_attr->trigger;
3688
polarity = irq_attr->polarity;
3691
* IRQs < 16 are already in the irq_2_pin[] map
3693
if (irq >= legacy_pic->nr_legacy_irqs) {
3694
if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) {
3695
printk(KERN_INFO "can not add pin %d for irq %d\n",
3701
setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
3706
int io_apic_set_pci_routing(struct device *dev, int irq,
3707
struct io_apic_irq_attr *irq_attr)
3711
* Avoid pin reprogramming. PRTs typically include entries
3712
* with redundant pin->gsi mappings (but unique PCI devices);
3713
* we only program the IOAPIC on the first.
3715
ioapic = irq_attr->ioapic;
3716
pin = irq_attr->ioapic_pin;
3717
if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3718
pr_debug("Pin %d-%d already programmed\n",
3719
mp_ioapics[ioapic].apicid, pin);
3722
set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3724
return __io_apic_set_pci_routing(dev, irq, irq_attr);
3727
u8 __init io_apic_unique_id(u8 id)
3729
#ifdef CONFIG_X86_32
3730
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3731
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3732
return io_apic_get_unique_id(nr_ioapics, id);
3737
DECLARE_BITMAP(used, 256);
3739
bitmap_zero(used, 256);
3740
for (i = 0; i < nr_ioapics; i++) {
3741
struct mpc_ioapic *ia = &mp_ioapics[i];
3742
__set_bit(ia->apicid, used);
3744
if (!test_bit(id, used))
3746
return find_first_zero_bit(used, 256);
3750
#ifdef CONFIG_X86_32
3751
int __init io_apic_get_unique_id(int ioapic, int apic_id)
3671
node = dev ? dev_to_node(dev) : cpu_to_node(0);
3673
return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3676
#ifdef CONFIG_X86_32
3677
static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3753
3679
union IO_APIC_reg_00 reg_00;
3754
3680
static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3822
3748
return apic_id;
3751
static u8 __init io_apic_unique_id(u8 id)
3753
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3754
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3755
return io_apic_get_unique_id(nr_ioapics, id);
3760
static u8 __init io_apic_unique_id(u8 id)
3763
DECLARE_BITMAP(used, 256);
3765
bitmap_zero(used, 256);
3766
for (i = 0; i < nr_ioapics; i++) {
3767
struct mpc_ioapic *ia = &mp_ioapics[i];
3768
__set_bit(ia->apicid, used);
3770
if (!test_bit(id, used))
3772
return find_first_zero_bit(used, 256);
3826
int __init io_apic_get_version(int ioapic)
3776
static int __init io_apic_get_version(int ioapic)
3828
3778
union IO_APIC_reg_01 reg_01;
3829
3779
unsigned long flags;
3884
3834
if ((ioapic > 0) && (irq > 16))
3887
desc = irq_to_desc(irq);
3837
idata = irq_get_irq_data(irq);
3890
3840
* Honour affinities which have been set in early boot
3893
(IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
3894
mask = desc->irq_data.affinity;
3842
if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3843
mask = idata->affinity;
3896
3845
mask = apic->target_cpus();
3898
3847
if (intr_remapping_enabled)
3899
ir_ioapic_set_affinity(&desc->irq_data, mask, false);
3848
ir_ioapic_set_affinity(idata, mask, false);
3901
ioapic_set_affinity(&desc->irq_data, mask, false);
3850
ioapic_set_affinity(idata, mask, false);
4086
4035
/* Enable IOAPIC early just for system timer */
4087
4036
void __init pre_init_apic_IRQ0(void)
4089
struct irq_cfg *cfg;
4038
struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4091
4040
printk(KERN_INFO "Early APIC setup for system timer0\n");
4092
4041
#ifndef CONFIG_SMP
4093
4042
physid_set_mask_of_physid(boot_cpu_physical_apicid,
4094
4043
&phys_cpu_present_map);
4096
/* Make sure the irq descriptor is set up */
4097
cfg = alloc_irq_and_cfg_at(0, 0);
4099
4045
setup_local_APIC();
4101
add_pin_to_irq_node(cfg, 0, 0, 0);
4102
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4104
setup_ioapic_irq(0, 0, 0, cfg, 0, 0);
4047
io_apic_setup_irq_pin(0, 0, &attr);
4048
irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,