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  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno
  • Date: 2011-06-07 12:14:05 UTC
  • mfrom: (43.1.9 sid)
  • Revision ID: james.westby@ubuntu.com-20110607121405-i3h1rd7nrnd2b73h
Tags: 2.6.39-2
http://bugs.debian.org/627492
http://bugs.debian.org/596626
http://bugs.debian.org/628932
http://bugs.debian.org/628191
http://bugs.debian.org/627837
http://bugs.debian.org/622997
http://bugs.debian.org/622745
http://bugs.debian.org/619827
http://bugs.debian.org/629401
[ Ben Hutchings ]
* [x86] Enable BACKLIGHT_APPLE, replacing BACKLIGHT_MBP_NVIDIA
  (Closes: #627492)
* cgroups: Disable memory resource controller by default. Allow it
  to be enabled using kernel parameter 'cgroup_enable=memory'.
* rt2800usb: Enable support for more USB devices including
  Linksys WUSB600N (Closes: #596626) (this change was accidentally
  omitted from 2.6.39-1)
* [x86] Remove Celeron from list of processors supporting PAE. Most
  'Celeron M' models do not.
* Update debconf template translations:
  - Swedish (Martin Bagge) (Closes: #628932)
  - French (David Prévot) (Closes: #628191)
* aufs: Update for 2.6.39 (Closes: #627837)
* Add stable 2.6.39.1, including:
  - ext4: dont set PageUptodate in ext4_end_bio()
  - pata_cmd64x: fix boot crash on parisc (Closes: #622997, #622745)
  - ext3: Fix fs corruption when make_indexed_dir() fails
  - netfilter: nf_ct_sip: validate Content-Length in TCP SIP messages
  - sctp: fix race between sctp_bind_addr_free() and
    sctp_bind_addr_conflict()
  - sctp: fix memory leak of the ASCONF queue when free asoc
  - md/bitmap: fix saving of events_cleared and other state
  - cdc_acm: Fix oops when Droids MuIn LCD is connected
  - cx88: Fix conversion from BKL to fine-grained locks (Closes: #619827)
  - keys: Set cred->user_ns in key_replace_session_keyring (CVE-2011-2184)
  - tmpfs: fix race between truncate and writepage
  - nfs41: Correct offset for LAYOUTCOMMIT
  - xen/mmu: fix a race window causing leave_mm BUG()
  - ext4: fix possible use-after-free in ext4_remove_li_request()
  For the complete list of changes, see:
   http://www.kernel.org/pub/linux/kernel/v2.6/ChangeLog-2.6.39.1
* Bump ABI to 2
* netfilter: Enable IP_SET, IP_SET_BITMAP_IP, IP_SET_BITMAP_IPMAC,
  IP_SET_BITMAP_PORT, IP_SET_HASH_IP, IP_SET_HASH_IPPORT,
  IP_SET_HASH_IPPORTIP, IP_SET_HASH_IPPORTNET, IP_SET_HASH_NET,
  IP_SET_HASH_NETPORT, IP_SET_LIST_SET, NETFILTER_XT_SET as modules
  (Closes: #629401)

[ Aurelien Jarno ]
* [mipsel/loongson-2f] Disable_SCSI_LPFC to workaround GCC ICE.

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arch/arm/mach-lh7a40x/include/mach/entry-macro.S
1
 
/*
2
 
 * arch/arm/mach-lh7a40x/include/mach/entry-macro.S
3
 
 *
4
 
 * Low-level IRQ helper macros for LH7A40x platforms
5
 
 *
6
 
 * This file is licensed under  the terms of the GNU General Public
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 * License version 2. This program is licensed "as is" without any
8
 
 * warranty of any kind, whether express or implied.
9
 
 */
10
 
#include <mach/hardware.h>
11
 
#include <mach/irqs.h>
12
 
 
13
 
/* In order to allow there to be support for both of the processor
14
 
   classes at the same time, we make a hack here that isn't very
15
 
   pretty.  At startup, the link pointed to with the
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   branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17
 
   detected as a lh7a404.
18
 
 
19
 
   *** FIXME: we should clean this up so that there is only one
20
 
              implementation for each CPU's design.
21
 
 
22
 
*/
23
 
 
24
 
#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
25
 
 
26
 
                .macro  disable_fiq
27
 
                .endm
28
 
 
29
 
                .macro  get_irqnr_preamble, base, tmp
30
 
                .endm
31
 
 
32
 
                .macro  arch_ret_to_user, tmp1, tmp2
33
 
                .endm
34
 
 
35
 
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
36
 
 
37
 
branch_irq_lh7a400: b 1000f
38
 
 
39
 
@ Implementation of the LH7A404 get_irqnr_and_base.
40
 
 
41
 
                mov     \irqnr, #0                      @ VIC1 irq base
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                mov     \base, #io_p2v(0x80000000)      @ APB registers
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                add     \base, \base, #0x8000
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                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
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                tst     \tmp, #VA_VECTORED              @ Direct vectored
46
 
                bne     1002f
47
 
                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
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                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
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                bne     1001f
50
 
                add     \base, \base, #(0xa000 - 0x8000)
51
 
                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
52
 
                tst     \tmp, #VA_VECTORED              @ Direct vectored
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                bne     1002f
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                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
55
 
                mov     \irqnr, #32                     @ VIC2 irq base
56
 
 
57
 
1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
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                bcs     1008f                           @ Bit set; irq found
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                add     \irqnr, \irqnr, #1
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                bne     1001b                           @ Until no bits
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                b       1009f                           @ Nothing?  Hmm.
62
 
1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
63
 
1008:           movs    \irqstat, #1                    @ Force !Z
64
 
                str     \tmp, [\base, #0x0030]          @ Clear vector
65
 
                b       1009f
66
 
 
67
 
@ Implementation of the LH7A400 get_irqnr_and_base.
68
 
 
69
 
1000:           mov     \irqnr, #0
70
 
                mov     \base, #io_p2v(0x80000000)      @ APB registers
71
 
                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
72
 
 
73
 
1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
74
 
                bcs     1008f                           @ Bit set; irq found
75
 
                add     \irqnr, \irqnr, #1
76
 
                bne     1001b                           @ Until no bits
77
 
                b       1009f                           @ Nothing?  Hmm.
78
 
1008:           movs    \irqstat, #1                    @ Force !Z
79
 
 
80
 
1009:
81
 
               .endm
82
 
 
83
 
 
84
 
 
85
 
#elif defined (CONFIG_ARCH_LH7A400)
86
 
                .macro  disable_fiq
87
 
                .endm
88
 
 
89
 
                .macro  get_irqnr_preamble, base, tmp
90
 
                .endm
91
 
 
92
 
                .macro  arch_ret_to_user, tmp1, tmp2
93
 
                .endm
94
 
 
95
 
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
96
 
                mov     \irqnr, #0
97
 
                mov     \base, #io_p2v(0x80000000)      @ APB registers
98
 
                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
99
 
 
100
 
1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
101
 
                bcs     1008f                           @ Bit set; irq found
102
 
                add     \irqnr, \irqnr, #1
103
 
                bne     1001b                           @ Until no bits
104
 
                b       1009f                           @ Nothing?  Hmm.
105
 
1008:           movs    \irqstat, #1                    @ Force !Z
106
 
1009:
107
 
               .endm
108
 
 
109
 
#elif defined(CONFIG_ARCH_LH7A404)
110
 
 
111
 
                .macro  disable_fiq
112
 
                .endm
113
 
 
114
 
                .macro  get_irqnr_preamble, base, tmp
115
 
                .endm
116
 
 
117
 
                .macro  arch_ret_to_user, tmp1, tmp2
118
 
                .endm
119
 
 
120
 
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
121
 
                mov     \irqnr, #0                      @ VIC1 irq base
122
 
                mov     \base, #io_p2v(0x80000000)      @ APB registers
123
 
                add     \base, \base, #0x8000
124
 
                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
125
 
                tst     \tmp, #VA_VECTORED              @ Direct vectored
126
 
                bne     1002f
127
 
                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
128
 
                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
129
 
                bne     1001f
130
 
                add     \base, \base, #(0xa000 - 0x8000)
131
 
                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
132
 
                tst     \tmp, #VA_VECTORED              @ Direct vectored
133
 
                bne     1002f
134
 
                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
135
 
                mov     \irqnr, #32                     @ VIC2 irq base
136
 
 
137
 
1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
138
 
                bcs     1008f                           @ Bit set; irq found
139
 
                add     \irqnr, \irqnr, #1
140
 
                bne     1001b                           @ Until no bits
141
 
                b       1009f                           @ Nothing?  Hmm.
142
 
1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
143
 
1008:           movs    \irqstat, #1                    @ Force !Z
144
 
                str     \tmp, [\base, #0x0030]          @ Clear vector
145
 
1009:
146
 
               .endm
147
 
#endif
148
 
 
149