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1
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2010 Intel Corporation.
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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#define DRV_VERSION "3.2.9-k2"
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const char ixgbe_driver_version[] = DRV_VERSION;
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static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
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static const char ixgbe_copyright[] =
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"Copyright (c) 1999-2011 Intel Corporation.";
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static const struct ixgbe_info *ixgbe_info_tbl[] = {
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[board_82598] = &ixgbe_82598_info,
643
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* @adapter: driver private struct
644
645
* @index: reg idx of queue to query (0-127)
646
* Helper function to determine the traffic index for a paticular
647
* Helper function to determine the traffic index for a particular
647
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* register index.
649
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* Returns : a tc index for use in range 0-7, or 0-3
651
u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
652
static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
654
int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
655
int dcb_i = netdev_get_num_tc(adapter->netdev);
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/* if DCB is not enabled the queues have no TC */
657
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if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2888
2894
switch (mask) {
2895
#ifdef CONFIG_IXGBE_DCB
2896
case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2897
mrqc = IXGBE_MRQC_RTRSS8TCEN;
2899
case (IXGBE_FLAG_DCB_ENABLED):
2900
mrqc = IXGBE_MRQC_RT8TCEN;
2902
#endif /* CONFIG_IXGBE_DCB */
2889
2903
case (IXGBE_FLAG_RSS_ENABLED):
2890
2904
mrqc = IXGBE_MRQC_RSSEN;
2892
2906
case (IXGBE_FLAG_SRIOV_ENABLED):
2893
2907
mrqc = IXGBE_MRQC_VMDQEN;
2895
#ifdef CONFIG_IXGBE_DCB
2896
case (IXGBE_FLAG_DCB_ENABLED):
2897
mrqc = IXGBE_MRQC_RT8TCEN;
2899
#endif /* CONFIG_IXGBE_DCB */
3077
3086
ixgbe_configure_srrctl(adapter, ring);
3078
3087
ixgbe_configure_rscctl(adapter, ring);
3089
/* If operating in IOV mode set RLPML for X540 */
3090
if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3091
hw->mac.type == ixgbe_mac_X540) {
3092
rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3093
rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3094
ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3080
3097
if (hw->mac.type == ixgbe_mac_82598EB) {
3082
3099
* enable cache line friendly hardware writes:
3641
3658
if (hw->mac.type == ixgbe_mac_82598EB)
3642
3659
netif_set_gso_max_size(adapter->netdev, 32768);
3645
if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3646
max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3649
ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3651
ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
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3662
/* Enable VLAN tag insert/strip */
3655
3663
adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3657
3665
hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3659
3667
/* reconfigure the hardware */
3660
ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3668
if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3670
if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3671
max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3673
ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3675
ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3677
ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3679
struct net_device *dev = adapter->netdev;
3681
if (adapter->ixgbe_ieee_ets)
3682
dev->dcbnl_ops->ieee_setets(dev,
3683
adapter->ixgbe_ieee_ets);
3684
if (adapter->ixgbe_ieee_pfc)
3685
dev->dcbnl_ops->ieee_setpfc(dev,
3686
adapter->ixgbe_ieee_pfc);
3689
/* Enable RSS Hash per TC */
3690
if (hw->mac.type != ixgbe_mac_82598EB) {
3694
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3696
u8 cnt = adapter->netdev->tc_to_txq[i].count;
3701
reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3703
IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
4243
4288
ixgbe_reinit_locked(adapter);
4246
#ifdef CONFIG_IXGBE_DCB
4247
static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4250
struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4252
if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4256
adapter->num_rx_queues = f->indices;
4257
adapter->num_tx_queues = f->indices;
4265
4292
* ixgbe_set_rss_queues: Allocate queues for RSS
4266
4293
* @adapter: board private structure to initialize
4332
4359
static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4335
4361
struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4337
f->indices = min((int)num_online_cpus(), f->indices);
4338
if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4363
if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4366
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4367
#ifdef CONFIG_IXGBE_DCB
4369
struct net_device *dev = adapter->netdev;
4371
tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4372
f->indices = dev->tc_to_txq[tc].count;
4373
f->mask = dev->tc_to_txq[tc].offset;
4376
f->indices = min((int)num_online_cpus(), f->indices);
4339
4378
adapter->num_rx_queues = 1;
4340
4379
adapter->num_tx_queues = 1;
4341
#ifdef CONFIG_IXGBE_DCB
4342
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4343
e_info(probe, "FCoE enabled with DCB\n");
4344
ixgbe_set_dcb_queues(adapter);
4347
4381
if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4348
4382
e_info(probe, "FCoE enabled with RSS\n");
4349
4383
if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4356
4390
f->mask = adapter->num_rx_queues;
4357
4391
adapter->num_rx_queues += f->indices;
4358
4392
adapter->num_tx_queues += f->indices;
4397
#endif /* IXGBE_FCOE */
4399
#ifdef CONFIG_IXGBE_DCB
4400
static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4403
struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4406
if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4410
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4411
q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4416
adapter->num_rx_queues = f->indices;
4417
adapter->num_tx_queues = f->indices;
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/* FCoE enabled queues require special configuration done through
4422
* configure_fcoe() and others. Here we map FCoE indices onto the
4423
* DCB queue pairs allowing FCoE to own configuration later.
4425
ixgbe_set_fcoe_queues(adapter);
4366
#endif /* IXGBE_FCOE */
4368
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* ixgbe_set_sriov_queues: Allocate queues for IOV use
4369
4434
* @adapter: board private structure to initialize
4502
4567
#ifdef CONFIG_IXGBE_DCB
4569
/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4570
void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4571
unsigned int *tx, unsigned int *rx)
4573
struct net_device *dev = adapter->netdev;
4574
struct ixgbe_hw *hw = &adapter->hw;
4575
u8 num_tcs = netdev_get_num_tc(dev);
4580
switch (hw->mac.type) {
4581
case ixgbe_mac_82598EB:
4585
case ixgbe_mac_82599EB:
4586
case ixgbe_mac_X540:
4591
} else if (tc < 5) {
4592
*tx = ((tc + 2) << 4);
4594
} else if (tc < num_tcs) {
4595
*tx = ((tc + 8) << 3);
4598
} else if (num_tcs == 4) {
4623
#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4625
/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4628
* @netdev: net device to configure
4629
* @tc: number of traffic classes to enable
4631
int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4634
unsigned int q, offset = 0;
4637
netdev_reset_tc(dev);
4639
struct ixgbe_adapter *adapter = netdev_priv(dev);
4641
/* Hardware supports up to 8 traffic classes */
4642
if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4645
/* Partition Tx queues evenly amongst traffic classes */
4646
for (i = 0; i < tc; i++) {
4647
q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4648
netdev_set_prio_tc_map(dev, i, i);
4649
netdev_set_tc_queue(dev, i, q, offset);
4653
/* This enables multiple traffic class support in the hardware
4654
* which defaults to strict priority transmission by default.
4655
* If traffic classes are already enabled perhaps through DCB
4656
* code path then existing configuration will be used.
4658
if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4659
dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4660
struct ieee_ets ets = {
4661
.prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4663
u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4665
dev->dcbnl_ops->setdcbx(dev, mode);
4666
dev->dcbnl_ops->ieee_setets(dev, &ets);
4504
4673
* ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4505
4674
* @adapter: board private structure to initialize
4510
4679
static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4514
int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4681
struct net_device *dev = adapter->netdev;
4683
u8 num_tcs = netdev_get_num_tc(dev);
4516
4685
if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4519
/* the number of queues is assumed to be symmetric */
4520
switch (adapter->hw.mac.type) {
4521
case ixgbe_mac_82598EB:
4522
for (i = 0; i < dcb_i; i++) {
4523
adapter->rx_ring[i]->reg_idx = i << 3;
4524
adapter->tx_ring[i]->reg_idx = i << 2;
4528
case ixgbe_mac_82599EB:
4529
case ixgbe_mac_X540:
4532
* Tx TC0 starts at: descriptor queue 0
4533
* Tx TC1 starts at: descriptor queue 32
4534
* Tx TC2 starts at: descriptor queue 64
4535
* Tx TC3 starts at: descriptor queue 80
4536
* Tx TC4 starts at: descriptor queue 96
4537
* Tx TC5 starts at: descriptor queue 104
4538
* Tx TC6 starts at: descriptor queue 112
4539
* Tx TC7 starts at: descriptor queue 120
4541
* Rx TC0-TC7 are offset by 16 queues each
4543
for (i = 0; i < 3; i++) {
4544
adapter->tx_ring[i]->reg_idx = i << 5;
4545
adapter->rx_ring[i]->reg_idx = i << 4;
4547
for ( ; i < 5; i++) {
4548
adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4549
adapter->rx_ring[i]->reg_idx = i << 4;
4551
for ( ; i < dcb_i; i++) {
4552
adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4553
adapter->rx_ring[i]->reg_idx = i << 4;
4556
} else if (dcb_i == 4) {
4558
* Tx TC0 starts at: descriptor queue 0
4559
* Tx TC1 starts at: descriptor queue 64
4560
* Tx TC2 starts at: descriptor queue 96
4561
* Tx TC3 starts at: descriptor queue 112
4563
* Rx TC0-TC3 are offset by 32 queues each
4565
adapter->tx_ring[0]->reg_idx = 0;
4566
adapter->tx_ring[1]->reg_idx = 64;
4567
adapter->tx_ring[2]->reg_idx = 96;
4568
adapter->tx_ring[3]->reg_idx = 112;
4569
for (i = 0 ; i < dcb_i; i++)
4570
adapter->rx_ring[i]->reg_idx = i << 5;
4688
for (i = 0, k = 0; i < num_tcs; i++) {
4689
unsigned int tx_s, rx_s;
4690
u16 count = dev->tc_to_txq[i].count;
4692
ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4693
for (j = 0; j < count; j++, k++) {
4694
adapter->tx_ring[k]->reg_idx = tx_s + j;
4695
adapter->rx_ring[k]->reg_idx = rx_s + j;
4696
adapter->tx_ring[k]->dcb_tc = i;
4697
adapter->rx_ring[k]->dcb_tc = i;
4620
4744
if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4623
#ifdef CONFIG_IXGBE_DCB
4624
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4625
struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4627
ixgbe_cache_ring_dcb(adapter);
4628
/* find out queues in TC for FCoE */
4629
fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4630
fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4632
* In 82599, the number of Tx queues for each traffic
4633
* class for both 8-TC and 4-TC modes are:
4634
* TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4635
* 8 TCs: 32 32 16 16 8 8 8 8
4636
* 4 TCs: 64 64 32 32
4637
* We have max 8 queues for FCoE, where 8 the is
4638
* FCoE redirection table size. If TC for FCoE is
4639
* less than or equal to TC3, we have enough queues
4640
* to add max of 8 queues for FCoE, so we start FCoE
4641
* Tx queue from the next one, i.e., reg_idx + 1.
4642
* If TC for FCoE is above TC3, implying 8 TC mode,
4643
* and we need 8 for FCoE, we have to take all queues
4644
* in that traffic class for FCoE.
4646
if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4649
#endif /* CONFIG_IXGBE_DCB */
4650
4747
if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4651
4748
if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4652
4749
(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
5174
5271
adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5175
5272
adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5176
5273
adapter->dcb_cfg.pfc_mode_enable = false;
5177
adapter->dcb_cfg.round_robin_enable = false;
5178
5274
adapter->dcb_set_bitmap = 0x00;
5275
adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5179
5276
ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5180
adapter->ring_feature[RING_F_DCB].indices);
5442
5539
int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5444
5541
/* MTU < 68 is an error and causes problems on some kernels */
5445
if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5542
if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5543
hw->mac.type != ixgbe_mac_X540) {
5544
if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5547
if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5448
5551
e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5449
5552
/* must set new MTU before calling down or up */
6101
6208
(link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6103
6210
(link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6104
"1 Gbps" : "unknown speed")),
6212
(link_speed == IXGBE_LINK_SPEED_100_FULL ?
6105
6215
((flow_rx && flow_tx) ? "RX/TX" :
6106
6216
(flow_rx ? "RX" :
6107
6217
(flow_tx ? "TX" : "None"))));
6109
6219
netif_carrier_on(netdev);
6220
ixgbe_check_vf_rate_limit(adapter);
6111
6222
/* Force detection of hung controller */
6112
6223
for (i = 0; i < adapter->num_tx_queues; i++) {
6637
6748
protocol = vlan_get_protocol(skb);
6639
if ((protocol == htons(ETH_P_FCOE)) ||
6640
(protocol == htons(ETH_P_FIP))) {
6641
if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6642
txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6643
txq += adapter->ring_feature[RING_F_FCOE].mask;
6645
#ifdef CONFIG_IXGBE_DCB
6646
} else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6647
txq = adapter->fcoe.up;
6750
if (((protocol == htons(ETH_P_FCOE)) ||
6751
(protocol == htons(ETH_P_FIP))) &&
6752
(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6753
txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6754
txq += adapter->ring_feature[RING_F_FCOE].mask;
6687
6783
tx_flags |= vlan_tx_tag_get(skb);
6688
6784
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6689
6785
tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6690
tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6786
tx_flags |= tx_ring->dcb_tc << 13;
6692
6788
tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6693
6789
tx_flags |= IXGBE_TX_FLAGS_VLAN;
6694
6790
} else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6695
6791
skb->priority != TC_PRIO_CONTROL) {
6696
tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6792
tx_flags |= tx_ring->dcb_tc << 13;
6697
6793
tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6698
6794
tx_flags |= IXGBE_TX_FLAGS_VLAN;
6702
6798
/* for FCoE with DCB, we force the priority to what
6703
6799
* was specified by the switch */
6704
6800
if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6705
(protocol == htons(ETH_P_FCOE) ||
6706
protocol == htons(ETH_P_FIP))) {
6707
#ifdef CONFIG_IXGBE_DCB
6708
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6709
tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6710
<< IXGBE_TX_FLAGS_VLAN_SHIFT);
6711
tx_flags |= ((adapter->fcoe.up << 13)
6712
<< IXGBE_TX_FLAGS_VLAN_SHIFT);
6715
/* flag for FCoE offloads */
6716
if (protocol == htons(ETH_P_FCOE))
6717
tx_flags |= IXGBE_TX_FLAGS_FCOE;
6801
(protocol == htons(ETH_P_FCOE)))
6802
tx_flags |= IXGBE_TX_FLAGS_FCOE;
6721
6805
/* four things can cause us to need a context descriptor */
6988
7072
.ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6989
7073
.ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6990
7074
.ndo_get_stats64 = ixgbe_get_stats64,
7075
#ifdef CONFIG_IXGBE_DCB
7076
.ndo_setup_tc = ixgbe_setup_tc,
6991
7078
#ifdef CONFIG_NET_POLL_CONTROLLER
6992
7079
.ndo_poll_controller = ixgbe_netpoll,
6994
7081
#ifdef IXGBE_FCOE
6995
7082
.ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7083
.ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6996
7084
.ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6997
7085
.ndo_fcoe_enable = ixgbe_fcoe_enable,
6998
7086
.ndo_fcoe_disable = ixgbe_fcoe_disable,
7129
7217
indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7219
#if defined(CONFIG_DCB)
7131
7220
indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7221
#elif defined(IXGBE_FCOE)
7133
7222
indices += min_t(unsigned int, num_possible_cpus(),
7134
7223
IXGBE_MAX_FCOE_INDICES);