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/* This Bridge driver's device context: */
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struct bridge_dev_context {
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struct dev_object *hdev_obj; /* Handle to Bridge device object. */
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u32 dw_dsp_base_addr; /* Arm's API to DSP virt base addr */
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struct dev_object *dev_obj; /* Handle to Bridge device object. */
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u32 dsp_base_addr; /* Arm's API to DSP virt base addr */
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* DSP External memory prog address as seen virtually by the OS on
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u32 dw_dsp_ext_base_addr; /* See the comment above */
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u32 dw_api_reg_base; /* API mem map'd registers */
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void __iomem *dw_dsp_mmu_base; /* DSP MMU Mapped registers */
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u32 dw_api_clk_base; /* CLK Registers */
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u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 dw_public_rhea; /* Pub Rhea */
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u32 dw_int_addr; /* MB INTR reg */
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u32 dw_tc_endianism; /* TC Endianism register */
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u32 dw_test_base; /* DSP MMU Mapped registers */
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u32 dw_self_loop; /* Pointer to the selfloop */
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u32 dw_dsp_start_add; /* API Boot vector */
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u32 dw_internal_size; /* Internal memory size */
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u32 dsp_ext_base_addr; /* See the comment above */
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u32 api_reg_base; /* API mem map'd registers */
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void __iomem *dsp_mmu_base; /* DSP MMU Mapped registers */
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u32 api_clk_base; /* CLK Registers */
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u32 dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 public_rhea; /* Pub Rhea */
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u32 int_addr; /* MB INTR reg */
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u32 tc_endianism; /* TC Endianism register */
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u32 test_base; /* DSP MMU Mapped registers */
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u32 self_loop; /* Pointer to the selfloop */
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u32 dsp_start_add; /* API Boot vector */
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u32 internal_size; /* Internal memory size */
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struct omap_mbox *mbox; /* Mail box handle */
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/* DMMU TLB entries */
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struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];
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u32 dw_brd_state; /* Last known board state. */
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u32 brd_state; /* Last known board state. */
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/* TC Settings */
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bool tc_word_swap_on; /* Traffic Controller Word Swap */
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* ======== sm_interrupt_dsp ========
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* Set interrupt value & send an interrupt to the DSP processor(s).
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* This is typicaly used when mailbox interrupt mechanisms allow data
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* This is typically used when mailbox interrupt mechanisms allow data
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* to be associated with interrupt such as for OMAP's CMD/DATA regs.
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* dev_context: Handle to Bridge driver defined device info.