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  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno
  • Date: 2011-06-07 12:14:05 UTC
  • mfrom: (43.1.9 sid)
  • Revision ID: james.westby@ubuntu.com-20110607121405-i3h1rd7nrnd2b73h
Tags: 2.6.39-2
http://bugs.debian.org/627492
http://bugs.debian.org/596626
http://bugs.debian.org/628932
http://bugs.debian.org/628191
http://bugs.debian.org/627837
http://bugs.debian.org/622997
http://bugs.debian.org/622745
http://bugs.debian.org/619827
http://bugs.debian.org/629401
[ Ben Hutchings ]
* [x86] Enable BACKLIGHT_APPLE, replacing BACKLIGHT_MBP_NVIDIA
  (Closes: #627492)
* cgroups: Disable memory resource controller by default. Allow it
  to be enabled using kernel parameter 'cgroup_enable=memory'.
* rt2800usb: Enable support for more USB devices including
  Linksys WUSB600N (Closes: #596626) (this change was accidentally
  omitted from 2.6.39-1)
* [x86] Remove Celeron from list of processors supporting PAE. Most
  'Celeron M' models do not.
* Update debconf template translations:
  - Swedish (Martin Bagge) (Closes: #628932)
  - French (David Prévot) (Closes: #628191)
* aufs: Update for 2.6.39 (Closes: #627837)
* Add stable 2.6.39.1, including:
  - ext4: dont set PageUptodate in ext4_end_bio()
  - pata_cmd64x: fix boot crash on parisc (Closes: #622997, #622745)
  - ext3: Fix fs corruption when make_indexed_dir() fails
  - netfilter: nf_ct_sip: validate Content-Length in TCP SIP messages
  - sctp: fix race between sctp_bind_addr_free() and
    sctp_bind_addr_conflict()
  - sctp: fix memory leak of the ASCONF queue when free asoc
  - md/bitmap: fix saving of events_cleared and other state
  - cdc_acm: Fix oops when Droids MuIn LCD is connected
  - cx88: Fix conversion from BKL to fine-grained locks (Closes: #619827)
  - keys: Set cred->user_ns in key_replace_session_keyring (CVE-2011-2184)
  - tmpfs: fix race between truncate and writepage
  - nfs41: Correct offset for LAYOUTCOMMIT
  - xen/mmu: fix a race window causing leave_mm BUG()
  - ext4: fix possible use-after-free in ext4_remove_li_request()
  For the complete list of changes, see:
   http://www.kernel.org/pub/linux/kernel/v2.6/ChangeLog-2.6.39.1
* Bump ABI to 2
* netfilter: Enable IP_SET, IP_SET_BITMAP_IP, IP_SET_BITMAP_IPMAC,
  IP_SET_BITMAP_PORT, IP_SET_HASH_IP, IP_SET_HASH_IPPORT,
  IP_SET_HASH_IPPORTIP, IP_SET_HASH_IPPORTNET, IP_SET_HASH_NET,
  IP_SET_HASH_NETPORT, IP_SET_LIST_SET, NETFILTER_XT_SET as modules
  (Closes: #629401)

[ Aurelien Jarno ]
* [mipsel/loongson-2f] Disable_SCSI_LPFC to workaround GCC ICE.

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Lines of Context:
drivers/mtd/nand/pxa3xx_nand.c
27
27
#include <plat/pxa3xx_nand.h>
28
28
 
29
29
#define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
 
30
#define NAND_STOP_DELAY         (2 * HZ/50)
 
31
#define PAGE_CHUNK_SIZE         (2048)
30
32
 
31
33
/* registers and bit definitions */
32
34
#define NDCR            (0x00) /* Control register */
52
54
#define NDCR_ND_MODE            (0x3 << 21)
53
55
#define NDCR_NAND_MODE          (0x0)
54
56
#define NDCR_CLR_PG_CNT         (0x1 << 20)
55
 
#define NDCR_CLR_ECC            (0x1 << 19)
 
57
#define NDCR_STOP_ON_UNCOR      (0x1 << 19)
56
58
#define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
57
59
#define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
58
60
 
59
61
#define NDCR_RA_START           (0x1 << 15)
60
62
#define NDCR_PG_PER_BLK         (0x1 << 14)
61
63
#define NDCR_ND_ARB_EN          (0x1 << 12)
 
64
#define NDCR_INT_MASK           (0xFFF)
62
65
 
63
66
#define NDSR_MASK               (0xfff)
64
 
#define NDSR_RDY                (0x1 << 11)
 
67
#define NDSR_RDY                (0x1 << 12)
 
68
#define NDSR_FLASH_RDY          (0x1 << 11)
65
69
#define NDSR_CS0_PAGED          (0x1 << 10)
66
70
#define NDSR_CS1_PAGED          (0x1 << 9)
67
71
#define NDSR_CS0_CMDD           (0x1 << 8)
74
78
#define NDSR_RDDREQ             (0x1 << 1)
75
79
#define NDSR_WRCMDREQ           (0x1)
76
80
 
 
81
#define NDCB0_ST_ROW_EN         (0x1 << 26)
77
82
#define NDCB0_AUTO_RS           (0x1 << 25)
78
83
#define NDCB0_CSEL              (0x1 << 24)
79
84
#define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
104
109
};
105
110
 
106
111
enum {
107
 
        STATE_READY     = 0,
 
112
        STATE_IDLE = 0,
108
113
        STATE_CMD_HANDLE,
109
114
        STATE_DMA_READING,
110
115
        STATE_DMA_WRITING,
111
116
        STATE_DMA_DONE,
112
117
        STATE_PIO_READING,
113
118
        STATE_PIO_WRITING,
 
119
        STATE_CMD_DONE,
 
120
        STATE_READY,
114
121
};
115
122
 
116
123
struct pxa3xx_nand_info {
117
124
        struct nand_chip        nand_chip;
118
125
 
 
126
        struct nand_hw_control  controller;
119
127
        struct platform_device   *pdev;
120
128
        struct pxa3xx_nand_cmdset *cmdset;
121
129
 
126
134
        unsigned int            buf_start;
127
135
        unsigned int            buf_count;
128
136
 
 
137
        struct mtd_info         *mtd;
129
138
        /* DMA information */
130
139
        int                     drcmr_dat;
131
140
        int                     drcmr_cmd;
149
158
 
150
159
        int                     use_ecc;        /* use HW ECC ? */
151
160
        int                     use_dma;        /* use DMA ? */
 
161
        int                     is_ready;
152
162
 
153
163
        unsigned int            page_size;      /* page size of attached chip */
154
164
        unsigned int            data_size;      /* data size in FIFO */
174
184
 
175
185
static int use_dma = 1;
176
186
module_param(use_dma, bool, 0444);
177
 
MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
 
187
MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
178
188
 
179
189
/*
180
190
 * Default NAND flash controller configuration setup by the
201
211
};
202
212
 
203
213
static struct pxa3xx_nand_flash builtin_flash_types[] = {
204
 
        {      0,   0, 2048,  8,  8,    0, &default_cmdset, &timing[0] },
205
 
        { 0x46ec,  32,  512, 16, 16, 4096, &default_cmdset, &timing[1] },
206
 
        { 0xdaec,  64, 2048,  8,  8, 2048, &default_cmdset, &timing[1] },
207
 
        { 0xd7ec, 128, 4096,  8,  8, 8192, &default_cmdset, &timing[1] },
208
 
        { 0xa12c,  64, 2048,  8,  8, 1024, &default_cmdset, &timing[2] },
209
 
        { 0xb12c,  64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
210
 
        { 0xdc2c,  64, 2048,  8,  8, 4096, &default_cmdset, &timing[2] },
211
 
        { 0xcc2c,  64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
212
 
        { 0xba20,  64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
 
214
{ "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 
215
{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 
216
{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 
217
{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 
218
{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 
219
{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 
220
{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 
221
{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 
222
{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
213
223
};
214
224
 
215
225
/* Define a default flash type setting serve as flash detecting only */
216
226
#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
217
227
 
 
228
const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
 
229
 
218
230
#define NDTR0_tCH(c)    (min((c), 7) << 19)
219
231
#define NDTR0_tCS(c)    (min((c), 7) << 16)
220
232
#define NDTR0_tWH(c)    (min((c), 7) << 11)
252
264
        nand_writel(info, NDTR1CS0, ndtr1);
253
265
}
254
266
 
255
 
#define WAIT_EVENT_TIMEOUT      10
256
 
 
257
 
static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
258
 
{
259
 
        int timeout = WAIT_EVENT_TIMEOUT;
260
 
        uint32_t ndsr;
261
 
 
262
 
        while (timeout--) {
263
 
                ndsr = nand_readl(info, NDSR) & NDSR_MASK;
264
 
                if (ndsr & event) {
265
 
                        nand_writel(info, NDSR, ndsr);
266
 
                        return 0;
267
 
                }
268
 
                udelay(10);
269
 
        }
270
 
 
271
 
        return -ETIMEDOUT;
272
 
}
273
 
 
274
267
static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
275
268
{
276
269
        int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
291
284
        }
292
285
}
293
286
 
294
 
static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
295
 
                uint16_t cmd, int column, int page_addr)
296
 
{
297
 
        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
298
 
        pxa3xx_set_datasize(info);
299
 
 
300
 
        /* generate values for NDCBx registers */
301
 
        info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
302
 
        info->ndcb1 = 0;
303
 
        info->ndcb2 = 0;
304
 
        info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
305
 
 
306
 
        if (info->col_addr_cycles == 2) {
307
 
                /* large block, 2 cycles for column address
308
 
                 * row address starts from 3rd cycle
309
 
                 */
310
 
                info->ndcb1 |= page_addr << 16;
311
 
                if (info->row_addr_cycles == 3)
312
 
                        info->ndcb2 = (page_addr >> 16) & 0xff;
313
 
        } else
314
 
                /* small block, 1 cycles for column address
315
 
                 * row address starts from 2nd cycle
316
 
                 */
317
 
                info->ndcb1 = page_addr << 8;
318
 
 
319
 
        if (cmd == cmdset->program)
320
 
                info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
321
 
 
322
 
        return 0;
323
 
}
324
 
 
325
 
static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
326
 
                        uint16_t cmd, int page_addr)
327
 
{
328
 
        info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
329
 
        info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
330
 
        info->ndcb1 = page_addr;
331
 
        info->ndcb2 = 0;
332
 
        return 0;
333
 
}
334
 
 
335
 
static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
336
 
{
337
 
        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
338
 
 
339
 
        info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
340
 
        info->ndcb1 = 0;
341
 
        info->ndcb2 = 0;
342
 
 
343
 
        info->oob_size = 0;
344
 
        if (cmd == cmdset->read_id) {
345
 
                info->ndcb0 |= NDCB0_CMD_TYPE(3);
346
 
                info->data_size = 8;
347
 
        } else if (cmd == cmdset->read_status) {
348
 
                info->ndcb0 |= NDCB0_CMD_TYPE(4);
349
 
                info->data_size = 8;
350
 
        } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
351
 
                   cmd == cmdset->unlock) {
352
 
                info->ndcb0 |= NDCB0_CMD_TYPE(5);
353
 
        } else
354
 
                return -EINVAL;
355
 
 
356
 
        return 0;
357
 
}
358
 
 
359
 
static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
360
 
{
361
 
        uint32_t ndcr;
362
 
 
363
 
        ndcr = nand_readl(info, NDCR);
364
 
        nand_writel(info, NDCR, ndcr & ~int_mask);
365
 
}
366
 
 
367
 
static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
368
 
{
369
 
        uint32_t ndcr;
370
 
 
371
 
        ndcr = nand_readl(info, NDCR);
372
 
        nand_writel(info, NDCR, ndcr | int_mask);
373
 
}
374
 
 
375
 
/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
376
 
 * otherwise, it does not work
 
287
/**
 
288
 * NOTE: it is a must to set ND_RUN firstly, then write
 
289
 * command buffer, otherwise, it does not work.
 
290
 * We enable all the interrupt at the same time, and
 
291
 * let pxa3xx_nand_irq to handle all logic.
377
292
 */
378
 
static int write_cmd(struct pxa3xx_nand_info *info)
 
293
static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
379
294
{
380
295
        uint32_t ndcr;
381
296
 
382
 
        /* clear status bits and run */
383
 
        nand_writel(info, NDSR, NDSR_MASK);
384
 
 
385
297
        ndcr = info->reg_ndcr;
386
 
 
387
298
        ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
388
299
        ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
389
300
        ndcr |= NDCR_ND_RUN;
390
301
 
 
302
        /* clear status bits and run */
 
303
        nand_writel(info, NDCR, 0);
 
304
        nand_writel(info, NDSR, NDSR_MASK);
391
305
        nand_writel(info, NDCR, ndcr);
392
 
 
393
 
        if (wait_for_event(info, NDSR_WRCMDREQ)) {
394
 
                printk(KERN_ERR "timed out writing command\n");
395
 
                return -ETIMEDOUT;
396
 
        }
397
 
 
398
 
        nand_writel(info, NDCB0, info->ndcb0);
399
 
        nand_writel(info, NDCB0, info->ndcb1);
400
 
        nand_writel(info, NDCB0, info->ndcb2);
401
 
        return 0;
402
 
}
403
 
 
404
 
static int handle_data_pio(struct pxa3xx_nand_info *info)
405
 
{
406
 
        int ret, timeout = CHIP_DELAY_TIMEOUT;
407
 
 
 
306
}
 
307
 
 
308
static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 
309
{
 
310
        uint32_t ndcr;
 
311
        int timeout = NAND_STOP_DELAY;
 
312
 
 
313
        /* wait RUN bit in NDCR become 0 */
 
314
        ndcr = nand_readl(info, NDCR);
 
315
        while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 
316
                ndcr = nand_readl(info, NDCR);
 
317
                udelay(1);
 
318
        }
 
319
 
 
320
        if (timeout <= 0) {
 
321
                ndcr &= ~NDCR_ND_RUN;
 
322
                nand_writel(info, NDCR, ndcr);
 
323
        }
 
324
        /* clear status bits */
 
325
        nand_writel(info, NDSR, NDSR_MASK);
 
326
}
 
327
 
 
328
static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 
329
{
 
330
        uint32_t ndcr;
 
331
 
 
332
        ndcr = nand_readl(info, NDCR);
 
333
        nand_writel(info, NDCR, ndcr & ~int_mask);
 
334
}
 
335
 
 
336
static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 
337
{
 
338
        uint32_t ndcr;
 
339
 
 
340
        ndcr = nand_readl(info, NDCR);
 
341
        nand_writel(info, NDCR, ndcr | int_mask);
 
342
}
 
343
 
 
344
static void handle_data_pio(struct pxa3xx_nand_info *info)
 
345
{
408
346
        switch (info->state) {
409
347
        case STATE_PIO_WRITING:
410
348
                __raw_writesl(info->mmio_base + NDDB, info->data_buff,
412
350
                if (info->oob_size > 0)
413
351
                        __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
414
352
                                        DIV_ROUND_UP(info->oob_size, 4));
415
 
 
416
 
                enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
417
 
 
418
 
                ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
419
 
                if (!ret) {
420
 
                        printk(KERN_ERR "program command time out\n");
421
 
                        return -1;
422
 
                }
423
353
                break;
424
354
        case STATE_PIO_READING:
425
355
                __raw_readsl(info->mmio_base + NDDB, info->data_buff,
431
361
        default:
432
362
                printk(KERN_ERR "%s: invalid state %d\n", __func__,
433
363
                                info->state);
434
 
                return -EINVAL;
 
364
                BUG();
435
365
        }
436
 
 
437
 
        info->state = STATE_READY;
438
 
        return 0;
439
366
}
440
367
 
441
 
static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
 
368
static void start_data_dma(struct pxa3xx_nand_info *info)
442
369
{
443
370
        struct pxa_dma_desc *desc = info->data_desc;
444
371
        int dma_len = ALIGN(info->data_size + info->oob_size, 32);
446
373
        desc->ddadr = DDADR_STOP;
447
374
        desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
448
375
 
449
 
        if (dir_out) {
 
376
        switch (info->state) {
 
377
        case STATE_DMA_WRITING:
450
378
                desc->dsadr = info->data_buff_phys;
451
379
                desc->dtadr = info->mmio_phys + NDDB;
452
380
                desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
453
 
        } else {
 
381
                break;
 
382
        case STATE_DMA_READING:
454
383
                desc->dtadr = info->data_buff_phys;
455
384
                desc->dsadr = info->mmio_phys + NDDB;
456
385
                desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 
386
                break;
 
387
        default:
 
388
                printk(KERN_ERR "%s: invalid state %d\n", __func__,
 
389
                                info->state);
 
390
                BUG();
457
391
        }
458
392
 
459
393
        DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
471
405
 
472
406
        if (dcsr & DCSR_BUSERR) {
473
407
                info->retcode = ERR_DMABUSERR;
474
 
                complete(&info->cmd_complete);
475
408
        }
476
409
 
477
 
        if (info->state == STATE_DMA_WRITING) {
478
 
                info->state = STATE_DMA_DONE;
479
 
                enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
480
 
        } else {
481
 
                info->state = STATE_READY;
482
 
                complete(&info->cmd_complete);
483
 
        }
 
410
        info->state = STATE_DMA_DONE;
 
411
        enable_int(info, NDCR_INT_MASK);
 
412
        nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
484
413
}
485
414
 
486
415
static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
487
416
{
488
417
        struct pxa3xx_nand_info *info = devid;
489
 
        unsigned int status;
 
418
        unsigned int status, is_completed = 0;
490
419
 
491
420
        status = nand_readl(info, NDSR);
492
421
 
493
 
        if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
494
 
                if (status & NDSR_DBERR)
495
 
                        info->retcode = ERR_DBERR;
496
 
                else if (status & NDSR_SBERR)
497
 
                        info->retcode = ERR_SBERR;
498
 
 
499
 
                disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
500
 
 
501
 
                if (info->use_dma) {
502
 
                        info->state = STATE_DMA_READING;
503
 
                        start_data_dma(info, 0);
504
 
                } else {
505
 
                        info->state = STATE_PIO_READING;
506
 
                        complete(&info->cmd_complete);
507
 
                }
508
 
        } else if (status & NDSR_WRDREQ) {
509
 
                disable_int(info, NDSR_WRDREQ);
510
 
                if (info->use_dma) {
511
 
                        info->state = STATE_DMA_WRITING;
512
 
                        start_data_dma(info, 1);
513
 
                } else {
514
 
                        info->state = STATE_PIO_WRITING;
515
 
                        complete(&info->cmd_complete);
516
 
                }
517
 
        } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
518
 
                if (status & NDSR_CS0_BBD)
519
 
                        info->retcode = ERR_BBERR;
520
 
 
521
 
                disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 
422
        if (status & NDSR_DBERR)
 
423
                info->retcode = ERR_DBERR;
 
424
        if (status & NDSR_SBERR)
 
425
                info->retcode = ERR_SBERR;
 
426
        if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 
427
                /* whether use dma to transfer data */
 
428
                if (info->use_dma) {
 
429
                        disable_int(info, NDCR_INT_MASK);
 
430
                        info->state = (status & NDSR_RDDREQ) ?
 
431
                                      STATE_DMA_READING : STATE_DMA_WRITING;
 
432
                        start_data_dma(info);
 
433
                        goto NORMAL_IRQ_EXIT;
 
434
                } else {
 
435
                        info->state = (status & NDSR_RDDREQ) ?
 
436
                                      STATE_PIO_READING : STATE_PIO_WRITING;
 
437
                        handle_data_pio(info);
 
438
                }
 
439
        }
 
440
        if (status & NDSR_CS0_CMDD) {
 
441
                info->state = STATE_CMD_DONE;
 
442
                is_completed = 1;
 
443
        }
 
444
        if (status & NDSR_FLASH_RDY) {
 
445
                info->is_ready = 1;
522
446
                info->state = STATE_READY;
523
 
                complete(&info->cmd_complete);
524
 
        }
 
447
        }
 
448
 
 
449
        if (status & NDSR_WRCMDREQ) {
 
450
                nand_writel(info, NDSR, NDSR_WRCMDREQ);
 
451
                status &= ~NDSR_WRCMDREQ;
 
452
                info->state = STATE_CMD_HANDLE;
 
453
                nand_writel(info, NDCB0, info->ndcb0);
 
454
                nand_writel(info, NDCB0, info->ndcb1);
 
455
                nand_writel(info, NDCB0, info->ndcb2);
 
456
        }
 
457
 
 
458
        /* clear NDSR to let the controller exit the IRQ */
525
459
        nand_writel(info, NDSR, status);
 
460
        if (is_completed)
 
461
                complete(&info->cmd_complete);
 
462
NORMAL_IRQ_EXIT:
526
463
        return IRQ_HANDLED;
527
464
}
528
465
 
529
 
static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
530
 
{
531
 
        uint32_t ndcr;
532
 
        int ret, timeout = CHIP_DELAY_TIMEOUT;
533
 
 
534
 
        if (write_cmd(info)) {
535
 
                info->retcode = ERR_SENDCMD;
536
 
                goto fail_stop;
537
 
        }
538
 
 
539
 
        info->state = STATE_CMD_HANDLE;
540
 
 
541
 
        enable_int(info, event);
542
 
 
543
 
        ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
544
 
        if (!ret) {
545
 
                printk(KERN_ERR "command execution timed out\n");
546
 
                info->retcode = ERR_SENDCMD;
547
 
                goto fail_stop;
548
 
        }
549
 
 
550
 
        if (info->use_dma == 0 && info->data_size > 0)
551
 
                if (handle_data_pio(info))
552
 
                        goto fail_stop;
553
 
 
554
 
        return 0;
555
 
 
556
 
fail_stop:
557
 
        ndcr = nand_readl(info, NDCR);
558
 
        nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
559
 
        udelay(10);
560
 
        return -ETIMEDOUT;
561
 
}
562
 
 
563
466
static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
564
467
{
565
468
        struct pxa3xx_nand_info *info = mtd->priv;
574
477
        return 1;
575
478
}
576
479
 
577
 
static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
578
 
                                int column, int page_addr)
 
480
static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 
481
                uint16_t column, int page_addr)
579
482
{
580
 
        struct pxa3xx_nand_info *info = mtd->priv;
581
 
        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
582
 
        int ret;
583
 
 
584
 
        info->use_dma = (use_dma) ? 1 : 0;
585
 
        info->use_ecc = 0;
586
 
        info->data_size = 0;
587
 
        info->state = STATE_READY;
588
 
 
589
 
        init_completion(&info->cmd_complete);
 
483
        uint16_t cmd;
 
484
        int addr_cycle, exec_cmd, ndcb0;
 
485
        struct mtd_info *mtd = info->mtd;
 
486
 
 
487
        ndcb0 = 0;
 
488
        addr_cycle = 0;
 
489
        exec_cmd = 1;
 
490
 
 
491
        /* reset data and oob column point to handle data */
 
492
        info->buf_start         = 0;
 
493
        info->buf_count         = 0;
 
494
        info->oob_size          = 0;
 
495
        info->use_ecc           = 0;
 
496
        info->is_ready          = 0;
 
497
        info->retcode           = ERR_NONE;
590
498
 
591
499
        switch (command) {
592
 
        case NAND_CMD_READOOB:
593
 
                /* disable HW ECC to get all the OOB data */
594
 
                info->buf_count = mtd->writesize + mtd->oobsize;
595
 
                info->buf_start = mtd->writesize + column;
596
 
                memset(info->data_buff, 0xFF, info->buf_count);
597
 
 
598
 
                if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
599
 
                        break;
600
 
 
601
 
                pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
602
 
 
603
 
                /* We only are OOB, so if the data has error, does not matter */
604
 
                if (info->retcode == ERR_DBERR)
605
 
                        info->retcode = ERR_NONE;
606
 
                break;
607
 
 
608
500
        case NAND_CMD_READ0:
 
501
        case NAND_CMD_PAGEPROG:
609
502
                info->use_ecc = 1;
610
 
                info->retcode = ERR_NONE;
611
 
                info->buf_start = column;
 
503
        case NAND_CMD_READOOB:
 
504
                pxa3xx_set_datasize(info);
 
505
                break;
 
506
        case NAND_CMD_SEQIN:
 
507
                exec_cmd = 0;
 
508
                break;
 
509
        default:
 
510
                info->ndcb1 = 0;
 
511
                info->ndcb2 = 0;
 
512
                break;
 
513
        }
 
514
 
 
515
        info->ndcb0 = ndcb0;
 
516
        addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 
517
                                    + info->col_addr_cycles);
 
518
 
 
519
        switch (command) {
 
520
        case NAND_CMD_READOOB:
 
521
        case NAND_CMD_READ0:
 
522
                cmd = info->cmdset->read1;
 
523
                if (command == NAND_CMD_READOOB)
 
524
                        info->buf_start = mtd->writesize + column;
 
525
                else
 
526
                        info->buf_start = column;
 
527
 
 
528
                if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
 
529
                        info->ndcb0 |= NDCB0_CMD_TYPE(0)
 
530
                                        | addr_cycle
 
531
                                        | (cmd & NDCB0_CMD1_MASK);
 
532
                else
 
533
                        info->ndcb0 |= NDCB0_CMD_TYPE(0)
 
534
                                        | NDCB0_DBC
 
535
                                        | addr_cycle
 
536
                                        | cmd;
 
537
 
 
538
        case NAND_CMD_SEQIN:
 
539
                /* small page addr setting */
 
540
                if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
 
541
                        info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 
542
                                        | (column & 0xFF);
 
543
 
 
544
                        info->ndcb2 = 0;
 
545
                } else {
 
546
                        info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 
547
                                        | (column & 0xFFFF);
 
548
 
 
549
                        if (page_addr & 0xFF0000)
 
550
                                info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 
551
                        else
 
552
                                info->ndcb2 = 0;
 
553
                }
 
554
 
612
555
                info->buf_count = mtd->writesize + mtd->oobsize;
613
556
                memset(info->data_buff, 0xFF, info->buf_count);
614
557
 
615
 
                if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
616
 
                        break;
617
 
 
618
 
                pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
619
 
 
620
 
                if (info->retcode == ERR_DBERR) {
621
 
                        /* for blank page (all 0xff), HW will calculate its ECC as
622
 
                         * 0, which is different from the ECC information within
623
 
                         * OOB, ignore such double bit errors
624
 
                         */
625
 
                        if (is_buf_blank(info->data_buff, mtd->writesize))
626
 
                                info->retcode = ERR_NONE;
627
 
                }
628
 
                break;
629
 
        case NAND_CMD_SEQIN:
630
 
                info->buf_start = column;
631
 
                info->buf_count = mtd->writesize + mtd->oobsize;
632
 
                memset(info->data_buff, 0xff, info->buf_count);
633
 
 
634
 
                /* save column/page_addr for next CMD_PAGEPROG */
635
 
                info->seqin_column = column;
636
 
                info->seqin_page_addr = page_addr;
637
 
                break;
 
558
                break;
 
559
 
638
560
        case NAND_CMD_PAGEPROG:
639
 
                info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
640
 
 
641
 
                if (prepare_read_prog_cmd(info, cmdset->program,
642
 
                                info->seqin_column, info->seqin_page_addr))
643
 
                        break;
644
 
 
645
 
                pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
646
 
                break;
647
 
        case NAND_CMD_ERASE1:
648
 
                if (prepare_erase_cmd(info, cmdset->erase, page_addr))
649
 
                        break;
650
 
 
651
 
                pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
652
 
                break;
653
 
        case NAND_CMD_ERASE2:
654
 
                break;
 
561
                if (is_buf_blank(info->data_buff,
 
562
                                        (mtd->writesize + mtd->oobsize))) {
 
563
                        exec_cmd = 0;
 
564
                        break;
 
565
                }
 
566
 
 
567
                cmd = info->cmdset->program;
 
568
                info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 
569
                                | NDCB0_AUTO_RS
 
570
                                | NDCB0_ST_ROW_EN
 
571
                                | NDCB0_DBC
 
572
                                | cmd
 
573
                                | addr_cycle;
 
574
                break;
 
575
 
655
576
        case NAND_CMD_READID:
 
577
                cmd = info->cmdset->read_id;
 
578
                info->buf_count = info->read_id_bytes;
 
579
                info->ndcb0 |= NDCB0_CMD_TYPE(3)
 
580
                                | NDCB0_ADDR_CYC(1)
 
581
                                | cmd;
 
582
 
 
583
                info->data_size = 8;
 
584
                break;
656
585
        case NAND_CMD_STATUS:
657
 
                info->use_dma = 0;      /* force PIO read */
658
 
                info->buf_start = 0;
659
 
                info->buf_count = (command == NAND_CMD_READID) ?
660
 
                                info->read_id_bytes : 1;
661
 
 
662
 
                if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
663
 
                                cmdset->read_id : cmdset->read_status))
664
 
                        break;
665
 
 
666
 
                pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
 
586
                cmd = info->cmdset->read_status;
 
587
                info->buf_count = 1;
 
588
                info->ndcb0 |= NDCB0_CMD_TYPE(4)
 
589
                                | NDCB0_ADDR_CYC(1)
 
590
                                | cmd;
 
591
 
 
592
                info->data_size = 8;
 
593
                break;
 
594
 
 
595
        case NAND_CMD_ERASE1:
 
596
                cmd = info->cmdset->erase;
 
597
                info->ndcb0 |= NDCB0_CMD_TYPE(2)
 
598
                                | NDCB0_AUTO_RS
 
599
                                | NDCB0_ADDR_CYC(3)
 
600
                                | NDCB0_DBC
 
601
                                | cmd;
 
602
                info->ndcb1 = page_addr;
 
603
                info->ndcb2 = 0;
 
604
 
667
605
                break;
668
606
        case NAND_CMD_RESET:
669
 
                if (prepare_other_cmd(info, cmdset->reset))
670
 
                        break;
671
 
 
672
 
                ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
673
 
                if (ret == 0) {
674
 
                        int timeout = 2;
675
 
                        uint32_t ndcr;
676
 
 
677
 
                        while (timeout--) {
678
 
                                if (nand_readl(info, NDSR) & NDSR_RDY)
679
 
                                        break;
680
 
                                msleep(10);
681
 
                        }
682
 
 
683
 
                        ndcr = nand_readl(info, NDCR);
684
 
                        nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
685
 
                }
686
 
                break;
 
607
                cmd = info->cmdset->reset;
 
608
                info->ndcb0 |= NDCB0_CMD_TYPE(5)
 
609
                                | cmd;
 
610
 
 
611
                break;
 
612
 
 
613
        case NAND_CMD_ERASE2:
 
614
                exec_cmd = 0;
 
615
                break;
 
616
 
687
617
        default:
688
 
                printk(KERN_ERR "non-supported command.\n");
 
618
                exec_cmd = 0;
 
619
                printk(KERN_ERR "pxa3xx-nand: non-supported"
 
620
                        " command %x\n", command);
689
621
                break;
690
622
        }
691
623
 
692
 
        if (info->retcode == ERR_DBERR) {
693
 
                printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
694
 
                info->retcode = ERR_NONE;
695
 
        }
 
624
        return exec_cmd;
 
625
}
 
626
 
 
627
static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 
628
                                int column, int page_addr)
 
629
{
 
630
        struct pxa3xx_nand_info *info = mtd->priv;
 
631
        int ret, exec_cmd;
 
632
 
 
633
        /*
 
634
         * if this is a x16 device ,then convert the input
 
635
         * "byte" address into a "word" address appropriate
 
636
         * for indexing a word-oriented device
 
637
         */
 
638
        if (info->reg_ndcr & NDCR_DWIDTH_M)
 
639
                column /= 2;
 
640
 
 
641
        exec_cmd = prepare_command_pool(info, command, column, page_addr);
 
642
        if (exec_cmd) {
 
643
                init_completion(&info->cmd_complete);
 
644
                pxa3xx_nand_start(info);
 
645
 
 
646
                ret = wait_for_completion_timeout(&info->cmd_complete,
 
647
                                CHIP_DELAY_TIMEOUT);
 
648
                if (!ret) {
 
649
                        printk(KERN_ERR "Wait time out!!!\n");
 
650
                        /* Stop State Machine for next command cycle */
 
651
                        pxa3xx_nand_stop(info);
 
652
                }
 
653
                info->state = STATE_IDLE;
 
654
        }
 
655
}
 
656
 
 
657
static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 
658
                struct nand_chip *chip, const uint8_t *buf)
 
659
{
 
660
        chip->write_buf(mtd, buf, mtd->writesize);
 
661
        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 
662
}
 
663
 
 
664
static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 
665
                struct nand_chip *chip, uint8_t *buf, int page)
 
666
{
 
667
        struct pxa3xx_nand_info *info = mtd->priv;
 
668
 
 
669
        chip->read_buf(mtd, buf, mtd->writesize);
 
670
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 
671
 
 
672
        if (info->retcode == ERR_SBERR) {
 
673
                switch (info->use_ecc) {
 
674
                case 1:
 
675
                        mtd->ecc_stats.corrected++;
 
676
                        break;
 
677
                case 0:
 
678
                default:
 
679
                        break;
 
680
                }
 
681
        } else if (info->retcode == ERR_DBERR) {
 
682
                /*
 
683
                 * for blank page (all 0xff), HW will calculate its ECC as
 
684
                 * 0, which is different from the ECC information within
 
685
                 * OOB, ignore such double bit errors
 
686
                 */
 
687
                if (is_buf_blank(buf, mtd->writesize))
 
688
                        mtd->ecc_stats.failed++;
 
689
        }
 
690
 
 
691
        return 0;
696
692
}
697
693
 
698
694
static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
769
765
        return 0;
770
766
}
771
767
 
772
 
static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
773
 
{
774
 
        return;
775
 
}
776
 
 
777
 
static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
778
 
                const uint8_t *dat, uint8_t *ecc_code)
779
 
{
780
 
        return 0;
781
 
}
782
 
 
783
 
static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
784
 
                uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
785
 
{
786
 
        struct pxa3xx_nand_info *info = mtd->priv;
787
 
        /*
788
 
         * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
789
 
         * consider it as a ecc error which will tell the caller the
790
 
         * read fail We have distinguish all the errors, but the
791
 
         * nand_read_ecc only check this function return value
792
 
         *
793
 
         * Corrected (single-bit) errors must also be noted.
794
 
         */
795
 
        if (info->retcode == ERR_SBERR)
796
 
                return 1;
797
 
        else if (info->retcode != ERR_NONE)
798
 
                return -1;
799
 
 
800
 
        return 0;
801
 
}
802
 
 
803
 
static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
804
 
{
805
 
        const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
806
 
        uint32_t ndcr;
807
 
        uint8_t  id_buff[8];
808
 
 
809
 
        if (prepare_other_cmd(info, cmdset->read_id)) {
810
 
                printk(KERN_ERR "failed to prepare command\n");
811
 
                return -EINVAL;
812
 
        }
813
 
 
814
 
        /* Send command */
815
 
        if (write_cmd(info))
816
 
                goto fail_timeout;
817
 
 
818
 
        /* Wait for CMDDM(command done successfully) */
819
 
        if (wait_for_event(info, NDSR_RDDREQ))
820
 
                goto fail_timeout;
821
 
 
822
 
        __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
823
 
        *id = id_buff[0] | (id_buff[1] << 8);
824
 
        return 0;
825
 
 
826
 
fail_timeout:
827
 
        ndcr = nand_readl(info, NDCR);
828
 
        nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
829
 
        udelay(10);
830
 
        return -ETIMEDOUT;
831
 
}
832
 
 
833
768
static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
834
769
                                    const struct pxa3xx_nand_flash *f)
835
770
{
836
771
        struct platform_device *pdev = info->pdev;
837
772
        struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
838
 
        uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
 
773
        uint32_t ndcr = 0x0; /* enable all interrupts */
839
774
 
840
775
        if (f->page_size != 2048 && f->page_size != 512)
841
776
                return -EINVAL;
844
779
                return -EINVAL;
845
780
 
846
781
        /* calculate flash information */
847
 
        info->cmdset = f->cmdset;
 
782
        info->cmdset = &default_cmdset;
848
783
        info->page_size = f->page_size;
849
 
        info->oob_buff = info->data_buff + f->page_size;
850
784
        info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
851
785
 
852
786
        /* calculate addressing information */
876
810
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
877
811
{
878
812
        uint32_t ndcr = nand_readl(info, NDCR);
879
 
        struct nand_flash_dev *type = NULL;
880
 
        uint32_t id = -1, page_per_block, num_blocks;
881
 
        int i;
882
 
 
883
 
        page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
884
813
        info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
885
 
        /* set info fields needed to __readid */
 
814
        /* set info fields needed to read id */
886
815
        info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
887
816
        info->reg_ndcr = ndcr;
888
817
        info->cmdset = &default_cmdset;
889
818
 
890
 
        if (__readid(info, &id))
891
 
                return -ENODEV;
892
 
 
893
 
        /* Lookup the flash id */
894
 
        id = (id >> 8) & 0xff;          /* device id is byte 2 */
895
 
        for (i = 0; nand_flash_ids[i].name != NULL; i++) {
896
 
                if (id == nand_flash_ids[i].id) {
897
 
                        type =  &nand_flash_ids[i];
898
 
                        break;
899
 
                }
900
 
        }
901
 
 
902
 
        if (!type)
903
 
                return -ENODEV;
904
 
 
905
 
        /* fill the missing flash information */
906
 
        i = __ffs(page_per_block * info->page_size);
907
 
        num_blocks = type->chipsize << (20 - i);
908
 
 
909
 
        /* calculate addressing information */
910
 
        info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
911
 
 
912
 
        if (num_blocks * page_per_block > 65536)
913
 
                info->row_addr_cycles = 3;
914
 
        else
915
 
                info->row_addr_cycles = 2;
916
 
 
917
819
        info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
918
820
        info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
919
821
 
920
822
        return 0;
921
823
}
922
824
 
923
 
static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
924
 
                                    const struct pxa3xx_nand_platform_data *pdata)
925
 
{
926
 
        const struct pxa3xx_nand_flash *f;
927
 
        uint32_t id = -1;
928
 
        int i;
929
 
 
930
 
        if (pdata->keep_config)
931
 
                if (pxa3xx_nand_detect_config(info) == 0)
932
 
                        return 0;
933
 
 
934
 
        /* we use default timing to detect id */
935
 
        f = DEFAULT_FLASH_TYPE;
936
 
        pxa3xx_nand_config_flash(info, f);
937
 
        if (__readid(info, &id))
938
 
                goto fail_detect;
939
 
 
940
 
        for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
941
 
                /* we first choose the flash definition from platfrom */
942
 
                if (i < pdata->num_flash)
943
 
                        f = pdata->flash + i;
944
 
                else
945
 
                        f = &builtin_flash_types[i - pdata->num_flash + 1];
946
 
                if (f->chip_id == id) {
947
 
                        dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
948
 
                        pxa3xx_nand_config_flash(info, f);
949
 
                        return 0;
950
 
                }
951
 
        }
952
 
 
953
 
        dev_warn(&info->pdev->dev,
954
 
                 "failed to detect configured nand flash; found %04x instead of\n",
955
 
                 id);
956
 
fail_detect:
957
 
        return -ENODEV;
958
 
}
959
 
 
960
825
/* the maximum possible buffer size for large page with OOB data
961
826
 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
962
827
 * data buffer and the DMA descriptor
998
863
        return 0;
999
864
}
1000
865
 
1001
 
static struct nand_ecclayout hw_smallpage_ecclayout = {
1002
 
        .eccbytes = 6,
1003
 
        .eccpos = {8, 9, 10, 11, 12, 13 },
1004
 
        .oobfree = { {2, 6} }
1005
 
};
1006
 
 
1007
 
static struct nand_ecclayout hw_largepage_ecclayout = {
1008
 
        .eccbytes = 24,
1009
 
        .eccpos = {
1010
 
                40, 41, 42, 43, 44, 45, 46, 47,
1011
 
                48, 49, 50, 51, 52, 53, 54, 55,
1012
 
                56, 57, 58, 59, 60, 61, 62, 63},
1013
 
        .oobfree = { {2, 38} }
1014
 
};
1015
 
 
1016
 
static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1017
 
                                 struct pxa3xx_nand_info *info)
1018
 
{
1019
 
        struct nand_chip *this = &info->nand_chip;
1020
 
 
1021
 
        this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
1022
 
 
1023
 
        this->waitfunc          = pxa3xx_nand_waitfunc;
1024
 
        this->select_chip       = pxa3xx_nand_select_chip;
1025
 
        this->dev_ready         = pxa3xx_nand_dev_ready;
1026
 
        this->cmdfunc           = pxa3xx_nand_cmdfunc;
1027
 
        this->read_word         = pxa3xx_nand_read_word;
1028
 
        this->read_byte         = pxa3xx_nand_read_byte;
1029
 
        this->read_buf          = pxa3xx_nand_read_buf;
1030
 
        this->write_buf         = pxa3xx_nand_write_buf;
1031
 
        this->verify_buf        = pxa3xx_nand_verify_buf;
1032
 
 
1033
 
        this->ecc.mode          = NAND_ECC_HW;
1034
 
        this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
1035
 
        this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
1036
 
        this->ecc.correct       = pxa3xx_nand_ecc_correct;
1037
 
        this->ecc.size          = info->page_size;
1038
 
 
1039
 
        if (info->page_size == 2048)
1040
 
                this->ecc.layout = &hw_largepage_ecclayout;
1041
 
        else
1042
 
                this->ecc.layout = &hw_smallpage_ecclayout;
1043
 
 
1044
 
        this->chip_delay = 25;
1045
 
}
1046
 
 
1047
 
static int pxa3xx_nand_probe(struct platform_device *pdev)
1048
 
{
1049
 
        struct pxa3xx_nand_platform_data *pdata;
 
866
static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 
867
{
 
868
        struct mtd_info *mtd = info->mtd;
 
869
        struct nand_chip *chip = mtd->priv;
 
870
 
 
871
        /* use the common timing to make a try */
 
872
        pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 
873
        chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 
874
        if (info->is_ready)
 
875
                return 1;
 
876
        else
 
877
                return 0;
 
878
}
 
879
 
 
880
static int pxa3xx_nand_scan(struct mtd_info *mtd)
 
881
{
 
882
        struct pxa3xx_nand_info *info = mtd->priv;
 
883
        struct platform_device *pdev = info->pdev;
 
884
        struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 
885
        struct nand_flash_dev pxa3xx_flash_ids[2] = { {NULL,}, {NULL,} };
 
886
        const struct pxa3xx_nand_flash *f = NULL;
 
887
        struct nand_chip *chip = mtd->priv;
 
888
        uint32_t id = -1;
 
889
        uint64_t chipsize;
 
890
        int i, ret, num;
 
891
 
 
892
        if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
 
893
                goto KEEP_CONFIG;
 
894
 
 
895
        ret = pxa3xx_nand_sensing(info);
 
896
        if (!ret) {
 
897
                kfree(mtd);
 
898
                info->mtd = NULL;
 
899
                printk(KERN_INFO "There is no nand chip on cs 0!\n");
 
900
 
 
901
                return -EINVAL;
 
902
        }
 
903
 
 
904
        chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
 
905
        id = *((uint16_t *)(info->data_buff));
 
906
        if (id != 0)
 
907
                printk(KERN_INFO "Detect a flash id %x\n", id);
 
908
        else {
 
909
                kfree(mtd);
 
910
                info->mtd = NULL;
 
911
                printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
 
912
 
 
913
                return -EINVAL;
 
914
        }
 
915
 
 
916
        num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
 
917
        for (i = 0; i < num; i++) {
 
918
                if (i < pdata->num_flash)
 
919
                        f = pdata->flash + i;
 
920
                else
 
921
                        f = &builtin_flash_types[i - pdata->num_flash + 1];
 
922
 
 
923
                /* find the chip in default list */
 
924
                if (f->chip_id == id)
 
925
                        break;
 
926
        }
 
927
 
 
928
        if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
 
929
                kfree(mtd);
 
930
                info->mtd = NULL;
 
931
                printk(KERN_ERR "ERROR!! flash not defined!!!\n");
 
932
 
 
933
                return -EINVAL;
 
934
        }
 
935
 
 
936
        pxa3xx_nand_config_flash(info, f);
 
937
        pxa3xx_flash_ids[0].name = f->name;
 
938
        pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
 
939
        pxa3xx_flash_ids[0].pagesize = f->page_size;
 
940
        chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
 
941
        pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
 
942
        pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
 
943
        if (f->flash_width == 16)
 
944
                pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
 
945
KEEP_CONFIG:
 
946
        if (nand_scan_ident(mtd, 1, pxa3xx_flash_ids))
 
947
                return -ENODEV;
 
948
        /* calculate addressing information */
 
949
        info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
 
950
        info->oob_buff = info->data_buff + mtd->writesize;
 
951
        if ((mtd->size >> chip->page_shift) > 65536)
 
952
                info->row_addr_cycles = 3;
 
953
        else
 
954
                info->row_addr_cycles = 2;
 
955
        mtd->name = mtd_names[0];
 
956
        chip->ecc.mode = NAND_ECC_HW;
 
957
        chip->ecc.size = f->page_size;
 
958
 
 
959
        chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0;
 
960
        chip->options |= NAND_NO_AUTOINCR;
 
961
        chip->options |= NAND_NO_READRDY;
 
962
 
 
963
        return nand_scan_tail(mtd);
 
964
}
 
965
 
 
966
static
 
967
struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
 
968
{
1050
969
        struct pxa3xx_nand_info *info;
1051
 
        struct nand_chip *this;
 
970
        struct nand_chip *chip;
1052
971
        struct mtd_info *mtd;
1053
972
        struct resource *r;
1054
 
        int ret = 0, irq;
1055
 
 
1056
 
        pdata = pdev->dev.platform_data;
1057
 
 
1058
 
        if (!pdata) {
1059
 
                dev_err(&pdev->dev, "no platform data defined\n");
1060
 
                return -ENODEV;
1061
 
        }
 
973
        int ret, irq;
1062
974
 
1063
975
        mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1064
976
                        GFP_KERNEL);
1065
977
        if (!mtd) {
1066
978
                dev_err(&pdev->dev, "failed to allocate memory\n");
1067
 
                return -ENOMEM;
 
979
                return NULL;
1068
980
        }
1069
981
 
1070
982
        info = (struct pxa3xx_nand_info *)(&mtd[1]);
 
983
        chip = (struct nand_chip *)(&mtd[1]);
1071
984
        info->pdev = pdev;
1072
 
 
1073
 
        this = &info->nand_chip;
 
985
        info->mtd = mtd;
1074
986
        mtd->priv = info;
1075
987
        mtd->owner = THIS_MODULE;
1076
988
 
 
989
        chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
 
990
        chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
 
991
        chip->controller        = &info->controller;
 
992
        chip->waitfunc          = pxa3xx_nand_waitfunc;
 
993
        chip->select_chip       = pxa3xx_nand_select_chip;
 
994
        chip->dev_ready         = pxa3xx_nand_dev_ready;
 
995
        chip->cmdfunc           = pxa3xx_nand_cmdfunc;
 
996
        chip->read_word         = pxa3xx_nand_read_word;
 
997
        chip->read_byte         = pxa3xx_nand_read_byte;
 
998
        chip->read_buf          = pxa3xx_nand_read_buf;
 
999
        chip->write_buf         = pxa3xx_nand_write_buf;
 
1000
        chip->verify_buf        = pxa3xx_nand_verify_buf;
 
1001
 
 
1002
        spin_lock_init(&chip->controller->lock);
 
1003
        init_waitqueue_head(&chip->controller->wq);
1077
1004
        info->clk = clk_get(&pdev->dev, NULL);
1078
1005
        if (IS_ERR(info->clk)) {
1079
1006
                dev_err(&pdev->dev, "failed to get nand clock\n");
1141
1068
                goto fail_free_buf;
1142
1069
        }
1143
1070
 
1144
 
        ret = pxa3xx_nand_detect_flash(info, pdata);
1145
 
        if (ret) {
1146
 
                dev_err(&pdev->dev, "failed to detect flash\n");
1147
 
                ret = -ENODEV;
1148
 
                goto fail_free_irq;
1149
 
        }
1150
 
 
1151
 
        pxa3xx_nand_init_mtd(mtd, info);
1152
 
 
1153
 
        platform_set_drvdata(pdev, mtd);
1154
 
 
1155
 
        if (nand_scan(mtd, 1)) {
1156
 
                dev_err(&pdev->dev, "failed to scan nand\n");
1157
 
                ret = -ENXIO;
1158
 
                goto fail_free_irq;
1159
 
        }
1160
 
 
1161
 
#ifdef CONFIG_MTD_PARTITIONS
1162
 
        if (mtd_has_cmdlinepart()) {
1163
 
                static const char *probes[] = { "cmdlinepart", NULL };
1164
 
                struct mtd_partition *parts;
1165
 
                int nr_parts;
1166
 
 
1167
 
                nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
1168
 
 
1169
 
                if (nr_parts)
1170
 
                        return add_mtd_partitions(mtd, parts, nr_parts);
1171
 
        }
1172
 
 
1173
 
        return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1174
 
#else
1175
 
        return 0;
1176
 
#endif
1177
 
 
1178
 
fail_free_irq:
 
1071
        platform_set_drvdata(pdev, info);
 
1072
 
 
1073
        return info;
 
1074
 
 
1075
fail_free_buf:
1179
1076
        free_irq(irq, info);
1180
 
fail_free_buf:
1181
1077
        if (use_dma) {
1182
1078
                pxa_free_dma(info->data_dma_ch);
1183
1079
                dma_free_coherent(&pdev->dev, info->data_buff_size,
1193
1089
        clk_put(info->clk);
1194
1090
fail_free_mtd:
1195
1091
        kfree(mtd);
1196
 
        return ret;
 
1092
        return NULL;
1197
1093
}
1198
1094
 
1199
1095
static int pxa3xx_nand_remove(struct platform_device *pdev)
1200
1096
{
1201
 
        struct mtd_info *mtd = platform_get_drvdata(pdev);
1202
 
        struct pxa3xx_nand_info *info = mtd->priv;
 
1097
        struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
 
1098
        struct mtd_info *mtd = info->mtd;
1203
1099
        struct resource *r;
1204
1100
        int irq;
1205
1101
 
1206
1102
        platform_set_drvdata(pdev, NULL);
1207
1103
 
1208
 
        del_mtd_device(mtd);
1209
 
#ifdef CONFIG_MTD_PARTITIONS
1210
 
        del_mtd_partitions(mtd);
1211
 
#endif
1212
1104
        irq = platform_get_irq(pdev, 0);
1213
1105
        if (irq >= 0)
1214
1106
                free_irq(irq, info);
1226
1118
        clk_disable(info->clk);
1227
1119
        clk_put(info->clk);
1228
1120
 
1229
 
        kfree(mtd);
1230
 
        return 0;
 
1121
        if (mtd) {
 
1122
                del_mtd_device(mtd);
 
1123
#ifdef CONFIG_MTD_PARTITIONS
 
1124
                del_mtd_partitions(mtd);
 
1125
#endif
 
1126
                kfree(mtd);
 
1127
        }
 
1128
        return 0;
 
1129
}
 
1130
 
 
1131
static int pxa3xx_nand_probe(struct platform_device *pdev)
 
1132
{
 
1133
        struct pxa3xx_nand_platform_data *pdata;
 
1134
        struct pxa3xx_nand_info *info;
 
1135
 
 
1136
        pdata = pdev->dev.platform_data;
 
1137
        if (!pdata) {
 
1138
                dev_err(&pdev->dev, "no platform data defined\n");
 
1139
                return -ENODEV;
 
1140
        }
 
1141
 
 
1142
        info = alloc_nand_resource(pdev);
 
1143
        if (info == NULL)
 
1144
                return -ENOMEM;
 
1145
 
 
1146
        if (pxa3xx_nand_scan(info->mtd)) {
 
1147
                dev_err(&pdev->dev, "failed to scan nand\n");
 
1148
                pxa3xx_nand_remove(pdev);
 
1149
                return -ENODEV;
 
1150
        }
 
1151
 
 
1152
#ifdef CONFIG_MTD_PARTITIONS
 
1153
        if (mtd_has_cmdlinepart()) {
 
1154
                const char *probes[] = { "cmdlinepart", NULL };
 
1155
                struct mtd_partition *parts;
 
1156
                int nr_parts;
 
1157
 
 
1158
                nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
 
1159
 
 
1160
                if (nr_parts)
 
1161
                        return add_mtd_partitions(info->mtd, parts, nr_parts);
 
1162
        }
 
1163
 
 
1164
        return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
 
1165
#else
 
1166
        return 0;
 
1167
#endif
1231
1168
}
1232
1169
 
1233
1170
#ifdef CONFIG_PM
1234
1171
static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1235
1172
{
1236
 
        struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1237
 
        struct pxa3xx_nand_info *info = mtd->priv;
 
1173
        struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
 
1174
        struct mtd_info *mtd = info->mtd;
1238
1175
 
1239
 
        if (info->state != STATE_READY) {
 
1176
        if (info->state) {
1240
1177
                dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1241
1178
                return -EAGAIN;
1242
1179
        }
1246
1183
 
1247
1184
static int pxa3xx_nand_resume(struct platform_device *pdev)
1248
1185
{
1249
 
        struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1250
 
        struct pxa3xx_nand_info *info = mtd->priv;
 
1186
        struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
 
1187
        struct mtd_info *mtd = info->mtd;
1251
1188
 
1252
1189
        nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1253
1190
        nand_writel(info, NDTR1CS0, info->ndtr1cs0);