65
72
.disable = generic_clk_disable,
75
/* returns current programmed clocks clock info structure */
76
static struct pclk_info *pclk_info_get(struct clk *clk)
79
struct pclk_info *info = NULL;
81
val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
82
& clk->pclk_sel->pclk_sel_mask;
84
for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
85
if (clk->pclk_sel->pclk_info[i].pclk_val == val)
86
info = &clk->pclk_sel->pclk_info[i];
93
* Set Update pclk, and pclk_info of clk and add clock sibling node to current
94
* parents children list
96
static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
100
spin_lock_irqsave(&clocks_lock, flags);
101
list_del(&clk->sibling);
102
list_add(&clk->sibling, &pclk_info->pclk->children);
104
clk->pclk = pclk_info->pclk;
105
spin_unlock_irqrestore(&clocks_lock, flags);
107
#ifdef CONFIG_DEBUG_FS
108
clk_debugfs_reparent(clk);
112
static void do_clk_disable(struct clk *clk)
117
if (!clk->usage_count) {
124
if (clk->usage_count == 0) {
126
* Surely, there are no active childrens or direct users
130
do_clk_disable(clk->pclk);
132
if (clk->ops && clk->ops->disable)
133
clk->ops->disable(clk);
137
static int do_clk_enable(struct clk *clk)
144
if (clk->usage_count == 0) {
146
ret = do_clk_enable(clk->pclk);
150
if (clk->ops && clk->ops->enable) {
151
ret = clk->ops->enable(clk);
154
do_clk_disable(clk->pclk);
159
* Since the clock is going to be used for the first
163
ret = clk->recalc(clk);
69
174
* clk_enable - inform the system when the clock source should be running.
70
175
* @clk: clock source
176
263
/* reflect parent change in hardware */
177
264
val = readl(clk->pclk_sel->pclk_sel_reg);
178
265
val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
179
val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift;
266
val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
180
267
writel(val, clk->pclk_sel->pclk_sel_reg);
181
268
spin_unlock_irqrestore(&clocks_lock, flags);
183
270
/* reflect parent change in software */
185
propagate_rate(&clk->children);
271
clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
273
propagate_rate(clk, 0);
188
276
EXPORT_SYMBOL(clk_set_parent);
279
* clk_set_rate - set the clock rate for a clock source
281
* @rate: desired clock rate in Hz
283
* Returns success (0) or negative errno.
285
int clk_set_rate(struct clk *clk, unsigned long rate)
294
spin_lock_irqsave(&clocks_lock, flags);
295
ret = clk->set_rate(clk, rate);
297
/* if successful -> propagate */
298
propagate_rate(clk, 0);
299
spin_unlock_irqrestore(&clocks_lock, flags);
300
} else if (clk->pclk) {
301
u32 mult = clk->div_factor ? clk->div_factor : 1;
302
ret = clk_set_rate(clk->pclk, mult * rate);
307
EXPORT_SYMBOL(clk_set_rate);
190
309
/* registers clock in platform clock framework */
191
310
void clk_register(struct clk_lookup *cl)
193
struct clk *clk = cl->clk;
194
313
unsigned long flags;
196
if (!clk || IS_ERR(clk))
199
319
spin_lock_irqsave(&clocks_lock, flags);
207
327
/* root clock don't have any parents */
208
328
if (!clk->pclk && !clk->pclk_sel) {
209
329
list_add(&clk->sibling, &root_clks);
330
} else if (clk->pclk && !clk->pclk_sel) {
210
331
/* add clocks with only one parent to parent's children list */
211
} else if (clk->pclk && !clk->pclk_sel) {
212
332
list_add(&clk->sibling, &clk->pclk->children);
214
/* add clocks with > 1 parent to 1st parent's children list */
215
list_add(&clk->sibling,
216
&clk->pclk_sel->pclk_info[0].pclk->children);
334
/* clocks with more than one parent */
335
struct pclk_info *pclk_info;
337
pclk_info = pclk_info_get(clk);
339
pr_err("CLKDEV: invalid pclk info of clk with"
340
" %s dev_id and %s con_id\n",
341
cl->dev_id, cl->con_id);
343
clk->pclk = pclk_info->pclk;
344
list_add(&clk->sibling, &pclk_info->pclk->children);
218
348
spin_unlock_irqrestore(&clocks_lock, flags);
350
/* debugfs specific */
351
#ifdef CONFIG_DEBUG_FS
352
list_add(&clk->node, &clocks);
220
356
/* add clock to arm clockdev framework */
225
* propagate_rate - recalculate and propagate all clocks in list head
227
* Recalculates all root clocks in list head, which if the clock's .recalc is
228
* set correctly, should also propagate their rates.
230
static void propagate_rate(struct list_head *lhead)
232
struct clk *clkp, *_temp;
234
list_for_each_entry_safe(clkp, _temp, lhead, sibling) {
237
propagate_rate(&clkp->children);
241
/* returns current programmed clocks clock info structure */
242
static struct pclk_info *pclk_info_get(struct clk *clk)
244
unsigned int mask, i;
246
struct pclk_info *info = NULL;
248
spin_lock_irqsave(&clocks_lock, flags);
249
mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
250
& clk->pclk_sel->pclk_sel_mask;
252
for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
253
if (clk->pclk_sel->pclk_info[i].pclk_mask == mask)
254
info = &clk->pclk_sel->pclk_info[i];
256
spin_unlock_irqrestore(&clocks_lock, flags);
361
* propagate_rate - recalculate and propagate all clocks to children
362
* @pclk: parent clock required to be propogated
363
* @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
365
* Recalculates all children clocks
367
void propagate_rate(struct clk *pclk, int on_init)
369
struct clk *clk, *_temp;
372
list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
374
ret = clk->recalc(clk);
376
* recalc will return error if clk out is not programmed
377
* In this case configure default rate.
379
if (ret && clk->set_rate)
380
clk->set_rate(clk, 0);
382
propagate_rate(clk, on_init);
387
/* Enable clks enabled on init, in software view */
388
if (clk->flags & ENABLED_ON_INIT)
394
* round_rate_index - return closest programmable rate index in rate_config tbl
395
* @clk: ptr to clock structure
396
* @drate: desired rate
397
* @rate: final rate will be returned in this variable only.
399
* Finds index in rate_config for highest clk rate which is less than
400
* requested rate. If there is no clk rate lesser than requested rate then
401
* -EINVAL is returned. This routine assumes that rate_config is written
402
* in incrementing order of clk rates.
403
* If drate passed is zero then default rate is programmed.
406
round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
408
unsigned long tmp = 0, prev_rate = 0;
418
* This loops ends on two conditions:
419
* - as soon as clk is found with rate greater than requested rate.
420
* - if all clks in rate_config are smaller than requested rate.
422
for (index = 0; index < clk->rate_config.count; index++) {
424
tmp = clk->calc_rate(clk, index);
430
/* return if can't find suitable clock */
434
} else if (index == clk->rate_config.count) {
435
/* program with highest clk rate possible */
436
index = clk->rate_config.count - 1;
445
* clk_round_rate - adjust a rate to the exact rate a clock can provide
447
* @rate: desired clock rate in Hz
449
* Returns rounded clock rate in Hz, or negative errno.
451
long clk_round_rate(struct clk *clk, unsigned long drate)
457
* propagate call to parent who supports calc_rate. Similar approach is
458
* used in clk_set_rate.
460
if (!clk->calc_rate) {
465
mult = clk->div_factor ? clk->div_factor : 1;
466
return clk_round_rate(clk->pclk, mult * drate) / mult;
469
index = round_rate_index(clk, drate, &rate);
475
EXPORT_SYMBOL(clk_round_rate);
477
/*All below functions are called with lock held */
262
* Set pclk as cclk's parent and add clock sibling node to current parents
480
* Calculates pll clk rate for specific value of mode, m, n and p
483
* rate = (2 * M[15:8] * Fin)/(N * 2^P)
486
* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
265
static void change_parent(struct clk *cclk, struct clk *pclk)
488
unsigned long pll_calc_rate(struct clk *clk, int index)
269
spin_lock_irqsave(&clocks_lock, flags);
270
list_del(&cclk->sibling);
271
list_add(&cclk->sibling, &pclk->children);
274
spin_unlock_irqrestore(&clocks_lock, flags);
490
unsigned long rate = clk->pclk->rate;
491
struct pll_rate_tbl *tbls = clk->rate_config.tbls;
494
mode = tbls[index].mode ? 256 : 1;
495
return (((2 * rate / 10000) * tbls[index].m) /
496
(mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
283
505
* In Dithered mode
284
506
* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
286
void pll1_clk_recalc(struct clk *clk)
508
int pll_clk_recalc(struct clk *clk)
288
510
struct pll_clk_config *config = clk->private_data;
289
511
unsigned int num = 2, den = 0, val, mode = 0;
292
spin_lock_irqsave(&clocks_lock, flags);
293
mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
513
mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
514
config->masks->mode_mask;
296
516
val = readl(config->cfg_reg);
297
517
/* calculate denominator */
298
den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
518
den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
300
den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
520
den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
302
522
/* calculate numerator & denominator */
304
524
/* Normal mode */
305
num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
525
num *= (val >> config->masks->norm_fdbk_m_shift) &
526
config->masks->norm_fdbk_m_mask;
307
528
/* Dithered mode */
308
num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
529
num *= (val >> config->masks->dith_fdbk_m_shift) &
530
config->masks->dith_fdbk_m_mask;
312
537
clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
313
spin_unlock_irqrestore(&clocks_lock, flags);
542
* Configures new clock rate of pll
544
int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
546
struct pll_rate_tbl *tbls = clk->rate_config.tbls;
547
struct pll_clk_config *config = clk->private_data;
548
unsigned long val, rate;
551
i = round_rate_index(clk, desired_rate, &rate);
555
val = readl(config->mode_reg) &
556
~(config->masks->mode_mask << config->masks->mode_shift);
557
val |= (tbls[i].mode & config->masks->mode_mask) <<
558
config->masks->mode_shift;
559
writel(val, config->mode_reg);
561
val = readl(config->cfg_reg) &
562
~(config->masks->div_p_mask << config->masks->div_p_shift);
563
val |= (tbls[i].p & config->masks->div_p_mask) <<
564
config->masks->div_p_shift;
565
val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
566
val |= (tbls[i].n & config->masks->div_n_mask) <<
567
config->masks->div_n_shift;
568
val &= ~(config->masks->dith_fdbk_m_mask <<
569
config->masks->dith_fdbk_m_shift);
571
val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
572
config->masks->dith_fdbk_m_shift;
574
val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
575
config->masks->norm_fdbk_m_shift;
577
writel(val, config->cfg_reg);
585
* Calculates ahb, apb clk rate for specific value of div
587
unsigned long bus_calc_rate(struct clk *clk, int index)
589
unsigned long rate = clk->pclk->rate;
590
struct bus_rate_tbl *tbls = clk->rate_config.tbls;
592
return rate / (tbls[index].div + 1);
316
595
/* calculates current programmed rate of ahb or apb bus */
317
void bus_clk_recalc(struct clk *clk)
596
int bus_clk_recalc(struct clk *clk)
319
598
struct bus_clk_config *config = clk->private_data;
320
599
unsigned int div;
323
spin_lock_irqsave(&clocks_lock, flags);
324
div = ((readl(config->reg) >> config->shift) & config->mask) + 1;
601
div = ((readl(config->reg) >> config->masks->shift) &
602
config->masks->mask) + 1;
325
607
clk->rate = (unsigned long)clk->pclk->rate / div;
326
spin_unlock_irqrestore(&clocks_lock, flags);
611
/* Configures new clock rate of AHB OR APB bus */
612
int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
614
struct bus_rate_tbl *tbls = clk->rate_config.tbls;
615
struct bus_clk_config *config = clk->private_data;
616
unsigned long val, rate;
619
i = round_rate_index(clk, desired_rate, &rate);
623
val = readl(config->reg) &
624
~(config->masks->mask << config->masks->shift);
625
val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
626
writel(val, config->reg);
634
* gives rate for different values of eq, x and y
636
* Fout from synthesizer can be given from two equations:
637
* Fout1 = (Fin * X/Y)/2 EQ1
638
* Fout2 = Fin * X/Y EQ2
640
unsigned long aux_calc_rate(struct clk *clk, int index)
642
unsigned long rate = clk->pclk->rate;
643
struct aux_rate_tbl *tbls = clk->rate_config.tbls;
644
u8 eq = tbls[index].eq ? 1 : 2;
646
return (((rate/10000) * tbls[index].xscale) /
647
(tbls[index].yscale * eq)) * 10000;
337
658
* Selection of eqn 1 or 2 is programmed in register
339
void aux_clk_recalc(struct clk *clk)
660
int aux_clk_recalc(struct clk *clk)
341
662
struct aux_clk_config *config = clk->private_data;
342
struct pclk_info *pclk_info = NULL;
343
663
unsigned int num = 1, den = 1, val, eqn;
346
/* get current programmed parent */
347
pclk_info = pclk_info_get(clk);
349
spin_lock_irqsave(&clocks_lock, flags);
352
spin_unlock_irqrestore(&clocks_lock, flags);
356
change_parent(clk, pclk_info->pclk);
358
spin_lock_irqsave(&clocks_lock, flags);
359
if (pclk_info->scalable) {
360
val = readl(config->synth_reg);
362
eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK;
363
if (eqn == AUX_EQ1_SEL)
366
/* calculate numerator */
367
num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK;
369
/* calculate denominator */
370
den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK;
371
val = (((clk->pclk->rate/10000) * num) / den) * 10000;
373
val = clk->pclk->rate;
376
spin_unlock_irqrestore(&clocks_lock, flags);
665
val = readl(config->synth_reg);
667
eqn = (val >> config->masks->eq_sel_shift) &
668
config->masks->eq_sel_mask;
669
if (eqn == config->masks->eq1_mask)
672
/* calculate numerator */
673
num = (val >> config->masks->xscale_sel_shift) &
674
config->masks->xscale_sel_mask;
676
/* calculate denominator */
677
den *= (val >> config->masks->yscale_sel_shift) &
678
config->masks->yscale_sel_mask;
683
clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
687
/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
688
int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
690
struct aux_rate_tbl *tbls = clk->rate_config.tbls;
691
struct aux_clk_config *config = clk->private_data;
692
unsigned long val, rate;
695
i = round_rate_index(clk, desired_rate, &rate);
699
val = readl(config->synth_reg) &
700
~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
701
val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
702
config->masks->eq_sel_shift;
703
val &= ~(config->masks->xscale_sel_mask <<
704
config->masks->xscale_sel_shift);
705
val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
706
config->masks->xscale_sel_shift;
707
val &= ~(config->masks->yscale_sel_mask <<
708
config->masks->yscale_sel_shift);
709
val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
710
config->masks->yscale_sel_shift;
711
writel(val, config->synth_reg);
719
* Calculates gpt clk rate for different values of mscale and nscale
721
* Fout= Fin/((2 ^ (N+1)) * (M+1))
723
unsigned long gpt_calc_rate(struct clk *clk, int index)
725
unsigned long rate = clk->pclk->rate;
726
struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
728
return rate / ((1 << (tbls[index].nscale + 1)) *
729
(tbls[index].mscale + 1));
381
734
* Fout from synthesizer can be given from below equations:
382
735
* Fout= Fin/((2 ^ (N+1)) * (M+1))
384
void gpt_clk_recalc(struct clk *clk)
737
int gpt_clk_recalc(struct clk *clk)
386
struct aux_clk_config *config = clk->private_data;
387
struct pclk_info *pclk_info = NULL;
739
struct gpt_clk_config *config = clk->private_data;
388
740
unsigned int div = 1, val;
391
pclk_info = pclk_info_get(clk);
393
spin_lock_irqsave(&clocks_lock, flags);
396
spin_unlock_irqrestore(&clocks_lock, flags);
400
change_parent(clk, pclk_info->pclk);
402
spin_lock_irqsave(&clocks_lock, flags);
403
if (pclk_info->scalable) {
404
val = readl(config->synth_reg);
405
div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK;
406
div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
742
val = readl(config->synth_reg);
743
div += (val >> config->masks->mscale_sel_shift) &
744
config->masks->mscale_sel_mask;
745
div *= 1 << (((val >> config->masks->nscale_sel_shift) &
746
config->masks->nscale_sel_mask) + 1);
409
751
clk->rate = (unsigned long)clk->pclk->rate / div;
410
spin_unlock_irqrestore(&clocks_lock, flags);
414
* Used for clocks that always have same value as the parent clock divided by a
755
/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
756
int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
758
struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
759
struct gpt_clk_config *config = clk->private_data;
760
unsigned long val, rate;
763
i = round_rate_index(clk, desired_rate, &rate);
767
val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
768
config->masks->mscale_sel_shift);
769
val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
770
config->masks->mscale_sel_shift;
771
val &= ~(config->masks->nscale_sel_mask <<
772
config->masks->nscale_sel_shift);
773
val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
774
config->masks->nscale_sel_shift;
775
writel(val, config->synth_reg);
783
* Calculates clcd clk rate for different values of div
785
* Fout from synthesizer can be given from below equation:
786
* Fout= Fin/2*div (division factor)
788
* 0-13 (fractional part)
789
* 14-16 (integer part)
790
* To calculate Fout we left shift val by 14 bits and divide Fin by
791
* complete div (including fractional part) and then right shift the
792
* result by 14 places.
794
unsigned long clcd_calc_rate(struct clk *clk, int index)
796
unsigned long rate = clk->pclk->rate;
797
struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
801
rate /= (2 * tbls[index].div);
809
* calculates current programmed rate of clcd synthesizer
810
* Fout from synthesizer can be given from below equation:
811
* Fout= Fin/2*div (division factor)
813
* 0-13 (fractional part)
814
* 14-16 (integer part)
815
* To calculate Fout we left shift val by 14 bits and divide Fin by
816
* complete div (including fractional part) and then right shift the
817
* result by 14 places.
819
int clcd_clk_recalc(struct clk *clk)
821
struct clcd_clk_config *config = clk->private_data;
822
unsigned int div = 1;
826
val = readl(config->synth_reg);
827
div = (val >> config->masks->div_factor_shift) &
828
config->masks->div_factor_mask;
833
prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
835
clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
840
/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
841
int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
843
struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
844
struct clcd_clk_config *config = clk->private_data;
845
unsigned long val, rate;
848
i = round_rate_index(clk, desired_rate, &rate);
852
val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
853
config->masks->div_factor_shift);
854
val |= (tbls[i].div & config->masks->div_factor_mask) <<
855
config->masks->div_factor_shift;
856
writel(val, config->synth_reg);
864
* Used for clocks that always have value as the parent clock divided by a
417
void follow_parent(struct clk *clk)
867
int follow_parent(struct clk *clk)
869
unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
421
spin_lock_irqsave(&clocks_lock, flags);
422
clk->rate = clk->pclk->rate;
423
spin_unlock_irqrestore(&clocks_lock, flags);
871
clk->rate = clk->pclk->rate/div_factor;
432
881
void recalc_root_clocks(void)
434
propagate_rate(&root_clks);
887
spin_lock_irqsave(&clocks_lock, flags);
888
list_for_each_entry(pclk, &root_clks, sibling) {
890
ret = pclk->recalc(pclk);
892
* recalc will return error if clk out is not programmed
893
* In this case configure default clock.
895
if (ret && pclk->set_rate)
896
pclk->set_rate(pclk, 0);
898
propagate_rate(pclk, 1);
899
/* Enable clks enabled on init, in software view */
900
if (pclk->flags & ENABLED_ON_INIT)
903
spin_unlock_irqrestore(&clocks_lock, flags);
906
#ifdef CONFIG_DEBUG_FS
908
* debugfs support to trace clock tree hierarchy and attributes
910
static struct dentry *clk_debugfs_root;
911
static int clk_debugfs_register_one(struct clk *c)
914
struct dentry *d, *child;
915
struct clk *pa = c->pclk;
921
p += sprintf(p, "%s", c->cl->con_id);
923
p += sprintf(p, "%s", c->cl->dev_id);
925
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
930
d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
931
(u32 *)&c->usage_count);
936
d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
941
d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
950
list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
951
debugfs_remove(child);
952
debugfs_remove(c->dent);
956
static int clk_debugfs_register(struct clk *c)
959
struct clk *pa = c->pclk;
961
if (pa && !pa->dent) {
962
err = clk_debugfs_register(pa);
968
err = clk_debugfs_register_one(c);
975
static int __init clk_debugfs_init(void)
981
d = debugfs_create_dir("clock", NULL);
984
clk_debugfs_root = d;
986
list_for_each_entry(c, &clocks, node) {
987
err = clk_debugfs_register(c);
993
debugfs_remove_recursive(clk_debugfs_root);
996
late_initcall(clk_debugfs_init);
998
static int clk_debugfs_reparent(struct clk *c)
1000
debugfs_remove(c->dent);
1001
return clk_debugfs_register_one(c);
1003
#endif /* CONFIG_DEBUG_FS */
added
removed
arch/arm/plat-spear/clock.c
