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/**************************************************************************
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* Copyright (c) 2007-2008, Intel Corporation.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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**************************************************************************/
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#include <linux/version.h>
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#include "drm_global.h"
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#include "psb_intel_drv.h"
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#include "psb_powermgmt.h"
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#include "ttm/ttm_object.h"
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#include "psb_ttm_fence_driver.h"
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#include "psb_ttm_userobj_api.h"
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#include "ttm/ttm_bo_driver.h"
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#include "ttm/ttm_lock.h"
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/*Append new drm mode definition here, align with libdrm definition*/
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#define DRM_MODE_SCALE_NO_SCALE 2
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extern struct ttm_bo_driver psb_ttm_bo_driver;
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#define DRIVER_NAME "pvrsrvkm"
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#define DRIVER_DESC "drm driver for the Intel GMA500"
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#define DRIVER_AUTHOR "Intel Corporation"
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#define OSPM_PROC_ENTRY "ospm"
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#define RTPM_PROC_ENTRY "rtpm"
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#define BLC_PROC_ENTRY "mrst_blc"
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#define DISPLAY_PROC_ENTRY "display_status"
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#define PSB_DRM_DRIVER_DATE "2009-03-10"
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#define PSB_DRM_DRIVER_MAJOR 8
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#define PSB_DRM_DRIVER_MINOR 1
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#define PSB_DRM_DRIVER_PATCHLEVEL 0
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*TTM driver private offsets.
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#define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
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#define PSB_OBJECT_HASH_ORDER 13
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#define PSB_FILE_OBJECT_HASH_ORDER 12
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#define PSB_BO_HASH_ORDER 12
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#define PSB_VDC_OFFSET 0x00000000
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#define PSB_VDC_SIZE 0x000080000
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#define MRST_MMIO_SIZE 0x0000C0000
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#define MDFLD_MMIO_SIZE 0x000100000
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#define PSB_SGX_SIZE 0x8000
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#define PSB_SGX_OFFSET 0x00040000
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#define MRST_SGX_OFFSET 0x00080000
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#define PSB_MMIO_RESOURCE 0
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#define PSB_GATT_RESOURCE 2
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#define PSB_GTT_RESOURCE 3
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#define PSB_GMCH_CTRL 0x52
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#define _PSB_GMCH_ENABLED 0x4
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#define PSB_PGETBL_CTL 0x2020
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#define _PSB_PGETBL_ENABLED 0x00000001
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#define PSB_SGX_2D_SLAVE_PORT 0x4000
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#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
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#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
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#define PSB_NUM_VALIDATE_BUFFERS 2048
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#define PSB_MEM_MMU_START 0x00000000
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#define PSB_MEM_TT_START 0xE0000000
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#define PSB_GL3_CACHE_CTL 0x2100
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#define PSB_GL3_CACHE_STAT 0x2108
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*Flags for external memory type field.
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#define MRST_MSVDX_OFFSET 0x90000 /*MSVDX Base offset */
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#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
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/* MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
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#define PSB_MSVDX_SIZE 0x10000
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#define LNC_TOPAZ_OFFSET 0xA0000
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#define PNW_TOPAZ_OFFSET 0xC0000
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#define PNW_GL3_OFFSET 0xB0000
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#define LNC_TOPAZ_SIZE 0x10000
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#define PNW_TOPAZ_SIZE 0x30000 /* PNW VXE285 has two cores */
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#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
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#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
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#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
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#define PSB_PDE_MASK 0x003FFFFF
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#define PSB_PDE_SHIFT 22
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#define PSB_PTE_SHIFT 12
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#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
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#define PSB_PTE_WO 0x0002 /* Write only */
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#define PSB_PTE_RO 0x0004 /* Read only */
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#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
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*VDC registers and bits
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#define PSB_MSVDX_CLOCKGATING 0x2064
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#define PSB_TOPAZ_CLOCKGATING 0x2068
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#define PSB_HWSTAM 0x2098
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#define PSB_INSTPM 0x20C0
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#define PSB_INT_IDENTITY_R 0x20A4
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#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
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#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
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#define _PSB_DPST_PIPEB_FLAG (1<<4)
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#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
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#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
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#define _PSB_DPST_PIPEA_FLAG (1<<6)
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#define _PSB_PIPEA_EVENT_FLAG (1<<6)
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#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
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#define _MDFLD_MIPIA_FLAG (1<<16)
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#define _MDFLD_MIPIC_FLAG (1<<17)
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#define _PSB_IRQ_SGX_FLAG (1<<18)
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#define _PSB_IRQ_MSVDX_FLAG (1<<19)
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#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
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/* This flag includes all the display IRQ bits excepts the vblank irqs. */
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#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
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_PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
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#define PSB_INT_IDENTITY_R 0x20A4
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#define PSB_INT_MASK_R 0x20A8
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#define PSB_INT_ENABLE_R 0x20A0
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#define _PSB_MMU_ER_MASK 0x0001FF00
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#define _PSB_MMU_ER_HOST (1 << 16)
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#define GPIO_CLOCK_DIR_MASK (1 << 0)
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#define GPIO_CLOCK_DIR_IN (0 << 1)
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#define GPIO_CLOCK_DIR_OUT (1 << 1)
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#define GPIO_CLOCK_VAL_MASK (1 << 2)
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#define GPIO_CLOCK_VAL_OUT (1 << 3)
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#define GPIO_CLOCK_VAL_IN (1 << 4)
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#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
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#define GPIO_DATA_DIR_MASK (1 << 8)
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#define GPIO_DATA_DIR_IN (0 << 9)
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#define GPIO_DATA_DIR_OUT (1 << 9)
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#define GPIO_DATA_VAL_MASK (1 << 10)
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#define GPIO_DATA_VAL_OUT (1 << 11)
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#define GPIO_DATA_VAL_IN (1 << 12)
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#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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#define VCLK_DIVISOR_VGA0 0x6000
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#define VCLK_DIVISOR_VGA1 0x6004
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#define VCLK_POST_DIV 0x6010
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#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
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#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
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#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
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#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
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#define PSB_COMM_USER_IRQ (1024 >> 2)
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#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
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#define PSB_COMM_FW (2048 >> 2)
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#define PSB_UIRQ_VISTEST 1
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#define PSB_UIRQ_OOM_REPLY 2
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#define PSB_UIRQ_FIRE_TA_REPLY 3
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#define PSB_UIRQ_FIRE_RASTER_REPLY 4
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
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#define PSB_LID_DELAY (DRM_HZ / 10)
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#define MDFLD_PNW_A0 0x00
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#define MDFLD_PNW_B0 0x04
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#define MDFLD_PNW_C0 0x08
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#define MDFLD_DSR_2D_3D_0 BIT0
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#define MDFLD_DSR_2D_3D_2 BIT1
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#define MDFLD_DSR_CURSOR_0 BIT2
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#define MDFLD_DSR_CURSOR_2 BIT3
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#define MDFLD_DSR_OVERLAY_0 BIT4
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#define MDFLD_DSR_OVERLAY_2 BIT5
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#define MDFLD_DSR_MIPI_CONTROL BIT6
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#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
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#define MDFLD_DSR_RR 45
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#define MDFLD_DPU_ENABLE BIT31
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#define MDFLD_DSR_FULLSCREEN BIT30
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#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
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#define PSB_PWR_STATE_ON 1
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#define PSB_PWR_STATE_OFF 2
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#define PSB_PMPOLICY_NOPM 0
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#define PSB_PMPOLICY_CLOCKGATING 1
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#define PSB_PMPOLICY_POWERDOWN 2
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#define PSB_PMSTATE_POWERUP 0
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#define PSB_PMSTATE_CLOCKGATED 1
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#define PSB_PMSTATE_POWERDOWN 2
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#define PSB_PCIx_MSI_ADDR_LOC 0x94
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#define PSB_PCIx_MSI_DATA_LOC 0x98
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#define MDFLD_PLANE_MAX_WIDTH 2048
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#define MDFLD_PLANE_MAX_HEIGHT 2048
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struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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struct opregion_asle;
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struct psb_intel_opregion {
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struct opregion_header *header;
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struct opregion_acpi *acpi;
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struct opregion_swsci *swsci;
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struct opregion_asle *asle;
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struct drm_psb_uopt {
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int pad; /*keep it here in case we use it in future*/
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*@buffers: array of pre-allocated validate buffers.
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*@used_buffers: number of buffers in @buffers array currently in use.
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*@validate_buffer: buffers validated from user-space.
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*@kern_validate_buffers : buffers validated from kernel-space.
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*@fence_flags : Fence flags to be used for fence creation.
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*This structure is used during execbuf validation.
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struct psb_validate_buffer *buffers;
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uint32_t used_buffers;
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struct list_head validate_list;
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struct list_head kern_validate_list;
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uint32_t fence_types;
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struct psb_validate_buffer;
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/* Currently defined profiles */
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VAProfileMPEG2Simple = 0,
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VAProfileMPEG2Main = 1,
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VAProfileMPEG4Simple = 2,
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VAProfileMPEG4AdvancedSimple = 3,
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VAProfileMPEG4Main = 4,
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VAProfileH264Baseline = 5,
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VAProfileH264Main = 6,
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VAProfileH264High = 7,
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VAProfileVC1Simple = 8,
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VAProfileVC1Main = 9,
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VAProfileVC1Advanced = 10,
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VAProfileH263Baseline = 11,
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VAProfileJPEGBaseline = 12,
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VAProfileH264ConstrainedBaseline = 13
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/* Currently defined entrypoints */
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VAEntrypointIDCT = 3,
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VAEntrypointMoComp = 4,
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VAEntrypointDeblocking = 5,
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VAEntrypointEncSlice = 6, /* slice level encode */
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VAEntrypointEncPicture = 7 /* pictuer encode, JPEG, etc */
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struct psb_video_ctx {
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struct list_head head;
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struct file *filp; /* DRM device file pointer */
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int ctx_type; /* profile<<8|entrypoint */
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/* todo: more context specific data for multi-context support */
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#define MODE_SETTING_IN_CRTC 0x1
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#define MODE_SETTING_IN_ENCODER 0x2
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#define MODE_SETTING_ON_GOING 0x3
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#define MODE_SETTING_IN_DSR 0x4
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#define MODE_SETTING_ENCODER_DONE 0x8
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#define GCT_R10_HEADER_SIZE 16
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#define GCT_R10_DISPLAY_DESC_SIZE 28
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struct drm_psb_private {
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void * dsi_configs[2];
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struct drm_global_reference mem_global_ref;
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struct ttm_bo_global_ref bo_global_ref;
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struct drm_device *dev;
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struct ttm_object_device *tdev;
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struct ttm_fence_device fdev;
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struct ttm_bo_device bdev;
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struct ttm_lock ttm_lock;
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struct vm_operations_struct *ttm_vm_ops;
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int has_fence_device;
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unsigned long chipset;
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struct drm_psb_uopt uopt;
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/*GTT Memory manager*/
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struct psb_gtt_mm *gtt_mm;
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struct page *scratch_page;
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uint32_t sequence[PSB_NUM_ENGINES];
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uint32_t last_sequence[PSB_NUM_ENGINES];
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uint32_t last_submitted_seq[PSB_NUM_ENGINES];
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struct psb_mmu_driver *mmu;
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struct psb_mmu_pd *pf_pd;
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uint32_t gatt_free_offset;
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/* IMG video context */
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struct list_head video_ctx;
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uint32_t vdc_irq_mask;
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uint32_t pipestat[PSB_NUM_PIPE];
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bool vblanksEnabledForFlips;
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spinlock_t irqmask_lock;
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spinlock_t sequence_lock;
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struct psb_intel_mode_device mode_dev;
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struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
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struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
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unsigned int ci_region_start;
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unsigned int ci_region_size;
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unsigned int rar_region_start;
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unsigned int rar_region_size;
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struct mutex temp_mem;
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*Relocation buffer mapping.
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spinlock_t reloc_lock;
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unsigned int rel_mapped_pages;
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wait_queue_head_t rel_mapped_queue;
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struct drm_psb_sarea *sarea_priv;
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struct drm_psb_sizes_arg sizes;
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uint32_t fuse_reg_value;
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/* pci revision id for B0:D2:F0 */
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uint8_t platform_rev_id;
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int backlight_duty_cycle; /* restore backlight to this value */
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bool panel_wants_dither;
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struct drm_display_mode *panel_fixed_mode;
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struct drm_display_mode *lfp_lvds_vbt_mode;
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struct drm_display_mode *sdvo_lvds_vbt_mode;
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struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/
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struct psb_intel_i2c_chan *lvds_i2c_bus;
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/* Feature bits from the VBIOS*/
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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unsigned int core_freq;
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uint32_t iLVDS_enable;
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uint32_t saveDSPACNTR;
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uint32_t saveDSPBCNTR;
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uint32_t savePIPEACONF;
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uint32_t savePIPEBCONF;
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uint32_t savePIPEASRC;
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uint32_t savePIPEBSRC;
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uint32_t saveDPLL_A_MD;
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uint32_t saveHTOTAL_A;
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uint32_t saveHBLANK_A;
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uint32_t saveHSYNC_A;
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uint32_t saveVTOTAL_A;
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uint32_t saveVBLANK_A;
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uint32_t saveVSYNC_A;
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uint32_t saveDSPASTRIDE;
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uint32_t saveDSPASIZE;
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uint32_t saveDSPAPOS;
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uint32_t saveDSPABASE;
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uint32_t saveDSPASURF;
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uint32_t saveDPLL_B_MD;
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uint32_t saveHTOTAL_B;
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uint32_t saveHBLANK_B;
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uint32_t saveHSYNC_B;
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uint32_t saveVTOTAL_B;
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uint32_t saveVBLANK_B;
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uint32_t saveVSYNC_B;
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uint32_t saveDSPBSTRIDE;
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uint32_t saveDSPBSIZE;
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uint32_t saveDSPBPOS;
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uint32_t saveDSPBBASE;
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uint32_t saveDSPBSURF;
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uint32_t saveVCLK_DIVISOR_VGA0;
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uint32_t saveVCLK_DIVISOR_VGA1;
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uint32_t saveVCLK_POST_DIV;
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uint32_t saveVGACNTRL;
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uint32_t savePP_CONTROL;
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uint32_t savePP_CYCLE;
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uint32_t savePFIT_CONTROL;
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uint32_t savePaletteA[256];
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uint32_t savePaletteB[256];
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uint32_t saveBLC_PWM_CTL2;
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uint32_t saveBLC_PWM_CTL;
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uint32_t saveCLOCKGATING;
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uint32_t saveDSPATILEOFF;
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uint32_t saveDSPBTILEOFF;
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uint32_t saveDSPAADDR;
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uint32_t saveDSPBADDR;
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uint32_t savePFIT_AUTO_RATIOS;
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uint32_t savePFIT_PGM_RATIOS;
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uint32_t savePP_ON_DELAYS;
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uint32_t savePP_OFF_DELAYS;
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uint32_t savePP_DIVISOR;
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uint32_t saveBCLRPAT_A;
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uint32_t saveBCLRPAT_B;
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uint32_t saveDSPALINOFF;
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uint32_t saveDSPBLINOFF;
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uint32_t savePERF_MODE;
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uint32_t saveCHICKENBIT;
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uint32_t saveDSPACURSOR_CTRL;
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uint32_t saveDSPBCURSOR_CTRL;
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uint32_t saveDSPACURSOR_BASE;
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uint32_t saveDSPBCURSOR_BASE;
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uint32_t saveDSPACURSOR_POS;
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uint32_t saveDSPBCURSOR_POS;
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uint32_t save_palette_a[256];
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uint32_t save_palette_b[256];
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uint32_t saveOV_OVADD;
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uint32_t saveOV_OGAMC0;
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uint32_t saveOV_OGAMC1;
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uint32_t saveOV_OGAMC2;
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uint32_t saveOV_OGAMC3;
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uint32_t saveOV_OGAMC4;
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uint32_t saveOV_OGAMC5;
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uint32_t saveOVC_OVADD;
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uint32_t saveOVC_OGAMC0;
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uint32_t saveOVC_OGAMC1;
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uint32_t saveOVC_OGAMC2;
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uint32_t saveOVC_OGAMC3;
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uint32_t saveOVC_OGAMC4;
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uint32_t saveOVC_OGAMC5;
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* extra MDFLD Register state
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uint32_t saveHDMIPHYMISCCTL;
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uint32_t saveHDMIB_CONTROL;
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uint32_t saveDSPCCNTR;
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uint32_t savePIPECCONF;
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uint32_t savePIPECSRC;
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uint32_t saveHTOTAL_C;
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uint32_t saveHBLANK_C;
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uint32_t saveHSYNC_C;
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uint32_t saveVTOTAL_C;
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uint32_t saveVBLANK_C;
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uint32_t saveVSYNC_C;
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uint32_t saveDSPCSTRIDE;
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uint32_t saveDSPCSIZE;
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uint32_t saveDSPCPOS;
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uint32_t saveDSPCSURF;
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uint32_t saveDSPCLINOFF;
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uint32_t saveDSPCTILEOFF;
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uint32_t saveDSPCCURSOR_CTRL;
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uint32_t saveDSPCCURSOR_BASE;
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uint32_t saveDSPCCURSOR_POS;
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uint32_t save_palette_c[256];
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uint32_t saveOV_OVADD_C;
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uint32_t saveOV_OGAMC0_C;
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uint32_t saveOV_OGAMC1_C;
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uint32_t saveOV_OGAMC2_C;
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uint32_t saveOV_OGAMC3_C;
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uint32_t saveOV_OGAMC4_C;
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uint32_t saveOV_OGAMC5_C;
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uint32_t saveDEVICE_READY_REG;
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uint32_t saveINTR_EN_REG;
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uint32_t saveDSI_FUNC_PRG_REG;
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uint32_t saveHS_TX_TIMEOUT_REG;
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uint32_t saveLP_RX_TIMEOUT_REG;
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uint32_t saveTURN_AROUND_TIMEOUT_REG;
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uint32_t saveDEVICE_RESET_REG;
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uint32_t saveDPI_RESOLUTION_REG;
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uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
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uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
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uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
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uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
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uint32_t saveVERT_SYNC_PAD_COUNT_REG;
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uint32_t saveVERT_BACK_PORCH_COUNT_REG;
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uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
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uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
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uint32_t saveINIT_COUNT_REG;
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uint32_t saveMAX_RET_PAK_REG;
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uint32_t saveVIDEO_FMT_REG;
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uint32_t saveEOT_DISABLE_REG;
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uint32_t saveLP_BYTECLK_REG;
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uint32_t saveHS_LS_DBI_ENABLE_REG;
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uint32_t saveTXCLKESC_REG;
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uint32_t saveDPHY_PARAM_REG;
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uint32_t saveMIPI_CONTROL_REG;
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void (*init_drvIC)(struct drm_device *dev);
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void (*dsi_prePowerState)(struct drm_device *dev);
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void (*dsi_postPowerState)(struct drm_device *dev);
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/* DPST Register Save */
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uint32_t saveHISTOGRAM_INT_CONTROL_REG;
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uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
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uint32_t savePWM_CONTROL_LOGIC;
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struct mutex reset_mutex;
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struct mutex cmdbuf_mutex;
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/*uint32_t ta_mem_pages;
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struct psb_ta_mem *ta_mem;
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int force_ta_mem_load;*/
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*TODO: change this to be per drm-context.
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struct psb_context context;
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struct timer_list lid_timer;
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struct psb_intel_opregion opregion;
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* Used for modifying backlight from
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* xrandr -- consider removing and using HAL instead
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struct drm_property *backlight_property;
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struct psb_file_data { /* TODO: Audit this, remove the indirection and set
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it up properly in open/postclose ACFIXME */
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struct ttm_object_file *tfile;
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struct psb_mmu_driver;
730
extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
731
extern int drm_pick_crtcs(struct drm_device *dev);
733
static inline struct psb_fpriv *psb_fpriv(struct drm_file *file_priv)
735
struct psb_file_data *pvr_file_priv
736
= (struct psb_file_data *)file_priv->driver_priv;
737
return (struct psb_fpriv *) pvr_file_priv->priv;
740
static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
742
return (struct drm_psb_private *) dev->dev_private;
746
*TTM glue. psb_ttm_glue.c
749
extern int psb_open(struct inode *inode, struct file *filp);
750
extern int psb_release(struct inode *inode, struct file *filp);
751
extern int psb_mmap(struct file *filp, struct vm_area_struct *vma);
753
extern int psb_fence_signaled_ioctl(struct drm_device *dev, void *data,
754
struct drm_file *file_priv);
755
extern int psb_verify_access(struct ttm_buffer_object *bo,
757
extern ssize_t psb_ttm_read(struct file *filp, char __user *buf,
758
size_t count, loff_t *f_pos);
759
extern ssize_t psb_ttm_write(struct file *filp, const char __user *buf,
760
size_t count, loff_t *f_pos);
761
extern int psb_fence_finish_ioctl(struct drm_device *dev, void *data,
762
struct drm_file *file_priv);
763
extern int psb_fence_unref_ioctl(struct drm_device *dev, void *data,
764
struct drm_file *file_priv);
765
extern int psb_pl_waitidle_ioctl(struct drm_device *dev, void *data,
766
struct drm_file *file_priv);
767
extern int psb_pl_setstatus_ioctl(struct drm_device *dev, void *data,
768
struct drm_file *file_priv);
769
extern int psb_pl_synccpu_ioctl(struct drm_device *dev, void *data,
770
struct drm_file *file_priv);
771
extern int psb_pl_unref_ioctl(struct drm_device *dev, void *data,
772
struct drm_file *file_priv);
773
extern int psb_pl_reference_ioctl(struct drm_device *dev, void *data,
774
struct drm_file *file_priv);
775
extern int psb_pl_create_ioctl(struct drm_device *dev, void *data,
776
struct drm_file *file_priv);
777
extern int psb_pl_ub_create_ioctl(struct drm_device *dev, void *data,
778
struct drm_file *file_priv);
779
extern int psb_extension_ioctl(struct drm_device *dev, void *data,
780
struct drm_file *file_priv);
781
extern int psb_ttm_global_init(struct drm_psb_private *dev_priv);
782
extern void psb_ttm_global_release(struct drm_psb_private *dev_priv);
783
extern int psb_getpageaddrs_ioctl(struct drm_device *dev, void *data,
784
struct drm_file *file_priv);
789
extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
792
struct drm_psb_private *dev_priv);
793
extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
794
extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
796
extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
797
uint32_t gtt_start, uint32_t gtt_pages);
798
extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
801
extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
802
extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
803
extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
804
unsigned long address,
806
extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
808
unsigned long address,
809
uint32_t num_pages, int type);
810
extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
814
*Enable / disable MMU for different requestors.
818
extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
819
extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
820
unsigned long address, uint32_t num_pages,
821
uint32_t desired_tile_stride,
822
uint32_t hw_tile_stride, int type);
823
extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
824
unsigned long address, uint32_t num_pages,
825
uint32_t desired_tile_stride,
826
uint32_t hw_tile_stride);
833
extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
834
struct drm_file *file_priv);
835
extern int psb_reg_submit(struct drm_psb_private *dev_priv,
836
uint32_t *regs, unsigned int cmds);
839
extern void psb_fence_or_sync(struct drm_file *file_priv,
841
uint32_t fence_types,
842
uint32_t fence_flags,
843
struct list_head *list,
844
struct psb_ttm_fence_rep *fence_arg,
845
struct ttm_fence_object **fence_p);
846
extern int psb_validate_kernel_buffer(struct psb_context *context,
847
struct ttm_buffer_object *bo,
848
uint32_t fence_class,
856
extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
857
extern int psb_irq_enable_dpst(struct drm_device *dev);
858
extern int psb_irq_disable_dpst(struct drm_device *dev);
859
extern void psb_irq_preinstall(struct drm_device *dev);
860
extern int psb_irq_postinstall(struct drm_device *dev);
861
extern void psb_irq_uninstall(struct drm_device *dev);
862
extern void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands);
863
extern int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands);
864
extern void psb_irq_turn_on_dpst(struct drm_device *dev);
865
extern void psb_irq_turn_off_dpst(struct drm_device *dev);
867
extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
868
extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence);
869
extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
870
extern int psb_enable_vblank(struct drm_device *dev, int crtc);
871
extern void psb_disable_vblank(struct drm_device *dev, int crtc);
873
psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
876
psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
878
extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
884
extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
886
extern int psb_fence_emit_sequence(struct ttm_fence_device *fdev,
887
uint32_t fence_class,
888
uint32_t flags, uint32_t *sequence,
889
unsigned long *timeout_jiffies);
890
extern void psb_fence_error(struct drm_device *dev,
892
uint32_t sequence, uint32_t type, int error);
893
extern int psb_ttm_fence_device_init(struct ttm_fence_device *fdev);
895
/* MSVDX/Topaz stuff */
896
extern int psb_remove_videoctx(struct drm_psb_private *dev_priv, struct file *filp);
898
extern int lnc_video_frameskip(struct drm_device *dev,
899
uint64_t user_pointer);
900
extern int lnc_video_getparam(struct drm_device *dev, void *data,
901
struct drm_file *file_priv);
906
extern int psb_intel_opregion_init(struct drm_device *dev);
911
extern int psbfb_probed(struct drm_device *dev);
912
extern int psbfb_remove(struct drm_device *dev,
913
struct drm_framebuffer *fb);
914
extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
915
struct drm_file *file_priv);
916
extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
917
struct drm_file *file_priv);
918
extern void *psbfb_vdc_reg(struct drm_device* dev);
923
extern void psbfb_fillrect(struct fb_info *info,
924
const struct fb_fillrect *rect);
925
extern void psbfb_copyarea(struct fb_info *info,
926
const struct fb_copyarea *region);
927
extern void psbfb_imageblit(struct fb_info *info,
928
const struct fb_image *image);
929
extern int psbfb_sync(struct fb_info *info);
931
extern void psb_spank(struct drm_psb_private *dev_priv);
937
extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
938
extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
939
extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
942
extern void psb_modeset_init(struct drm_device *dev);
943
extern void psb_modeset_cleanup(struct drm_device *dev);
944
extern int psb_fbdev_init(struct drm_device * dev);
947
int psb_backlight_init(struct drm_device *dev);
948
void psb_backlight_exit(void);
949
int psb_set_brightness(struct backlight_device *bd);
950
int psb_get_brightness(struct backlight_device *bd);
951
struct backlight_device * psb_get_backlight_device(void);
954
*Debug print bits setting
956
#define PSB_D_GENERAL (1 << 0)
957
#define PSB_D_INIT (1 << 1)
958
#define PSB_D_IRQ (1 << 2)
959
#define PSB_D_ENTRY (1 << 3)
960
/* debug the get H/V BP/FP count */
961
#define PSB_D_HV (1 << 4)
962
#define PSB_D_DBI_BF (1 << 5)
963
#define PSB_D_PM (1 << 6)
964
#define PSB_D_RENDER (1 << 7)
965
#define PSB_D_REG (1 << 8)
966
#define PSB_D_MSVDX (1 << 9)
967
#define PSB_D_TOPAZ (1 << 10)
969
#ifndef DRM_DEBUG_CODE
970
/* To enable debug printout, set drm_psb_debug in psb_drv.c
971
* to any combination of above print flags.
973
/* #define DRM_DEBUG_CODE 2 */
976
extern int drm_psb_debug;
977
extern int drm_psb_no_fb;
978
extern int drm_psb_disable_vsync;
979
extern int drm_idle_check_interval;
981
#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
982
PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
983
#define PSB_DEBUG_INIT(_fmt, _arg...) \
984
PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
985
#define PSB_DEBUG_IRQ(_fmt, _arg...) \
986
PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
987
#define PSB_DEBUG_ENTRY(_fmt, _arg...) \
988
PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg)
989
#define PSB_DEBUG_HV(_fmt, _arg...) \
990
PSB_DEBUG(PSB_D_HV, _fmt, ##_arg)
991
#define PSB_DEBUG_DBI_BF(_fmt, _arg...) \
992
PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg)
993
#define PSB_DEBUG_PM(_fmt, _arg...) \
994
PSB_DEBUG(PSB_D_PM, _fmt, ##_arg)
995
#define PSB_DEBUG_RENDER(_fmt, _arg...) \
996
PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
997
#define PSB_DEBUG_REG(_fmt, _arg...) \
998
PSB_DEBUG(PSB_D_REG, _fmt, ##_arg)
999
#define PSB_DEBUG_MSVDX(_fmt, _arg...) \
1000
PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg)
1001
#define PSB_DEBUG_TOPAZ(_fmt, _arg...) \
1002
PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg)
1005
#define PSB_DEBUG(_flag, _fmt, _arg...) \
1007
if (unlikely((_flag) & drm_psb_debug)) \
1009
"[psb:0x%02x:%s] " _fmt , _flag, \
1010
__func__ , ##_arg); \
1013
#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
1019
#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
1021
static inline u32 MRST_MSG_READ32(uint port, uint offset)
1023
int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
1024
uint32_t ret_val = 0;
1025
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1026
pci_write_config_dword (pci_root, 0xD0, mcr);
1027
pci_read_config_dword (pci_root, 0xD4, &ret_val);
1028
pci_dev_put(pci_root);
1031
static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
1033
int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
1034
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1035
pci_write_config_dword (pci_root, 0xD4, value);
1036
pci_write_config_dword (pci_root, 0xD0, mcr);
1037
pci_dev_put(pci_root);
1039
static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
1041
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
1042
uint32_t ret_val = 0;
1043
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1044
pci_write_config_dword (pci_root, 0xD0, mcr);
1045
pci_read_config_dword (pci_root, 0xD4, &ret_val);
1046
pci_dev_put(pci_root);
1049
static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
1051
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
1052
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1053
pci_write_config_dword (pci_root, 0xD4, value);
1054
pci_write_config_dword (pci_root, 0xD0, mcr);
1055
pci_dev_put(pci_root);
1058
static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
1060
struct drm_psb_private *dev_priv = dev->dev_private;
1061
int reg_val = ioread32(dev_priv->vdc_reg + (reg));
1062
PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg, reg_val);
1066
#define REG_READ(reg) REGISTER_READ(dev, (reg))
1067
static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
1070
struct drm_psb_private *dev_priv = dev->dev_private;
1071
if ((reg < 0x70084 || reg >0x70088) && (reg < 0xa000 || reg >0xa3ff))
1072
PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1074
iowrite32((val), dev_priv->vdc_reg + (reg));
1077
#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
1079
static inline void REGISTER_WRITE16(struct drm_device *dev,
1080
uint32_t reg, uint32_t val)
1082
struct drm_psb_private *dev_priv = dev->dev_private;
1084
PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1086
iowrite16((val), dev_priv->vdc_reg + (reg));
1089
#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
1091
static inline void REGISTER_WRITE8(struct drm_device *dev,
1092
uint32_t reg, uint32_t val)
1094
struct drm_psb_private *dev_priv = dev->dev_private;
1096
PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1098
iowrite8((val), dev_priv->vdc_reg + (reg));
1101
#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
1103
#define PSB_ALIGN_TO(_val, _align) \
1104
(((_val) + ((_align) - 1)) & ~((_align) - 1))
1105
#define PSB_WVDC32(_val, _offs) \
1106
iowrite32(_val, dev_priv->vdc_reg + (_offs))
1107
#define PSB_RVDC32(_offs) \
1108
ioread32(dev_priv->vdc_reg + (_offs))
1110
/* #define TRAP_SGX_PM_FAULT 1 */
1111
#ifdef TRAP_SGX_PM_FAULT
1112
#define PSB_RSGX32(_offs) \
1114
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
1115
printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
1116
__FILE__, __LINE__); \
1119
ioread32(dev_priv->sgx_reg + (_offs)); \
1122
#define PSB_RSGX32(_offs) \
1123
ioread32(dev_priv->sgx_reg + (_offs))
1125
#define PSB_WSGX32(_val, _offs) \
1126
iowrite32(_val, dev_priv->sgx_reg + (_offs))
1128
#define MSVDX_REG_DUMP 0
1131
#define PSB_WMSVDX32(_val, _offs) \
1132
printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\
1133
iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1134
#define PSB_RMSVDX32(_offs) \
1135
ioread32(dev_priv->msvdx_reg + (_offs))
1139
#define PSB_WMSVDX32(_val, _offs) \
1140
iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1141
#define PSB_RMSVDX32(_offs) \
1142
ioread32(dev_priv->msvdx_reg + (_offs))
1146
#define PSB_ALPL(_val, _base) \
1147
(((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
1148
#define PSB_ALPLM(_val, _base) \
1149
((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))