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/* ************************************************************************* */
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/* ************************************************************************* */
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/* |-------------------------------------| |-------------------------------| */
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/* | LF | FV | * | * | S1 | S0 | I1 | I0 | | S | L | E | U | N | Z | V | C | */
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/* |-------------------------------------| |-------------------------------| */
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/* ************************************************************************* */
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static UINT8 LF_bit(dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; }
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static UINT8 FV_bit(dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; }
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//static UINT8 S_bits(dsp56k_core* cpustate); #define s1BIT ((SR & 0x0800) != 0) #define s0BIT ((SR & 0x0400) != 0)
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static UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; }
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static UINT8 S_bit(dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; }
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static UINT8 L_bit(dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; }
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static UINT8 E_bit(dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; }
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static UINT8 U_bit(dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; }
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static UINT8 N_bit(dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; }
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static UINT8 Z_bit(dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; }
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static UINT8 V_bit(dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; }
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static UINT8 C_bit(dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; }
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static void LF_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void FV_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void S_bits_set(dsp56k_core* cpustate, UINT8 value)
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static void I_bits_set(dsp56k_core* cpustate, UINT8 value)
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static void S_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void L_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void E_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void U_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void N_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void Z_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void V_bit_set(dsp56k_core* cpustate, UINT8 value)
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static void C_bit_set(dsp56k_core* cpustate, UINT8 value)
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/* Operating Mode Register */
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// static UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); } // #define mcBIT ((OMR & 0x0004) != 0)
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static UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); } // #define mbBIT ((OMR & 0x0002) != 0)
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static UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); } // #define maBIT ((OMR & 0x0001) != 0)
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// static UINT8 S_bits(dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; }
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static UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; }
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static UINT8 S_bit (dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; }
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static UINT8 L_bit (dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; }
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static UINT8 E_bit (dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; }
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static UINT8 U_bit (dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; }
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static UINT8 N_bit (dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; }
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static UINT8 Z_bit (dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; }
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static UINT8 V_bit (dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; }
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static UINT8 C_bit (dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; }
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static void LF_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); }
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static void FV_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); }
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static void S_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); }
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static void I_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); }
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static void S_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); }
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static void L_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); }
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static void E_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); }
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static void U_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); }
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static void N_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); }
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static void Z_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); }
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static void V_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); }
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static void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); }
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/* ************************************************************************* */
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/* Operating Mode Register */
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/* ************************************************************************* */
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/* |---------------------------------------------------------------------| */
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/* | * | * | * | * | * | * | * | * | CD | SD | R | SA | * | MC | MB | MA | */
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/* |---------------------------------------------------------------------| */
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/* ************************************************************************* */
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// static UINT8 CD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); }
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// static UINT8 SD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); }
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// static UINT8 R_bit(dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); }
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// static UINT8 SA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); }
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// static UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); }
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static UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); }
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static UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); }
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static void CD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
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static void SD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
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static void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
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static void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
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static void SA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
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static void MC_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
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static void MB_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
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static void MA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
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static UINT8 UF_bit(dsp56k_core* cpustate) { return (SP & 0x0020) >> 5; }
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static UINT8 SE_bit(dsp56k_core* cpustate) { return (SP & 0x0010) >> 4; }
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static UINT8 dsp56k_operating_mode(dsp56k_core* cpustate)
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return ((MB_bit(cpustate) << 1) | MA_bit(cpustate));
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/* ************************************************************************* */
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/* ************************************************************************* */
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/* |---------------------------------------------------------------------| */
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/* | * | * | * | * | * | * | * | * | * | * | UF | SE | P3 | P2 | P1 | P0 | */
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/* |---------------------------------------------------------------------| */
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/* ************************************************************************* */
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static UINT8 UF_bit(dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); }
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static UINT8 SE_bit(dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); }
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//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {};
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//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {};
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static UINT8 dsp56k_operating_mode(dsp56k_core* cpustate)
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return ((MB_bit(cpustate) << 1) | MA_bit(cpustate));
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/***************************************************************************
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INITIALIZATION AND RESET
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***************************************************************************/
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static void pcu_init(dsp56k_core* cpustate)
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// Init the irq table