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***************************************************************************/
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/*-------------------------------------------------
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irqn_line_set - set the given IRQ line to the
685
specified state on the active CPU
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-------------------------------------------------*/
688
INLINE void irqn_line_set(const device_config *device, int line, int state)
690
if (interrupt_enable[cpu_get_index(device)])
691
cpu_set_input_line(device, line, state);
695
/*-------------------------------------------------
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705
-------------------------------------------------*/
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INTERRUPT_GEN( nmi_line_pulse ) { irqn_line_set(device, INPUT_LINE_NMI, PULSE_LINE); }
700
INTERRUPT_GEN( nmi_line_assert ) { irqn_line_set(device, INPUT_LINE_NMI, ASSERT_LINE); }
707
INTERRUPT_GEN( nmi_line_pulse ) { if (interrupt_enabled(device)) cpu_set_input_line(device, INPUT_LINE_NMI, PULSE_LINE); }
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INTERRUPT_GEN( nmi_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, INPUT_LINE_NMI, ASSERT_LINE); }
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/*-------------------------------------------------
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-------------------------------------------------*/
707
INTERRUPT_GEN( irq0_line_hold ) { irqn_line_set(device, 0, HOLD_LINE); }
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INTERRUPT_GEN( irq0_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 0); }
709
INTERRUPT_GEN( irq0_line_assert ) { irqn_line_set(device, 0, ASSERT_LINE); }
711
INTERRUPT_GEN( irq1_line_hold ) { irqn_line_set(device, 1, HOLD_LINE); }
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INTERRUPT_GEN( irq1_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 1); }
713
INTERRUPT_GEN( irq1_line_assert ) { irqn_line_set(device, 1, ASSERT_LINE); }
715
INTERRUPT_GEN( irq2_line_hold ) { irqn_line_set(device, 2, HOLD_LINE); }
716
INTERRUPT_GEN( irq2_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 2); }
717
INTERRUPT_GEN( irq2_line_assert ) { irqn_line_set(device, 2, ASSERT_LINE); }
719
INTERRUPT_GEN( irq3_line_hold ) { irqn_line_set(device, 3, HOLD_LINE); }
720
INTERRUPT_GEN( irq3_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 3); }
721
INTERRUPT_GEN( irq3_line_assert ) { irqn_line_set(device, 3, ASSERT_LINE); }
723
INTERRUPT_GEN( irq4_line_hold ) { irqn_line_set(device, 4, HOLD_LINE); }
724
INTERRUPT_GEN( irq4_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 4); }
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INTERRUPT_GEN( irq4_line_assert ) { irqn_line_set(device, 4, ASSERT_LINE); }
727
INTERRUPT_GEN( irq5_line_hold ) { irqn_line_set(device, 5, HOLD_LINE); }
728
INTERRUPT_GEN( irq5_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 5); }
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INTERRUPT_GEN( irq5_line_assert ) { irqn_line_set(device, 5, ASSERT_LINE); }
731
INTERRUPT_GEN( irq6_line_hold ) { irqn_line_set(device, 6, HOLD_LINE); }
732
INTERRUPT_GEN( irq6_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 6); }
733
INTERRUPT_GEN( irq6_line_assert ) { irqn_line_set(device, 6, ASSERT_LINE); }
735
INTERRUPT_GEN( irq7_line_hold ) { irqn_line_set(device, 7, HOLD_LINE); }
736
INTERRUPT_GEN( irq7_line_pulse ) { if (interrupt_enable[cpu_get_index(device)]) generic_pulse_irq_line(device, 7); }
737
INTERRUPT_GEN( irq7_line_assert ) { irqn_line_set(device, 7, ASSERT_LINE); }
715
INTERRUPT_GEN( irq0_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 0, HOLD_LINE); }
716
INTERRUPT_GEN( irq0_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 0); }
717
INTERRUPT_GEN( irq0_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 0, ASSERT_LINE); }
719
INTERRUPT_GEN( irq1_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 1, HOLD_LINE); }
720
INTERRUPT_GEN( irq1_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 1); }
721
INTERRUPT_GEN( irq1_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 1, ASSERT_LINE); }
723
INTERRUPT_GEN( irq2_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 2, HOLD_LINE); }
724
INTERRUPT_GEN( irq2_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 2); }
725
INTERRUPT_GEN( irq2_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 2, ASSERT_LINE); }
727
INTERRUPT_GEN( irq3_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 3, HOLD_LINE); }
728
INTERRUPT_GEN( irq3_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 3); }
729
INTERRUPT_GEN( irq3_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 3, ASSERT_LINE); }
731
INTERRUPT_GEN( irq4_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 4, HOLD_LINE); }
732
INTERRUPT_GEN( irq4_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 4); }
733
INTERRUPT_GEN( irq4_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 4, ASSERT_LINE); }
735
INTERRUPT_GEN( irq5_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 5, HOLD_LINE); }
736
INTERRUPT_GEN( irq5_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 5); }
737
INTERRUPT_GEN( irq5_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 5, ASSERT_LINE); }
739
INTERRUPT_GEN( irq6_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 6, HOLD_LINE); }
740
INTERRUPT_GEN( irq6_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 6); }
741
INTERRUPT_GEN( irq6_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 6, ASSERT_LINE); }
743
INTERRUPT_GEN( irq7_line_hold ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 7, HOLD_LINE); }
744
INTERRUPT_GEN( irq7_line_pulse ) { if (interrupt_enabled(device)) generic_pulse_irq_line(device, 7); }
745
INTERRUPT_GEN( irq7_line_assert ) { if (interrupt_enabled(device)) cpu_set_input_line(device, 7, ASSERT_LINE); }