811
811
case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(ppcdrc); break;
813
813
/* --- the following bits of info are returned as NULL-terminated strings --- */
814
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
814
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
816
816
/* --- everything else is handled generically --- */
817
817
default: ppccom_get_info(ppc, state, info); break;
2107
2107
if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP))
2109
void *base = memory_decrypted_read_ptr(ppc->program, seqhead->physpc);
2109
void *base = memory_decrypted_read_ptr(ppc->program, seqhead->physpc ^ ppc->codexor);
2110
2110
UML_LOAD(block, IREG(0), base, IMM(0), DWORD); // load i0,base,dword
2111
2111
UML_CMP(block, IREG(0), IMM(seqhead->opptr.l[0])); // cmp i0,*opptr
2112
2112
UML_EXHc(block, IF_NE, ppc->impstate->nocode, IMM(seqhead->pc)); // exne nocode,seqhead->pc
2120
2120
for (curdesc = seqhead->next; curdesc != seqlast->next; curdesc = curdesc->next)
2121
2121
if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
2123
void *base = memory_decrypted_read_ptr(ppc->program, seqhead->physpc);
2123
void *base = memory_decrypted_read_ptr(ppc->program, seqhead->physpc ^ ppc->codexor);
2124
2124
UML_LOAD(block, IREG(0), base, IMM(0), DWORD); // load i0,base,dword
2125
2125
UML_CMP(block, IREG(0), IMM(curdesc->opptr.l[0])); // cmp i0,*opptr
2126
2126
UML_EXHc(block, IF_NE, ppc->impstate->nocode, IMM(seqhead->pc)); // exne nocode,seqhead->pc
2129
2129
UINT32 sum = 0;
2130
void *base = memory_decrypted_read_ptr(ppc->program, seqhead->physpc);
2130
void *base = memory_decrypted_read_ptr(ppc->program, seqhead->physpc ^ ppc->codexor);
2131
2131
UML_LOAD(block, IREG(0), base, IMM(0), DWORD); // load i0,base,dword
2132
2132
sum += seqhead->opptr.l[0];
2133
2133
for (curdesc = seqhead->next; curdesc != seqlast->next; curdesc = curdesc->next)
2134
2134
if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
2136
base = memory_decrypted_read_ptr(ppc->program, curdesc->physpc);
2136
base = memory_decrypted_read_ptr(ppc->program, curdesc->physpc ^ ppc->codexor);
2137
2137
UML_LOAD(block, IREG(1), base, IMM(0), DWORD); // load i1,base,dword
2138
2138
UML_ADD(block, IREG(0), IREG(0), IREG(1)); // add i0,i0,i1
2139
2139
sum += curdesc->opptr.l[0];
2334
2334
UML_OR(block, CR32(0), IREG(1), XERSO32); // or [cr0],i1,[xerso]
2337
/*-------------------------------------------------
2338
generate_fp_flags - compute FPSCR floating
2340
-------------------------------------------------*/
2342
static void generate_fp_flags(powerpc_state *ppc, drcuml_block *block, const opcode_desc *desc, int updatefprf)
2344
/* for now, only handle the FPRF field */
2347
UML_MOV(block, MEM(&ppc->param0), IMM(G_RD(desc->opptr.l[0])));
2348
UML_CALLC(block, ppccom_update_fprf, ppc);
2338
2352
/*-------------------------------------------------
2339
2353
generate_branch - generate an unconditional
3505
3519
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3506
3520
UML_CALLH(block, ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align
3507
3521
generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3508
3523
UML_CMP(block, IREG(0), IREG(0)); // cmp i0,i0
3524
UML_GETFLGS(block, IREG(0), DRCUML_FLAG_Z | DRCUML_FLAG_C | DRCUML_FLAG_S); // getflgs i0,zcs
3525
UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), BYTE); // load i0,cmp_cr_table,i0,byte
3526
UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso]
3509
3528
generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags>
3790
3809
return generate_instruction_3f(ppc, block, compiler, desc);
3791
3810
UML_FDADD(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb
3792
3811
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3812
generate_fp_flags(ppc, block, desc, TRUE);
3795
3815
case 0x14: /* FSUBSx */
3797
3817
return generate_instruction_3f(ppc, block, compiler, desc);
3798
3818
UML_FDSUB(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb
3799
3819
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3820
generate_fp_flags(ppc, block, desc, TRUE);
3802
3823
case 0x19: /* FMULSx */
3803
3824
if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES))
3804
3825
return generate_instruction_3f(ppc, block, compiler, desc);
3805
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdmul f0,ra,rb
3826
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3806
3827
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3828
generate_fp_flags(ppc, block, desc, TRUE);
3809
3831
case 0x12: /* FDIVSx */
3811
3833
return generate_instruction_3f(ppc, block, compiler, desc);
3812
3834
UML_FDDIV(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb
3813
3835
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3836
generate_fp_flags(ppc, block, desc, TRUE);
3816
3839
case 0x16: /* FSQRTSx */
3818
3841
return generate_instruction_3f(ppc, block, compiler, desc);
3819
3842
UML_FDSQRT(block, FREG(0), F64(G_RB(op))); // fdsqrt f0,rb
3820
3843
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3844
generate_fp_flags(ppc, block, desc, TRUE);
3823
3847
case 0x18: /* FRESx */
3824
3848
UML_FSFRFLT(block, FREG(0), F64(G_RB(op)), QWORD); // fsfrlt f0,rb,qword
3825
3849
UML_FSRECIP(block, FREG(0), FREG(0)); // fsrecip f0,f0
3826
3850
UML_FDFRFLT(block, F64(G_RD(op)), FREG(0), DWORD); // fdfrflt rd,f0,dword
3851
generate_fp_flags(ppc, block, desc, TRUE);
3829
3854
case 0x1d: /* FMADDSx */
3832
3857
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3833
3858
UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
3834
3859
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3860
generate_fp_flags(ppc, block, desc, TRUE);
3837
3863
case 0x1c: /* FMSUBSx */
3840
3866
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3841
3867
UML_FDSUB(block, FREG(0), FREG(0), F64(G_RB(op))); // fdsub f0,f0,rb
3842
3868
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3869
generate_fp_flags(ppc, block, desc, TRUE);
3845
3872
case 0x1f: /* FNMADDSx */
3849
3876
UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
3850
3877
UML_FDNEG(block, FREG(0), FREG(0)); // fdneg f0,f0
3851
3878
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3879
generate_fp_flags(ppc, block, desc, TRUE);
3854
3882
case 0x1e: /* FNMSUBSx */
3857
3885
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3858
3886
UML_FDSUB(block, FREG(0), F64(G_RB(op)), FREG(0)); // fdsub f0,rb,f0
3859
3887
UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
3888
generate_fp_flags(ppc, block, desc, TRUE);
3883
3912
case 0x15: /* FADDx */
3884
3913
UML_FDADD(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdadd rd,ra,rb
3914
generate_fp_flags(ppc, block, desc, TRUE);
3887
3917
case 0x14: /* FSUBx */
3888
3918
UML_FDSUB(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdsub rd,ra,rb
3919
generate_fp_flags(ppc, block, desc, TRUE);
3891
3922
case 0x19: /* FMULx */
3892
UML_FDMUL(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdmul rd,ra,rb
3923
UML_FDMUL(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_REGC(op))); // fdmul rd,ra,rc
3924
generate_fp_flags(ppc, block, desc, TRUE);
3895
3927
case 0x12: /* FDIVx */
3896
3928
UML_FDDIV(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fddiv rd,ra,rb
3929
generate_fp_flags(ppc, block, desc, TRUE);
3899
3932
case 0x16: /* FSQRTx */
3900
3933
UML_FDSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdsqrt rd,rb
3934
generate_fp_flags(ppc, block, desc, TRUE);
3903
3937
case 0x1a: /* FRSQRTEx */
3904
3938
UML_FDRSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdrsqrt rd,rb
3939
generate_fp_flags(ppc, block, desc, TRUE);
3907
3942
case 0x17: /* FSELx */
3913
3948
case 0x1d: /* FMADDx */
3914
3949
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3915
3950
UML_FDADD(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdadd rd,f0,rb
3951
generate_fp_flags(ppc, block, desc, TRUE);
3918
3954
case 0x1f: /* FNMADDx */
3919
3955
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3920
3956
UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
3921
3957
UML_FDNEG(block, F64(G_RD(op)), FREG(0)); // fdneg rd,f0
3958
generate_fp_flags(ppc, block, desc, TRUE);
3924
3961
case 0x1c: /* FMSUBx */
3925
3962
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3926
3963
UML_FDSUB(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdsub rd,f0,rb
3964
generate_fp_flags(ppc, block, desc, TRUE);
3929
3967
case 0x1e: /* FNMSUBx */
3930
3968
UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
3931
3969
UML_FDSUB(block, F64(G_RD(op)), F64(G_RB(op)), FREG(0)); // fdsub rd,rb,f0
3970
generate_fp_flags(ppc, block, desc, TRUE);
3952
3991
case 0x00c: /* FRSPx */
3953
3992
UML_FDRNDS(block, F64(G_RD(op)), F64(G_RB(op))); // fdrnds rd,rb
3993
generate_fp_flags(ppc, block, desc, TRUE);
3956
3996
case 0x00e: /* FCTIWx */
4300
4340
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(ppcdrc4xx); break;
4302
4342
/* --- the following bits of info are returned as NULL-terminated strings --- */
4303
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 403GA"); break;
4343
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 403GA"); break;
4305
4345
/* --- everything else is handled generically --- */
4306
4346
default: CPU_GET_INFO_CALL(ppcdrc4xx); break;
4335
4375
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(ppcdrc4xx); break;
4337
4377
/* --- the following bits of info are returned as NULL-terminated strings --- */
4338
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 403GCX"); break;
4378
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 403GCX"); break;
4340
4380
/* --- everything else is handled generically --- */
4341
4381
default: CPU_GET_INFO_CALL(ppcdrc4xx); break;
4374
4414
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc601); break;
4376
4416
/* --- the following bits of info are returned as NULL-terminated strings --- */
4377
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 601"); break;
4417
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 601"); break;
4379
4419
/* --- everything else is handled generically --- */
4380
4420
default: CPU_GET_INFO_CALL(ppcdrc); break;
4408
4448
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc602); break;
4410
4450
/* --- the following bits of info are returned as NULL-terminated strings --- */
4411
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 602"); break;
4451
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 602"); break;
4413
4453
/* --- everything else is handled generically --- */
4414
4454
default: CPU_GET_INFO_CALL(ppcdrc); break;
4442
4482
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc603); break;
4444
4484
/* --- the following bits of info are returned as NULL-terminated strings --- */
4445
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 603"); break;
4485
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 603"); break;
4447
4487
/* --- everything else is handled generically --- */
4448
4488
default: CPU_GET_INFO_CALL(ppcdrc); break;
4476
4516
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc603e); break;
4478
4518
/* --- the following bits of info are returned as NULL-terminated strings --- */
4479
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 603e"); break;
4519
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 603e"); break;
4481
4521
/* --- everything else is handled generically --- */
4482
4522
default: CPU_GET_INFO_CALL(ppcdrc); break;
4510
4550
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc603r); break;
4512
4552
/* --- the following bits of info are returned as NULL-terminated strings --- */
4513
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 603R"); break;
4553
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 603R"); break;
4515
4555
/* --- everything else is handled generically --- */
4516
4556
default: CPU_GET_INFO_CALL(ppcdrc); break;
4544
4584
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc604); break;
4546
4586
/* --- the following bits of info are returned as NULL-terminated strings --- */
4547
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 604"); break;
4587
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC 604"); break;
4549
4589
/* --- everything else is handled generically --- */
4550
4590
default: CPU_GET_INFO_CALL(ppcdrc); break;
4583
4623
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(mpc8240); break;
4585
4625
/* --- the following bits of info are returned as NULL-terminated strings --- */
4586
case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC MPC8240"); break;
4626
case DEVINFO_STR_NAME: strcpy(info->s, "PowerPC MPC8240"); break;
4588
4628
/* --- everything else is handled generically --- */
4589
4629
default: CPU_GET_INFO_CALL(ppcdrc); break;
added
removed
src/emu/cpu/powerpc/ppcdrc.c
