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/* tc-crx.c -- Assembler code for the CRX CPU core.
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Copyright 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012
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Free Software Foundation, Inc.
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Contributed by Tomer Levi, NSC, Israel.
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Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
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Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "bfd_stdint.h"
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#include "safe-ctype.h"
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#include "dwarf2dbg.h"
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#include "opcode/crx.h"
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/* Word is considered here as a 16-bit unsigned short int. */
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/* Register is 4-bit size. */
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/* Maximum size of a single instruction (in words). */
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#define INSN_MAX_SIZE 3
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/* Maximum bits which may be set in a `mask16' operand. */
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#define MAX_REGS_IN_MASK16 8
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/* Utility macros for string comparison. */
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#define streq(a, b) (strcmp (a, b) == 0)
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#define strneq(a, b, c) (strncmp (a, b, c) == 0)
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/* Assign a number NUM, shifted by SHIFT bytes, into a location
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pointed by index BYTE of array 'output_opcode'. */
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#define CRX_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT)
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OP_LEGAL = 0, /* Legal operand. */
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OP_OUT_OF_RANGE, /* Operand not within permitted range. */
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OP_NOT_EVEN, /* Operand is Odd number, should be even. */
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OP_ILLEGAL_DISPU4, /* Operand is not within DISPU4 range. */
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OP_ILLEGAL_CST4, /* Operand is not within CST4 range. */
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OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
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(0xFFFF0000-0xFFFFFFFF). */
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/* Opcode mnemonics hash table. */
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static struct hash_control *crx_inst_hash;
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/* CRX registers hash table. */
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static struct hash_control *reg_hash;
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/* CRX coprocessor registers hash table. */
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static struct hash_control *copreg_hash;
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/* Current instruction we're assembling. */
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const inst *instruction;
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/* Global variables. */
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/* Array to hold an instruction encoding. */
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long output_opcode[2];
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/* Nonzero means a relocatable symbol. */
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/* A copy of the original instruction (used in error messages). */
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char ins_parse[MAX_INST_LEN];
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/* The current processed argument number. */
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/* Generic assembler global variables which must be defined by all targets. */
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/* Characters which always start a comment. */
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const char comment_chars[] = "#";
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/* Characters which start a comment at the beginning of a line. */
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const char line_comment_chars[] = "#";
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/* This array holds machine specific line separator characters. */
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const char line_separator_chars[] = ";";
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/* Chars that can be used to separate mant from exp in floating point nums. */
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const char EXP_CHARS[] = "eE";
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/* Chars that mean this number is a floating point constant as in 0f12.456 */
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const char FLT_CHARS[] = "f'";
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/* Target-specific multicharacter options, not const-declared at usage. */
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const char *md_shortopts = "";
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struct option md_longopts[] =
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{NULL, no_argument, NULL, 0}
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size_t md_longopts_size = sizeof (md_longopts);
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/* This table describes all the machine specific pseudo-ops
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the assembler has to support. The fields are:
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*** Pseudo-op name without dot.
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*** Function to call to execute this pseudo-op.
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*** Integer arg to pass to the function. */
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const pseudo_typeS md_pseudo_table[] =
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/* In CRX machine, align is in bytes (not a ptwo boundary). */
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{"align", s_align_bytes, 0},
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/* CRX relaxation table. */
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const relax_typeS md_relax_table[] =
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{0xfa, -0x100, 2, 1}, /* 8 */
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{0xfffe, -0x10000, 4, 2}, /* 16 */
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{0xfffffffe, -0xfffffffe, 6, 0}, /* 32 */
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{0xfffe, -0x10000, 4, 4}, /* 16 */
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{0xfffffffe, -0xfffffffe, 6, 0}, /* 32 */
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{0xfe, -0x100, 4, 6}, /* 8 */
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{0xfffffe, -0x1000000, 6, 0} /* 24 */
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static void reset_vars (char *);
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static reg get_register (char *);
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static copreg get_copregister (char *);
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static argtype get_optype (operand_type);
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static int get_opbits (operand_type);
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static int get_opflags (operand_type);
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static int get_number_of_operands (void);
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static void parse_operand (char *, ins *);
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static int gettrap (const char *);
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static void handle_LoadStor (const char *);
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static int get_cinv_parameters (const char *);
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static long getconstant (long, int);
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static op_err check_range (long *, int, unsigned int, int);
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static int getreg_image (reg);
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static void parse_operands (ins *, char *);
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static void parse_insn (ins *, char *);
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static void print_operand (int, int, argument *);
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static void print_constant (int, int, argument *);
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static int exponent2scale (int);
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static void mask_reg (int, unsigned short *);
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static void process_label_constant (char *, ins *);
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static void set_operand (char *, ins *);
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static char * preprocess_reglist (char *, int *);
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static int assemble_insn (char *, ins *);
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static void print_insn (ins *);
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static void warn_if_needed (ins *);
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static int adjust_if_needed (ins *);
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/* Return the bit size for a given operand. */
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get_opbits (operand_type op)
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return crx_optab[op].bit_size;
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/* Return the argument type of a given operand. */
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get_optype (operand_type op)
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return crx_optab[op].arg_type;
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/* Return the flags of a given operand. */
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get_opflags (operand_type op)
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return crx_optab[op].flags;
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/* Get the core processor register 'reg_name'. */
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get_register (char *reg_name)
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const reg_entry *rreg;
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rreg = (const reg_entry *) hash_find (reg_hash, reg_name);
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return rreg->value.reg_val;
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/* Get the coprocessor register 'copreg_name'. */
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get_copregister (char *copreg_name)
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const reg_entry *coreg;
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coreg = (const reg_entry *) hash_find (copreg_hash, copreg_name);
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return coreg->value.copreg_val;
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return nullcopregister;
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/* Round up a section size to the appropriate boundary. */
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md_section_align (segT seg, valueT val)
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/* Round .text section to a multiple of 2. */
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if (seg == text_section)
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return (val + 1) & ~1;
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/* Parse an operand that is machine-specific (remove '*'). */
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md_operand (expressionS * exp)
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char c = *input_line_pointer;
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input_line_pointer++;
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/* Reset global variables before parsing a new instruction. */
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reset_vars (char *op)
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cur_arg_num = relocatable = 0;
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memset (& output_opcode, '\0', sizeof (output_opcode));
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/* Save a copy of the original OP (used in error messages). */
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strncpy (ins_parse, op, sizeof ins_parse - 1);
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ins_parse [sizeof ins_parse - 1] = 0;
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/* This macro decides whether a particular reloc is an entry in a
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switch table. It is used when relaxing, because the linker needs
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to know about all such entries so that it can adjust them if
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#define SWITCH_TABLE(fix) \
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( (fix)->fx_addsy != NULL \
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&& (fix)->fx_subsy != NULL \
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&& S_GET_SEGMENT ((fix)->fx_addsy) == \
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S_GET_SEGMENT ((fix)->fx_subsy) \
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&& S_GET_SEGMENT (fix->fx_addsy) != undefined_section \
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&& ( (fix)->fx_r_type == BFD_RELOC_CRX_NUM8 \
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|| (fix)->fx_r_type == BFD_RELOC_CRX_NUM16 \
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|| (fix)->fx_r_type == BFD_RELOC_CRX_NUM32))
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/* See whether we need to force a relocation into the output file.
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This is used to force out switch and PC relative relocations when
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crx_force_relocation (fixS *fix)
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if (generic_force_reloc (fix) || SWITCH_TABLE (fix))
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/* Generate a relocation entry for a fixup. */
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tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
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reloc = xmalloc (sizeof (arelent));
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reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
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*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
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reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
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reloc->addend = fixP->fx_offset;
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if (fixP->fx_subsy != NULL)
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if (SWITCH_TABLE (fixP))
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/* Keep the current difference in the addend. */
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reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
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- S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
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switch (fixP->fx_r_type)
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case BFD_RELOC_CRX_NUM8:
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fixP->fx_r_type = BFD_RELOC_CRX_SWITCH8;
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case BFD_RELOC_CRX_NUM16:
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fixP->fx_r_type = BFD_RELOC_CRX_SWITCH16;
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case BFD_RELOC_CRX_NUM32:
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fixP->fx_r_type = BFD_RELOC_CRX_SWITCH32;
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/* We only resolve difference expressions in the same section. */
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as_bad_where (fixP->fx_file, fixP->fx_line,
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_("can't resolve `%s' {%s section} - `%s' {%s section}"),
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fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
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segment_name (fixP->fx_addsy
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? S_GET_SEGMENT (fixP->fx_addsy)
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S_GET_NAME (fixP->fx_subsy),
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segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
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gas_assert ((int) fixP->fx_r_type > 0);
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reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
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if (reloc->howto == (reloc_howto_type *) NULL)
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as_bad_where (fixP->fx_file, fixP->fx_line,
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_("internal error: reloc %d (`%s') not supported by object file format"),
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bfd_get_reloc_code_name (fixP->fx_r_type));
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gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
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/* Prepare machine-dependent frags for relaxation. */
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md_estimate_size_before_relax (fragS *fragp, asection *seg)
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/* If symbol is undefined or located in a different section,
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select the largest supported relocation. */
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relax_substateT subtype;
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relax_substateT rlx_state[] = {0, 2,
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for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
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if (fragp->fr_subtype == rlx_state[subtype]
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&& (!S_IS_DEFINED (fragp->fr_symbol)
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|| seg != S_GET_SEGMENT (fragp->fr_symbol)))
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fragp->fr_subtype = rlx_state[subtype + 1];
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if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
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return md_relax_table[fragp->fr_subtype].rlx_length;
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md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
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/* 'opcode' points to the start of the instruction, whether
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we need to change the instruction's fixed encoding. */
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char *opcode = fragP->fr_literal + fragP->fr_fix;
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bfd_reloc_code_real_type reloc;
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subseg_change (sec, 0);
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switch (fragP->fr_subtype)
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reloc = BFD_RELOC_CRX_REL8;
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reloc = BFD_RELOC_CRX_REL16;
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reloc = BFD_RELOC_CRX_REL32;
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reloc = BFD_RELOC_CRX_REL16;
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reloc = BFD_RELOC_CRX_REL32;
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reloc = BFD_RELOC_CRX_REL8_CMP;
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reloc = BFD_RELOC_CRX_REL24;
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fix_new (fragP, fragP->fr_fix,
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bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
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fragP->fr_symbol, fragP->fr_offset, 1, reloc);
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fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
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/* Process machine-dependent command line options. Called once for
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each option on the command line that the machine-independent part of
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GAS does not understand. */
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md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
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/* Machine-dependent usage-output. */
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md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
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md_atof (int type, char *litP, int *sizeP)
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return ieee_md_atof (type, litP, sizeP, target_big_endian);
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/* Apply a fixS (fixup of an instruction or data that we didn't have
475
enough info to complete immediately) to the data in a frag.
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Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
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relaxation of debug sections, this function is called only when
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fixuping relocations of debug sections. */
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md_apply_fix (fixS *fixP, valueT *valP, segT seg)
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char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
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switch (fixP->fx_r_type)
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case BFD_RELOC_CRX_NUM8:
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bfd_put_8 (stdoutput, (unsigned char) val, buf);
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case BFD_RELOC_CRX_NUM16:
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bfd_put_16 (stdoutput, val, buf);
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case BFD_RELOC_CRX_NUM32:
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bfd_put_32 (stdoutput, val, buf);
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/* We shouldn't ever get here because linkrelax is nonzero. */
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if (fixP->fx_addsy == NULL
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&& fixP->fx_pcrel == 0)
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if (fixP->fx_pcrel == 1
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&& fixP->fx_addsy != NULL
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&& S_GET_SEGMENT (fixP->fx_addsy) == seg)
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/* The location from which a PC relative jump should be calculated,
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given a PC relative reloc. */
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md_pcrel_from (fixS *fixp)
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return fixp->fx_frag->fr_address + fixp->fx_where;
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/* This function is called once, at assembler startup time. This should
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set up all the tables, etc that the MD part of the assembler needs. */
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const char *hashret = NULL;
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/* Set up a hash table for the instructions. */
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if ((crx_inst_hash = hash_new ()) == NULL)
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as_fatal (_("Virtual memory exhausted"));
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while (crx_instruction[i].mnemonic != NULL)
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const char *mnemonic = crx_instruction[i].mnemonic;
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hashret = hash_insert (crx_inst_hash, mnemonic,
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(void *) &crx_instruction[i]);
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if (hashret != NULL && *hashret != '\0')
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as_fatal (_("Can't hash `%s': %s\n"), crx_instruction[i].mnemonic,
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*hashret == 0 ? _("(unknown reason)") : hashret);
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/* Insert unique names into hash table. The CRX instruction set
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has many identical opcode names that have different opcodes based
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on the operands. This hash table then provides a quick index to
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the first opcode with a particular name in the opcode table. */
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while (crx_instruction[i].mnemonic != NULL
558
&& streq (crx_instruction[i].mnemonic, mnemonic));
561
/* Initialize reg_hash hash table. */
562
if ((reg_hash = hash_new ()) == NULL)
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as_fatal (_("Virtual memory exhausted"));
566
const reg_entry *regtab;
568
for (regtab = crx_regtab;
569
regtab < (crx_regtab + NUMREGS); regtab++)
571
hashret = hash_insert (reg_hash, regtab->name, (void *) regtab);
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as_fatal (_("Internal Error: Can't hash %s: %s"),
579
/* Initialize copreg_hash hash table. */
580
if ((copreg_hash = hash_new ()) == NULL)
581
as_fatal (_("Virtual memory exhausted"));
584
const reg_entry *copregtab;
586
for (copregtab = crx_copregtab; copregtab < (crx_copregtab + NUMCOPREGS);
589
hashret = hash_insert (copreg_hash, copregtab->name,
592
as_fatal (_("Internal Error: Can't hash %s: %s"),
597
/* Set linkrelax here to avoid fixups in most sections. */
601
/* Process constants (immediate/absolute)
602
and labels (jump targets/Memory locations). */
605
process_label_constant (char *str, ins * crx_ins)
607
char *saved_input_line_pointer;
608
argument *cur_arg = &crx_ins->arg[cur_arg_num]; /* Current argument. */
610
saved_input_line_pointer = input_line_pointer;
611
input_line_pointer = str;
613
expression (&crx_ins->exp);
615
switch (crx_ins->exp.X_op)
619
/* Missing or bad expr becomes absolute 0. */
620
as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
622
crx_ins->exp.X_op = O_constant;
623
crx_ins->exp.X_add_number = 0;
624
crx_ins->exp.X_add_symbol = (symbolS *) 0;
625
crx_ins->exp.X_op_symbol = (symbolS *) 0;
629
cur_arg->X_op = O_constant;
630
cur_arg->constant = crx_ins->exp.X_add_number;
636
cur_arg->X_op = O_symbol;
637
crx_ins->rtype = BFD_RELOC_NONE;
640
switch (cur_arg->type)
643
if (IS_INSN_TYPE (LD_STOR_INS_INC))
644
crx_ins->rtype = BFD_RELOC_CRX_REGREL12;
645
else if (IS_INSN_TYPE (CSTBIT_INS)
646
|| IS_INSN_TYPE (STOR_IMM_INS))
647
crx_ins->rtype = BFD_RELOC_CRX_REGREL28;
649
crx_ins->rtype = BFD_RELOC_CRX_REGREL32;
653
crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
657
if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
658
crx_ins->rtype = BFD_RELOC_CRX_REL16;
659
else if (IS_INSN_TYPE (BRANCH_INS))
660
crx_ins->rtype = BFD_RELOC_CRX_REL8;
661
else if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (STOR_IMM_INS)
662
|| IS_INSN_TYPE (CSTBIT_INS))
663
crx_ins->rtype = BFD_RELOC_CRX_ABS32;
664
else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
665
crx_ins->rtype = BFD_RELOC_CRX_REL4;
666
else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
667
crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
671
if (IS_INSN_TYPE (ARITH_INS))
672
crx_ins->rtype = BFD_RELOC_CRX_IMM32;
673
else if (IS_INSN_TYPE (ARITH_BYTE_INS))
674
crx_ins->rtype = BFD_RELOC_CRX_IMM16;
682
cur_arg->X_op = crx_ins->exp.X_op;
686
input_line_pointer = saved_input_line_pointer;
690
/* Get the values of the scale to be encoded -
691
used for the scaled index mode of addressing. */
694
exponent2scale (int val)
698
/* If 'val' is 0, the following 'for' will be an endless loop. */
702
for (exponent = 0; (val != 1); val >>= 1, exponent++)
708
/* Parsing different types of operands
709
-> constants Immediate/Absolute/Relative numbers
710
-> Labels Relocatable symbols
711
-> (rbase) Register base
712
-> disp(rbase) Register relative
713
-> disp(rbase)+ Post-increment mode
714
-> disp(rbase,ridx,scl) Register index mode */
717
set_operand (char *operand, ins * crx_ins)
719
char *operandS; /* Pointer to start of sub-opearand. */
720
char *operandE; /* Pointer to end of sub-opearand. */
724
argument *cur_arg = &crx_ins->arg[cur_arg_num]; /* Current argument. */
726
/* Initialize pointers. */
727
operandS = operandE = operand;
729
switch (cur_arg->type)
731
case arg_sc: /* Case *+0x18. */
732
case arg_ic: /* Case $0x18. */
734
case arg_c: /* Case 0x18. */
736
process_label_constant (operandS, crx_ins);
738
if (cur_arg->type != arg_ic)
739
cur_arg->type = arg_c;
742
case arg_icr: /* Case $0x18(r1). */
744
case arg_cr: /* Case 0x18(r1). */
745
/* Set displacement constant. */
746
while (*operandE != '(')
749
process_label_constant (operandS, crx_ins);
751
case arg_rbase: /* Case (r1). */
753
/* Set register base. */
754
while (*operandE != ')')
757
if ((cur_arg->r = get_register (operandS)) == nullregister)
758
as_bad (_("Illegal register `%s' in Instruction `%s'"),
759
operandS, ins_parse);
761
if (cur_arg->type != arg_rbase)
762
cur_arg->type = arg_cr;
766
/* Set displacement constant. */
767
while (*operandE != '(')
770
process_label_constant (operandS, crx_ins);
771
operandS = ++operandE;
773
/* Set register base. */
774
while ((*operandE != ',') && (! ISSPACE (*operandE)))
777
if ((cur_arg->r = get_register (operandS)) == nullregister)
778
as_bad (_("Illegal register `%s' in Instruction `%s'"),
779
operandS, ins_parse);
781
/* Skip leading white space. */
782
while (ISSPACE (*operandE))
786
/* Set register index. */
787
while ((*operandE != ')') && (*operandE != ','))
792
if ((cur_arg->i_r = get_register (operandS)) == nullregister)
793
as_bad (_("Illegal register `%s' in Instruction `%s'"),
794
operandS, ins_parse);
796
/* Skip leading white space. */
797
while (ISSPACE (*operandE))
806
while (*operandE != ')')
810
/* Preprocess the scale string. */
811
input_save = input_line_pointer;
812
input_line_pointer = operandS;
814
input_line_pointer = input_save;
816
scale_val = scale.X_add_number;
818
/* Check if the scale value is legal. */
819
if (scale_val != 1 && scale_val != 2
820
&& scale_val != 4 && scale_val != 8)
821
as_bad (_("Illegal Scale - `%d'"), scale_val);
823
cur_arg->scale = exponent2scale (scale_val);
832
/* Parse a single operand.
833
operand - Current operand to parse.
834
crx_ins - Current assembled instruction. */
837
parse_operand (char *operand, ins * crx_ins)
840
argument *cur_arg = &crx_ins->arg[cur_arg_num]; /* Current argument. */
842
/* Initialize the type to NULL before parsing. */
843
cur_arg->type = nullargs;
845
/* Check whether this is a general processor register. */
846
if ((ret_val = get_register (operand)) != nullregister)
848
cur_arg->type = arg_r;
849
cur_arg->r = ret_val;
850
cur_arg->X_op = O_register;
854
/* Check whether this is a core [special] coprocessor register. */
855
if ((ret_val = get_copregister (operand)) != nullcopregister)
857
cur_arg->type = arg_copr;
859
cur_arg->type = arg_copsr;
860
cur_arg->cr = ret_val;
861
cur_arg->X_op = O_register;
865
/* Deal with special characters. */
869
if (strchr (operand, '(') != NULL)
870
cur_arg->type = arg_icr;
872
cur_arg->type = arg_ic;
877
cur_arg->type = arg_sc;
882
cur_arg->type = arg_rbase;
890
if (strchr (operand, '(') != NULL)
892
if (strchr (operand, ',') != NULL
893
&& (strchr (operand, ',') > strchr (operand, '(')))
894
cur_arg->type = arg_idxr;
896
cur_arg->type = arg_cr;
899
cur_arg->type = arg_c;
902
/* Parse an operand according to its type. */
904
cur_arg->constant = 0;
905
set_operand (operand, crx_ins);
908
/* Parse the various operands. Each operand is then analyzed to fillup
909
the fields in the crx_ins data structure. */
912
parse_operands (ins * crx_ins, char *operands)
914
char *operandS; /* Operands string. */
915
char *operandH, *operandT; /* Single operand head/tail pointers. */
916
int allocated = 0; /* Indicates a new operands string was allocated. */
917
char *operand[MAX_OPERANDS]; /* Separating the operands. */
918
int op_num = 0; /* Current operand number we are parsing. */
919
int bracket_flag = 0; /* Indicates a bracket '(' was found. */
920
int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */
922
/* Preprocess the list of registers, if necessary. */
923
operandS = operandH = operandT = (INST_HAS_REG_LIST) ?
924
preprocess_reglist (operands, &allocated) : operands;
926
while (*operandT != '\0')
928
if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
931
operand[op_num++] = strdup (operandH);
936
if (*operandT == ' ')
937
as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
939
if (*operandT == '(')
941
else if (*operandT == '[')
944
if (*operandT == ')')
949
as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
951
else if (*operandT == ']')
956
as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
959
if (bracket_flag == 1 && *operandT == ')')
961
else if (sq_bracket_flag == 1 && *operandT == ']')
967
/* Adding the last operand. */
968
operand[op_num++] = strdup (operandH);
969
crx_ins->nargs = op_num;
971
/* Verifying correct syntax of operands (all brackets should be closed). */
972
if (bracket_flag || sq_bracket_flag)
973
as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
975
/* Now we parse each operand separately. */
976
for (op_num = 0; op_num < crx_ins->nargs; op_num++)
978
cur_arg_num = op_num;
979
parse_operand (operand[op_num], crx_ins);
980
free (operand[op_num]);
987
/* Get the trap index in dispatch table, given its name.
988
This routine is used by assembling the 'excp' instruction. */
991
gettrap (const char *s)
993
const trap_entry *trap;
995
for (trap = crx_traps; trap < (crx_traps + NUMTRAPS); trap++)
996
if (strcasecmp (trap->name, s) == 0)
999
as_bad (_("Unknown exception: `%s'"), s);
1003
/* Post-Increment instructions, as well as Store-Immediate instructions, are a
1004
sub-group within load/stor instruction groups.
1005
Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
1006
advance the instruction pointer to the start of that sub-group (that is, up
1007
to the first instruction of that type).
1008
Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS. */
1011
handle_LoadStor (const char *operands)
1013
/* Post-Increment instructions precede Store-Immediate instructions in
1014
CRX instruction table, hence they are handled before.
1015
This synchronization should be kept. */
1017
/* Assuming Post-Increment insn has the following format :
1018
'MNEMONIC DISP(REG)+, REG' (e.g. 'loadw 12(r5)+, r6').
1019
LD_STOR_INS_INC are the only store insns containing a plus sign (+). */
1020
if (strstr (operands, ")+") != NULL)
1022
while (! IS_INSN_TYPE (LD_STOR_INS_INC))
1027
/* Assuming Store-Immediate insn has the following format :
1028
'MNEMONIC $DISP, ...' (e.g. 'storb $1, 12(r5)').
1029
STOR_IMM_INS are the only store insns containing a dollar sign ($). */
1030
if (strstr (operands, "$") != NULL)
1031
while (! IS_INSN_TYPE (STOR_IMM_INS))
1035
/* Top level module where instruction parsing starts.
1036
crx_ins - data structure holds some information.
1037
operands - holds the operands part of the whole instruction. */
1040
parse_insn (ins *insn, char *operands)
1044
/* Handle instructions with no operands. */
1045
for (i = 0; no_op_insn[i] != NULL; i++)
1047
if (streq (no_op_insn[i], instruction->mnemonic))
1054
/* Handle 'excp'/'cinv' instructions. */
1055
if (IS_INSN_MNEMONIC ("excp") || IS_INSN_MNEMONIC ("cinv"))
1058
insn->arg[0].type = arg_ic;
1059
insn->arg[0].constant = IS_INSN_MNEMONIC ("excp") ?
1060
gettrap (operands) : get_cinv_parameters (operands);
1061
insn->arg[0].X_op = O_constant;
1065
/* Handle load/stor unique instructions before parsing. */
1066
if (IS_INSN_TYPE (LD_STOR_INS))
1067
handle_LoadStor (operands);
1069
if (operands != NULL)
1070
parse_operands (insn, operands);
1073
/* Cinv instruction requires special handling. */
1076
get_cinv_parameters (const char *operand)
1078
const char *p = operand;
1079
int d_used = 0, i_used = 0, u_used = 0, b_used = 0;
1083
if (*p == ',' || *p == ' ')
1095
as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
1098
return ((b_used ? 8 : 0)
1101
+ (u_used ? 1 : 0));
1104
/* Retrieve the opcode image of a given register.
1105
If the register is illegal for the current instruction,
1109
getreg_image (reg r)
1111
const reg_entry *rreg;
1113
int is_procreg = 0; /* Nonzero means argument should be processor reg. */
1115
if (((IS_INSN_MNEMONIC ("mtpr")) && (cur_arg_num == 1))
1116
|| ((IS_INSN_MNEMONIC ("mfpr")) && (cur_arg_num == 0)) )
1119
/* Check whether the register is in registers table. */
1121
rreg = &crx_regtab[r];
1122
/* Check whether the register is in coprocessor registers table. */
1123
else if (r < (int) MAX_COPREG)
1124
rreg = &crx_copregtab[r-MAX_REG];
1125
/* Register not found. */
1128
as_bad (_("Unknown register: `%d'"), r);
1132
reg_name = rreg->name;
1134
/* Issue a error message when register is illegal. */
1136
as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
1137
reg_name, ins_parse); \
1143
if (is_procreg || (instruction->flags & USER_REG))
1148
case CRX_CFG_REGTYPE:
1161
case CRX_CS_REGTYPE:
1172
/* Routine used to represent integer X using NBITS bits. */
1175
getconstant (long x, int nbits)
1177
return x & ((((1U << (nbits - 1)) - 1) << 1) | 1);
1180
/* Print a constant value to 'output_opcode':
1181
ARG holds the operand's type and value.
1182
SHIFT represents the location of the operand to be print into.
1183
NBITS determines the size (in bits) of the constant. */
1186
print_constant (int nbits, int shift, argument *arg)
1188
unsigned long mask = 0;
1190
long constant = getconstant (arg->constant, nbits);
1198
/* mask the upper part of the constant, that is, the bits
1199
going to the lowest byte of output_opcode[0].
1200
The upper part of output_opcode[1] is always filled,
1201
therefore it is always masked with 0xFFFF. */
1202
mask = (1 << (nbits - 16)) - 1;
1203
/* Divide the constant between two consecutive words :
1205
+---------+---------+---------+---------+
1206
| | X X X X | X X X X | |
1207
+---------+---------+---------+---------+
1208
output_opcode[0] output_opcode[1] */
1210
CRX_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
1211
CRX_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
1216
/* Special case - in arg_cr, the SHIFT represents the location
1217
of the REGISTER, not the constant, which is itself not shifted. */
1218
if (arg->type == arg_cr)
1220
CRX_PRINT (0, constant, 0);
1224
/* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
1225
always filling the upper part of output_opcode[1]. If we mistakenly
1226
write it to output_opcode[0], the constant prefix (that is, 'match')
1229
+---------+---------+---------+---------+
1230
| 'match' | | X X X X | |
1231
+---------+---------+---------+---------+
1232
output_opcode[0] output_opcode[1] */
1234
if ((instruction->size > 2) && (shift == WORD_SHIFT))
1235
CRX_PRINT (1, constant, WORD_SHIFT);
1237
CRX_PRINT (0, constant, shift);
1241
CRX_PRINT (0, constant, shift);
1246
/* Print an operand to 'output_opcode', which later on will be
1247
printed to the object file:
1248
ARG holds the operand's type, size and value.
1249
SHIFT represents the printing location of operand.
1250
NBITS determines the size (in bits) of a constant operand. */
1253
print_operand (int nbits, int shift, argument *arg)
1258
CRX_PRINT (0, getreg_image (arg->r), shift);
1262
if (arg->cr < c0 || arg->cr > c15)
1263
as_bad (_("Illegal Co-processor register in Instruction `%s' "),
1265
CRX_PRINT (0, getreg_image (arg->cr), shift);
1269
if (arg->cr < cs0 || arg->cr > cs15)
1270
as_bad (_("Illegal Co-processor special register in Instruction `%s' "),
1272
CRX_PRINT (0, getreg_image (arg->cr), shift);
1277
+--------------------------------+
1278
| r_base | r_idx | scl| disp |
1279
+--------------------------------+ */
1280
CRX_PRINT (0, getreg_image (arg->r), 12);
1281
CRX_PRINT (0, getreg_image (arg->i_r), 8);
1282
CRX_PRINT (0, arg->scale, 6);
1285
print_constant (nbits, shift, arg);
1289
CRX_PRINT (0, getreg_image (arg->r), shift);
1293
/* case base_cst4. */
1294
if (instruction->flags & DISPU4MAP)
1295
print_constant (nbits, shift + REG_SIZE, arg);
1297
/* rbase_disps<NN> and other such cases. */
1298
print_constant (nbits, shift, arg);
1299
/* Add the register argument to the output_opcode. */
1300
CRX_PRINT (0, getreg_image (arg->r), shift);
1308
/* Retrieve the number of operands for the current assembled instruction. */
1311
get_number_of_operands (void)
1315
for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
1320
/* Verify that the number NUM can be represented in BITS bits (that is,
1321
within its permitted range), based on the instruction's FLAGS.
1322
If UPDATE is nonzero, update the value of NUM if necessary.
1323
Return OP_LEGAL upon success, actual error type upon failure. */
1326
check_range (long *num, int bits, int unsigned flags, int update)
1329
int retval = OP_LEGAL;
1331
uint32_t upper_64kb = 0xffff0000;
1332
uint32_t value = *num;
1334
/* Verify operand value is even. */
1335
if (flags & OP_EVEN)
1341
if (flags & OP_UPPER_64KB)
1343
/* Check if value is to be mapped to upper 64 KB memory area. */
1344
if ((value & upper_64kb) == upper_64kb)
1346
value -= upper_64kb;
1351
return OP_NOT_UPPER_64KB;
1354
if (flags & OP_SHIFT)
1356
/* All OP_SHIFT args are also OP_SIGNED, so we want to keep the
1357
sign. However, right shift of a signed type with a negative
1358
value is implementation defined. See ISO C 6.5.7. So we use
1359
an unsigned type and sign extend afterwards. */
1361
value = (value ^ 0x40000000) - 0x40000000;
1365
else if (flags & OP_SHIFT_DEC)
1367
value = (value >> 1) - 1;
1374
/* 0x7e and 0x7f are reserved escape sequences of dispe9. */
1375
if (value == 0x7e || value == 0x7f)
1376
return OP_OUT_OF_RANGE;
1379
if (flags & OP_DISPU4)
1383
uint32_t mul = (instruction->flags & DISPUB4 ? 1
1384
: instruction->flags & DISPUW4 ? 2
1385
: instruction->flags & DISPUD4 ? 4
1388
for (bin = 0; bin < cst4_maps; bin++)
1390
if (value == mul * bin)
1399
retval = OP_ILLEGAL_DISPU4;
1401
else if (flags & OP_CST4)
1405
for (bin = 0; bin < cst4_maps; bin++)
1407
if (value == (uint32_t) cst4_map[bin])
1416
retval = OP_ILLEGAL_CST4;
1418
else if (flags & OP_SIGNED)
1421
max = max << (bits - 1);
1423
max = ((max - 1) << 1) | 1;
1425
retval = OP_OUT_OF_RANGE;
1427
else if (flags & OP_UNSIGNED)
1430
max = max << (bits - 1);
1431
max = ((max - 1) << 1) | 1;
1433
retval = OP_OUT_OF_RANGE;
1438
/* Assemble a single instruction:
1439
INSN is already parsed (that is, all operand values and types are set).
1440
For instruction to be assembled, we need to find an appropriate template in
1441
the instruction table, meeting the following conditions:
1442
1: Has the same number of operands.
1443
2: Has the same operand types.
1444
3: Each operand size is sufficient to represent the instruction's values.
1445
Returns 1 upon success, 0 upon failure. */
1448
assemble_insn (char *mnemonic, ins *insn)
1450
/* Type of each operand in the current template. */
1451
argtype cur_type[MAX_OPERANDS];
1452
/* Size (in bits) of each operand in the current template. */
1453
unsigned int cur_size[MAX_OPERANDS];
1454
/* Flags of each operand in the current template. */
1455
unsigned int cur_flags[MAX_OPERANDS];
1456
/* Instruction type to match. */
1457
unsigned int ins_type;
1458
/* Boolean flag to mark whether a match was found. */
1461
/* Nonzero if an instruction with same number of operands was found. */
1462
int found_same_number_of_operands = 0;
1463
/* Nonzero if an instruction with same argument types was found. */
1464
int found_same_argument_types = 0;
1465
/* Nonzero if a constant was found within the required range. */
1466
int found_const_within_range = 0;
1467
/* Argument number of an operand with invalid type. */
1468
int invalid_optype = -1;
1469
/* Argument number of an operand with invalid constant value. */
1470
int invalid_const = -1;
1471
/* Operand error (used for issuing various constant error messages). */
1472
op_err op_error, const_err = OP_LEGAL;
1474
/* Retrieve data (based on FUNC) for each operand of a given instruction. */
1475
#define GET_CURRENT_DATA(FUNC, ARRAY) \
1476
for (i = 0; i < insn->nargs; i++) \
1477
ARRAY[i] = FUNC (instruction->operands[i].op_type)
1479
#define GET_CURRENT_TYPE GET_CURRENT_DATA(get_optype, cur_type)
1480
#define GET_CURRENT_SIZE GET_CURRENT_DATA(get_opbits, cur_size)
1481
#define GET_CURRENT_FLAGS GET_CURRENT_DATA(get_opflags, cur_flags)
1483
/* Instruction has no operands -> only copy the constant opcode. */
1484
if (insn->nargs == 0)
1486
output_opcode[0] = BIN (instruction->match, instruction->match_bits);
1490
/* In some case, same mnemonic can appear with different instruction types.
1491
For example, 'storb' is supported with 3 different types :
1492
LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
1493
We assume that when reaching this point, the instruction type was
1494
pre-determined. We need to make sure that the type stays the same
1495
during a search for matching instruction. */
1496
ins_type = CRX_INS_TYPE(instruction->flags);
1498
while (/* Check that match is still not found. */
1500
/* Check we didn't get to end of table. */
1501
&& instruction->mnemonic != NULL
1502
/* Check that the actual mnemonic is still available. */
1503
&& IS_INSN_MNEMONIC (mnemonic)
1504
/* Check that the instruction type wasn't changed. */
1505
&& IS_INSN_TYPE(ins_type))
1507
/* Check whether number of arguments is legal. */
1508
if (get_number_of_operands () != insn->nargs)
1510
found_same_number_of_operands = 1;
1512
/* Initialize arrays with data of each operand in current template. */
1517
/* Check for type compatibility. */
1518
for (i = 0; i < insn->nargs; i++)
1520
if (cur_type[i] != insn->arg[i].type)
1522
if (invalid_optype == -1)
1523
invalid_optype = i + 1;
1527
found_same_argument_types = 1;
1529
for (i = 0; i < insn->nargs; i++)
1531
/* Reverse the operand indices for certain opcodes:
1534
Other index -->> stays the same. */
1535
int j = instruction->flags & REVERSE_MATCH ?
1540
/* Only check range - don't update the constant's value, since the
1541
current instruction may not be the last we try to match.
1542
The constant's value will be updated later, right before printing
1543
it to the object file. */
1544
if ((insn->arg[j].X_op == O_constant)
1545
&& (op_error = check_range (&insn->arg[j].constant, cur_size[j],
1548
if (invalid_const == -1)
1550
invalid_const = j + 1;
1551
const_err = op_error;
1555
/* For symbols, we make sure the relocation size (which was already
1556
determined) is sufficient. */
1557
else if ((insn->arg[j].X_op == O_symbol)
1558
&& ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
1562
found_const_within_range = 1;
1564
/* If we got till here -> Full match is found. */
1568
/* Try again with next instruction. */
1575
/* We haven't found a match - instruction can't be assembled. */
1576
if (!found_same_number_of_operands)
1577
as_bad (_("Incorrect number of operands"));
1578
else if (!found_same_argument_types)
1579
as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
1580
else if (!found_const_within_range)
1584
case OP_OUT_OF_RANGE:
1585
as_bad (_("Operand out of range (arg %d)"), invalid_const);
1588
as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
1590
case OP_ILLEGAL_DISPU4:
1591
as_bad (_("Invalid DISPU4 operand value (arg %d)"), invalid_const);
1593
case OP_ILLEGAL_CST4:
1594
as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const);
1596
case OP_NOT_UPPER_64KB:
1597
as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
1601
as_bad (_("Illegal operand (arg %d)"), invalid_const);
1609
/* Full match - print the encoding to output file. */
1611
/* Make further checkings (such that couldn't be made earlier).
1612
Warn the user if necessary. */
1613
warn_if_needed (insn);
1615
/* Check whether we need to adjust the instruction pointer. */
1616
if (adjust_if_needed (insn))
1617
/* If instruction pointer was adjusted, we need to update
1618
the size of the current template operands. */
1621
for (i = 0; i < insn->nargs; i++)
1623
int j = instruction->flags & REVERSE_MATCH ?
1628
/* This time, update constant value before printing it. */
1629
if ((insn->arg[j].X_op == O_constant)
1630
&& (check_range (&insn->arg[j].constant, cur_size[j],
1631
cur_flags[j], 1) != OP_LEGAL))
1632
as_fatal (_("Illegal operand (arg %d)"), j+1);
1635
/* First, copy the instruction's opcode. */
1636
output_opcode[0] = BIN (instruction->match, instruction->match_bits);
1638
for (i = 0; i < insn->nargs; i++)
1641
print_operand (cur_size[i], instruction->operands[i].shift,
1649
/* Bunch of error checkings.
1650
The checks are made after a matching instruction was found. */
1653
warn_if_needed (ins *insn)
1655
/* If the post-increment address mode is used and the load/store
1656
source register is the same as rbase, the result of the
1657
instruction is undefined. */
1658
if (IS_INSN_TYPE (LD_STOR_INS_INC))
1660
/* Enough to verify that one of the arguments is a simple reg. */
1661
if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
1662
if (insn->arg[0].r == insn->arg[1].r)
1663
as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
1667
/* Some instruction assume the stack pointer as rptr operand.
1668
Issue an error when the register to be loaded is also SP. */
1669
if (instruction->flags & NO_SP)
1671
if (getreg_image (insn->arg[0].r) == getreg_image (sp))
1672
as_bad (_("`%s' has undefined result"), ins_parse);
1675
/* If the rptr register is specified as one of the registers to be loaded,
1676
the final contents of rptr are undefined. Thus, we issue an error. */
1677
if (instruction->flags & NO_RPTR)
1679
if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
1680
as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
1681
getreg_image (insn->arg[0].r));
1685
/* In some cases, we need to adjust the instruction pointer although a
1686
match was already found. Here, we gather all these cases.
1687
Returns 1 if instruction pointer was adjusted, otherwise 0. */
1690
adjust_if_needed (ins *insn)
1694
/* Special check for 'addub $0, r0' instruction -
1695
The opcode '0000 0000 0000 0000' is not allowed. */
1696
if (IS_INSN_MNEMONIC ("addub"))
1698
if ((instruction->operands[0].op_type == cst4)
1699
&& instruction->operands[1].op_type == regr)
1701
if (insn->arg[0].constant == 0 && insn->arg[1].r == r0)
1709
/* Optimization: Omit a zero displacement in bit operations,
1710
saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)'). */
1711
if (IS_INSN_TYPE (CSTBIT_INS))
1713
if ((instruction->operands[1].op_type == rbase_disps12)
1714
&& (insn->arg[1].X_op == O_constant)
1715
&& (insn->arg[1].constant == 0))
1725
/* Set the appropriate bit for register 'r' in 'mask'.
1726
This indicates that this register is loaded or stored by
1730
mask_reg (int r, unsigned short int *mask)
1732
if ((reg)r > (reg)sp)
1734
as_bad (_("Invalid Register in Register List"));
1741
/* Preprocess register list - create a 16-bit mask with one bit for each
1742
of the 16 general purpose registers. If a bit is set, it indicates
1743
that this register is loaded or stored by the instruction. */
1746
preprocess_reglist (char *param, int *allocated)
1748
char reg_name[MAX_REGNAME_LEN]; /* Current parsed register name. */
1749
char *regP; /* Pointer to 'reg_name' string. */
1750
int reg_counter = 0; /* Count number of parsed registers. */
1751
unsigned short int mask = 0; /* Mask for 16 general purpose registers. */
1752
char *new_param; /* New created operands string. */
1753
char *paramP = param; /* Pointer to original opearands string. */
1754
char maskstring[10]; /* Array to print the mask as a string. */
1755
int hi_found = 0, lo_found = 0; /* Boolean flags for hi/lo registers. */
1759
/* If 'param' is already in form of a number, no need to preprocess. */
1760
if (strchr (paramP, '{') == NULL)
1763
/* Verifying correct syntax of operand. */
1764
if (strchr (paramP, '}') == NULL)
1765
as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1767
while (*paramP++ != '{');
1769
new_param = (char *)xcalloc (MAX_INST_LEN, sizeof (char));
1771
strncpy (new_param, param, paramP - param - 1);
1773
while (*paramP != '}')
1776
memset (®_name, '\0', sizeof (reg_name));
1778
while (ISALNUM (*paramP))
1781
strncpy (reg_name, regP, paramP - regP);
1783
/* Coprocessor register c<N>. */
1784
if (IS_INSN_TYPE (COP_REG_INS))
1786
if (((cr = get_copregister (reg_name)) == nullcopregister)
1787
|| (crx_copregtab[cr-MAX_REG].type != CRX_C_REGTYPE))
1788
as_fatal (_("Illegal register `%s' in cop-register list"), reg_name);
1789
mask_reg (getreg_image (cr - c0), &mask);
1791
/* Coprocessor Special register cs<N>. */
1792
else if (IS_INSN_TYPE (COPS_REG_INS))
1794
if (((cr = get_copregister (reg_name)) == nullcopregister)
1795
|| (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
1796
as_fatal (_("Illegal register `%s' in cop-special-register list"),
1798
mask_reg (getreg_image (cr - cs0), &mask);
1800
/* User register u<N>. */
1801
else if (instruction->flags & USER_REG)
1803
if (streq(reg_name, "uhi"))
1808
else if (streq(reg_name, "ulo"))
1813
else if (((r = get_register (reg_name)) == nullregister)
1814
|| (crx_regtab[r].type != CRX_U_REGTYPE))
1815
as_fatal (_("Illegal register `%s' in user register list"), reg_name);
1817
mask_reg (getreg_image (r - u0), &mask);
1819
/* General purpose register r<N>. */
1822
if (streq(reg_name, "hi"))
1827
else if (streq(reg_name, "lo"))
1832
else if (((r = get_register (reg_name)) == nullregister)
1833
|| (crx_regtab[r].type != CRX_R_REGTYPE))
1834
as_fatal (_("Illegal register `%s' in register list"), reg_name);
1836
mask_reg (getreg_image (r - r0), &mask);
1839
if (++reg_counter > MAX_REGS_IN_MASK16)
1840
as_bad (_("Maximum %d bits may be set in `mask16' operand"),
1841
MAX_REGS_IN_MASK16);
1844
while (!ISALNUM (*paramP) && *paramP != '}')
1848
if (*++paramP != '\0')
1849
as_warn (_("rest of line ignored; first ignored character is `%c'"),
1852
switch (hi_found + lo_found)
1855
/* At least one register should be specified. */
1857
as_bad (_("Illegal `mask16' operand, operation is undefined - `%s'"),
1862
/* HI can't be specified without LO (and vise-versa). */
1863
as_bad (_("HI/LO registers should be specified together"));
1867
/* HI/LO registers mustn't be masked with additional registers. */
1869
as_bad (_("HI/LO registers should be specified without additional registers"));
1875
sprintf (maskstring, "$0x%x", mask);
1876
strcat (new_param, maskstring);
1880
/* Print the instruction.
1881
Handle also cases where the instruction is relaxable/relocatable. */
1884
print_insn (ins *insn)
1886
unsigned int i, j, insn_size;
1888
unsigned short words[4];
1891
/* Arrange the insn encodings in a WORD size array. */
1892
for (i = 0, j = 0; i < 2; i++)
1894
words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
1895
words[j++] = output_opcode[i] & 0xFFFF;
1898
/* Handle relaxtion. */
1899
if ((instruction->flags & RELAXABLE) && relocatable)
1903
/* Write the maximal instruction size supported. */
1904
insn_size = INSN_MAX_SIZE;
1907
if (IS_INSN_TYPE (BRANCH_INS))
1910
else if (IS_INSN_TYPE (DCR_BRANCH_INS) || IS_INSN_MNEMONIC ("bal"))
1913
else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
1918
this_frag = frag_var (rs_machine_dependent, insn_size * 2,
1920
insn->exp.X_add_symbol,
1921
insn->exp.X_add_number,
1926
insn_size = instruction->size;
1927
this_frag = frag_more (insn_size * 2);
1929
/* Handle relocation. */
1930
if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
1932
reloc_howto_type *reloc_howto;
1935
reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
1940
size = bfd_get_reloc_size (reloc_howto);
1942
if (size < 1 || size > 4)
1945
fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
1946
size, &insn->exp, reloc_howto->pc_relative,
1951
/* Verify a 2-byte code alignment. */
1952
addr_mod = frag_now_fix () & 1;
1953
if (frag_now->has_code && frag_now->insn_addr != addr_mod)
1954
as_bad (_("instruction address is not a multiple of 2"));
1955
frag_now->insn_addr = addr_mod;
1956
frag_now->has_code = 1;
1958
/* Write the instruction encoding to frag. */
1959
for (i = 0; i < insn_size; i++)
1961
md_number_to_chars (this_frag, (valueT) words[i], 2);
1966
/* This is the guts of the machine-dependent assembler. OP points to a
1967
machine dependent instruction. This function is supposed to emit
1968
the frags/bytes it assembles to. */
1971
md_assemble (char *op)
1977
/* Reset global variables for a new instruction. */
1980
/* Strip the mnemonic. */
1981
for (param = op; *param != 0 && !ISSPACE (*param); param++)
1986
/* Find the instruction. */
1987
instruction = (const inst *) hash_find (crx_inst_hash, op);
1988
if (instruction == NULL)
1990
as_bad (_("Unknown opcode: `%s'"), op);
1995
/* Tie dwarf2 debug info to the address at the start of the insn. */
1996
dwarf2_emit_insn (0);
1998
/* Parse the instruction's operands. */
1999
parse_insn (&crx_ins, param);
2001
/* Assemble the instruction - return upon failure. */
2002
if (assemble_insn (op, &crx_ins) == 0)
2008
/* Print the instruction. */
2010
print_insn (&crx_ins);
added
removed
binutils-2.23.52.20130611/gas/config/tc-crx.c
