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/* tc-i960.c - All the i80960-specific stuff
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Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
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1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009, 2010
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Free Software Foundation, Inc.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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/* See comment on md_parse_option for 80960-specific invocation options. */
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/* There are 4 different lengths of (potentially) symbol-based displacements
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in the 80960 instruction set, each of which could require address fix-ups
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and (in the case of external symbols) emission of relocation directives:
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This is a standard length for the base assembler and requires no
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This is a non-standard length, but the base assembler has a
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hook for bit field address fixups: the fixS structure can
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point to a descriptor of the field, in which case our
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md_number_to_field() routine gets called to process it.
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I made the hook a little cleaner by having fix_new() (in the base
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assembler) return a pointer to the fixS in question. And I made it a
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little simpler by storing the field size (in this case 13) instead of
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of a pointer to another structure: 80960 displacements are ALWAYS
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stored in the low-order bits of a 4-byte word.
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Since the target of a COBR cannot be external, no relocation
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directives for this size displacement have to be generated.
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But the base assembler had to be modified to issue error
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messages if the symbol did turn out to be external.
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Fixups are handled as for the 13-bit case (except that 24 is stored
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The relocation directive generated is the same as that for the 32-bit
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displacement, except that it's PC-relative (the 32-bit displacement
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never is). The i80960 version of the linker needs a mod to
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distinguish and handle the 24-bit case.
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MEMA formats are always promoted to MEMB (32-bit) if the displacement
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is based on a symbol, because it could be relocated at link time.
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The only time we use the 12-bit format is if an absolute value of
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less than 4096 is specified, in which case we need neither a fixup nor
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a relocation directive. */
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#include "safe-ctype.h"
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#include "opcode/i960.h"
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#if defined (OBJ_AOUT) || defined (OBJ_BOUT)
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#define TC_S_IS_SYSPROC(s) ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
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#define TC_S_IS_BALNAME(s) (S_GET_OTHER (s) == N_BALNAME)
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#define TC_S_IS_CALLNAME(s) (S_GET_OTHER (s) == N_CALLNAME)
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#define TC_S_IS_BADPROC(s) ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
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#define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER ((s), (p) + 1))
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#define TC_S_GET_SYSPROC(s) (S_GET_OTHER (s) - 1)
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#define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER ((s), N_BALNAME))
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#define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER ((s), N_CALLNAME))
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#define TC_S_FORCE_TO_SYSPROC(s) {;}
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#else /* ! OBJ_A/BOUT */
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#define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS (s) == C_SCALL)
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#define TC_S_IS_BALNAME(s) (SF_GET_BALNAME (s))
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#define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME (s))
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#define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
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#define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
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#define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
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#define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME (s))
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#define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME (s))
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#define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS ((s), C_SCALL))
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#else /* ! OBJ_COFF */
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#define TC_S_IS_SYSPROC(s) 0
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#define TC_S_IS_BALNAME(s) 0
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#define TC_S_IS_CALLNAME(s) 0
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#define TC_S_IS_BADPROC(s) 0
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#define TC_S_SET_SYSPROC(s, p)
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#define TC_S_GET_SYSPROC(s) 0
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#define TC_S_FORCE_TO_BALNAME(s)
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#define TC_S_FORCE_TO_CALLNAME(s)
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#define TC_S_FORCE_TO_SYSPROC(s)
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#error COFF, a.out, b.out, and ELF are the only supported formats.
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#endif /* ! OBJ_ELF */
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#endif /* ! OBJ_COFF */
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#endif /* ! OBJ_A/BOUT */
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extern char *input_line_pointer;
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/* Local i80960 routines. */
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/* See md_parse_option() for meanings of these options. */
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static char norelax; /* True if -norelax switch seen. */
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static char instrument_branches; /* True if -b switch seen. */
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/* Characters that always start a comment.
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If the pre-processor is disabled, these aren't very useful. */
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const char comment_chars[] = "#";
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/* Characters that only start a comment at the beginning of
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a line. If the line seems to have the form '# 123 filename'
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.line and .file directives will appear in the pre-processed output.
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Note that input_file.c hand checks for '#' at the beginning of the
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first line of the input file. This is because the compiler outputs
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#NO_APP at the beginning of its output. */
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/* Also note that comments started like this one will always work. */
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = ";";
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/* Chars that can be used to separate mant from exp in floating point nums. */
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const char EXP_CHARS[] = "eE";
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/* Chars that mean this number is a floating point constant,
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as in 0f12.456 or 0d1.2345e12. */
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const char FLT_CHARS[] = "fFdDtT";
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/* Table used by base assembler to relax addresses based on varying length
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instructions. The fields are:
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1) most positive reach of this state,
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2) most negative reach of this state,
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3) how many bytes this mode will add to the size of the current frag
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4) which index into the table to try if we can't fit into this one.
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For i80960, the only application is the (de-)optimization of cobr
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instructions into separate compare and branch instructions when a 13-bit
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displacement won't hack it. */
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const relax_typeS md_relax_table[] =
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{0, 0, 0, 0}, /* State 0 => no more relaxation possible. */
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{4088, -4096, 0, 2}, /* State 1: conditional branch (cobr). */
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{0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl). */
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/* These are the machine dependent pseudo-ops.
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This table describes all the machine specific pseudo-ops the assembler
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has to support. The fields are:
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pseudo-op name without dot
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function to call to execute this pseudo-op
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integer arg to pass to the function. */
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/* Macros to extract info from an 'expressionS' structure 'e'. */
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#define adds(e) e.X_add_symbol
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#define offs(e) e.X_add_number
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/* Branch-prediction bits for CTRL/COBR format opcodes. */
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#define BP_MASK 0x00000002 /* Mask for branch-prediction bit. */
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#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch. */
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#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch. */
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/* Some instruction opcodes that we need explicitly. */
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#define BE 0x12000000
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#define BG 0x11000000
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#define BGE 0x13000000
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#define BL 0x14000000
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#define BLE 0x16000000
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#define BNE 0x15000000
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#define BNO 0x10000000
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#define BO 0x17000000
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#define CHKBIT 0x5a002700
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#define CMPI 0x5a002080
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#define CMPO 0x5a002000
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#define BAL 0x0b000000
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#define CALL 0x09000000
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#define CALLS 0x66003800
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#define RET 0x0a000000
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/* These masks are used to build up a set of MEMB mode bits. */
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#define MEMB_BIT 0x1000
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/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
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#define MEMA_ABASE 0x2000
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/* Info from which a MEMA or MEMB format instruction can be generated. */
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/* (First) 32 bits of instruction. */
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/* 0-(none), 12- or, 32-bit displacement needed. */
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/* The expression in the source instruction from which the
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displacement should be determined. */
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/* The two pieces of info we need to generate a register operand. */
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int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg. */
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int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0). */
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int n; /* Register number or literal value. */
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/* Number and assembler mnemonic for all registers that can appear in
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/* Numbers for special-function registers are for assembler internal
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use only: they are scaled back to range [0-31] for binary output. */
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/* Numbers for floating point registers are for assembler internal
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use only: they are scaled back to [0-3] for binary output. */
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{ NULL, 0 }, /* END OF LIST */
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#define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
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#define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
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#define IS_FP_REG(n) ((n) >= FP0)
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/* Number and assembler mnemonic for all registers that can appear as
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'abase' (indirect addressing) registers. */
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/* For assembler internal use only: this number never appears in binary
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{ NULL, 0 }, /* END OF LIST */
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static struct hash_control *op_hash; /* Opcode mnemonics. */
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static struct hash_control *reg_hash; /* Register name hash table. */
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static struct hash_control *areg_hash; /* Abase register hash table. */
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/* Architecture for which we are assembling. */
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#define ARCH_ANY 0 /* Default: no architecture checking done. */
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int architecture = ARCH_ANY; /* Architecture requested on invocation line. */
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int iclasses_seen; /* OR of instruction classes (I_* constants)
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for which we've actually assembled
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/* BRANCH-PREDICTION INSTRUMENTATION
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The following supports generation of branch-prediction instrumentation
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(turned on by -b switch). The instrumentation collects counts
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of branches taken/not-taken for later input to a utility that will
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set the branch prediction bits of the instructions in accordance with
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the behavior observed. (Note that the KX series does not have
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The instrumentation consists of:
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(1) before and after each conditional branch, a call to an external
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routine that increments and steps over an inline counter. The
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counter itself, initialized to 0, immediately follows the call
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instruction. For each branch, the counter following the branch
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is the number of times the branch was not taken, and the difference
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between the counters is the number of times it was taken. An
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example of an instrumented conditional branch:
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(2) a table of pointers to the instrumented branches, so that an
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external postprocessing routine can locate all of the counters.
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the table begins with a 2-word header: a pointer to the next in
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a linked list of such tables (initialized to 0); and a count
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of the number of entries in the table (exclusive of the header.
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Note that input source code is expected to already contain calls
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an external routine that will link the branch local table into a
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list of such tables. */
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/* Number of branches instrumented so far. Also used to generate
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unique local labels for each instrumented branch. */
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#define BR_LABEL_BASE "LBRANCH"
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/* Basename of local labels on instrumented branches, to avoid
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conflict with compiler- generated local labels. */
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#define BR_CNT_FUNC "__inc_branch"
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/* Name of the external routine that will increment (and step over) an
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#define BR_TAB_NAME "__BRANCH_TABLE__"
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/* Name of the table of pointers to branches. A local (i.e.,
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non-external) symbol. */
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static void ctrl_fmt (char *, long, int);
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int i; /* Loop counter. */
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const struct i960_opcode *oP; /* Pointer into opcode table. */
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const char *retval; /* Value returned by hash functions. */
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op_hash = hash_new ();
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reg_hash = hash_new ();
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areg_hash = hash_new ();
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/* For some reason, the base assembler uses an empty string for "no
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error message", instead of a NULL pointer. */
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for (oP = i960_opcodes; oP->name && !retval; oP++)
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retval = hash_insert (op_hash, oP->name, (void *) oP);
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for (i = 0; regnames[i].reg_name && !retval; i++)
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retval = hash_insert (reg_hash, regnames[i].reg_name,
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(char *) ®names[i].reg_num);
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for (i = 0; aregs[i].areg_name && !retval; i++)
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retval = hash_insert (areg_hash, aregs[i].areg_name,
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(char *) &aregs[i].areg_num);
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as_fatal (_("Hashing returned \"%s\"."), retval);
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/* parse_expr: parse an expression
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Use base assembler's expression parser to parse an expression.
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It, unfortunately, runs off a global which we have to save/restore
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in order to make it work for us.
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An empty expression string is treated as an absolute 0.
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Sets O_illegal regardless of expression evaluation if entire input
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string is not consumed in the evaluation -- tolerate no dangling junk! */
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parse_expr (char *textP, /* Text of expression to be parsed. */
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expressionS *expP) /* Where to put the results of parsing. */
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char *save_in; /* Save global here. */
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/* Treat empty string as absolute 0. */
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expP->X_add_symbol = expP->X_op_symbol = NULL;
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expP->X_add_number = 0;
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expP->X_op = O_constant;
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save_in = input_line_pointer; /* Save global. */
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input_line_pointer = textP; /* Make parser work for us. */
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(void) expression (expP);
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if ((size_t) (input_line_pointer - textP) != strlen (textP))
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/* Did not consume all of the input. */
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expP->X_op = O_illegal;
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symP = expP->X_add_symbol;
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if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
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/* Register name in an expression. */
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/* FIXME: this isn't much of a check any more. */
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expP->X_op = O_illegal;
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input_line_pointer = save_in; /* Restore global. */
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/* emit: output instruction binary
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Output instruction binary, in target byte order, 4 bytes at a time.
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Return pointer to where it was placed. */
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emit (long instr) /* Word to be output, host byte order. */
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char *toP; /* Where to output it. */
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toP = frag_more (4); /* Allocate storage. */
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md_number_to_chars (toP, instr, 4); /* Convert to target byte order. */
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/* get_cdisp: handle displacement for a COBR or CTRL instruction.
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Parse displacement for a COBR or CTRL instruction.
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If successful, output the instruction opcode and set up for it,
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depending on the arg 'var_frag', either:
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o an address fixup to be done when all symbol values are known, or
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o a varying length code fragment, with address fixup info. This
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will be done for cobr instructions that may have to be relaxed
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in to compare/branch instructions (8 bytes) if the final
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address displacement is greater than 13 bits. */
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get_cdisp (char *dispP, /* Displacement as specified in source instruction. */
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char *ifmtP, /* "COBR" or "CTRL" (for use in error message). */
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long instr, /* Instruction needing the displacement. */
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int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */
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int var_frag,/* 1 if varying length code fragment should be emitted;
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0 if an address fix should be emitted. */
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int callj) /* 1 if callj relocation should be done; else 0. */
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expressionS e; /* Parsed expression. */
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fixS *fixP; /* Structure describing needed address fix. */
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char *outP; /* Where instruction binary is output to. */
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parse_expr (dispP, &e);
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as_bad (_("expression syntax error"));
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if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
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|| S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
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outP = frag_more (8); /* Allocate worst-case storage. */
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md_number_to_chars (outP, instr, 4);
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frag_variant (rs_machine_dependent, 4, 4, 1,
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adds (e), offs (e), outP);
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/* Set up a new fix structure, so address can be updated
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when all symbol values are known. */
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fixP = fix_new (frag_now,
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outP - frag_now->fr_literal,
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fixP->fx_tcbit = callj;
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/* We want to modify a bit field when the address is
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known. But we don't need all the garbage in the
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bit_fix structure. So we're going to lie and store
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the number of bits affected instead of a pointer. */
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fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
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as_bad (_("attempt to branch into different segment"));
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as_bad (_("target of %s instruction must be a label"), ifmtP);
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md_chars_to_number (char * val, /* Value in target byte order. */
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int n) /* Number of bytes in the input. */
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for (retval = 0; n--;)
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retval |= (unsigned char) val[n];
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/* mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
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There are 2 possible MEMA formats:
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- displacement + abase
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They are distinguished by the setting of the MEMA_ABASE bit. */
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mema_to_memb (char * opcodeP) /* Where to find the opcode, in target byte order. */
652
long opcode; /* Opcode in host byte order. */
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long mode; /* Mode bits for MEMB instruction. */
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opcode = md_chars_to_number (opcodeP, 4);
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know (!(opcode & MEMB_BIT));
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mode = MEMB_BIT | D_BIT;
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if (opcode & MEMA_ABASE)
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opcode &= 0xffffc000; /* Clear MEMA offset and mode bits. */
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opcode |= mode; /* Set MEMB mode bits. */
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md_number_to_chars (opcodeP, opcode, 4);
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Return TRUE iff the target architecture supports the specified
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special-function register (sfr). */
674
targ_has_sfr (int n) /* Number (0-31) of sfr. */
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switch (architecture)
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return ((0 <= n) && (n <= 4));
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return ((0 <= n) && (n <= 2));
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/* Look up a (suspected) register name in the register table and return the
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associated register number (or -1 if not found). */
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get_regnum (char *regname) /* Suspected register name. */
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rP = (int *) hash_find (reg_hash, regname);
700
return (rP == NULL) ? -1 : *rP;
703
/* syntax: Issue a syntax error. */
708
as_bad (_("syntax error"));
711
/* parse_regop: parse a register operand.
713
In case of illegal operand, issue a message and return some valid
714
information so instruction processing can continue. */
717
parse_regop (struct regop *regopP, /* Where to put description of register operand. */
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char *optext, /* Text of operand. */
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char opdesc) /* Descriptor byte: what's legal for this operand. */
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int n; /* Register number. */
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expressionS e; /* Parsed expression. */
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/* See if operand is a register. */
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n = get_regnum (optext);
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/* Global or local register. */
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if (!REG_ALIGN (opdesc, n))
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as_bad (_("unaligned register"));
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else if (IS_FP_REG (n) && FP_OK (opdesc))
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/* Floating point register, and it's allowed. */
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else if (IS_SF_REG (n) && SFR_OK (opdesc))
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/* Special-function register, and it's allowed. */
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if (!targ_has_sfr (regopP->n))
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as_bad (_("no such sfr in this architecture"));
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else if (LIT_OK (opdesc))
761
/* How about a literal? */
766
/* Floating point literal acceptable. */
767
/* Skip over 0f, 0d, or 0e prefix. */
768
if ((optext[0] == '0')
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&& (optext[1] >= 'd')
770
&& (optext[1] <= 'f'))
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if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
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if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
787
/* Fixed point literal acceptable. */
788
parse_expr (optext, &e);
789
if (e.X_op != O_constant
790
|| (offs (e) < 0) || (offs (e) > 31))
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as_bad (_("illegal literal"));
795
regopP->n = offs (e);
800
/* Nothing worked. */
802
regopP->mode = 0; /* Register r0 is always a good one. */
807
/* get_ispec: parse a memory operand for an index specification
809
Here, an "index specification" is taken to be anything surrounded
810
by square brackets and NOT followed by anything else.
812
If it's found, detach it from the input string, remove the surrounding
813
square brackets, and return a pointer to it. Otherwise, return NULL. */
816
get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */
819
/* Points to start of index specification. */
821
/* Points to end of index specification. */
824
/* Find opening square bracket, if any. */
825
start = strchr (textP, '[');
829
/* Eliminate '[', detach from rest of operand. */
832
end = strchr (start, ']');
835
as_bad (_("unmatched '['"));
838
/* Eliminate ']' and make sure it was the last thing
841
if (*(end + 1) != '\0')
842
as_bad (_("garbage after index spec ignored"));
848
/* parse_memop: parse a memory operand
850
This routine is based on the observation that the 4 mode bits of the
851
MEMB format, taken individually, have fairly consistent meaning:
853
M3 (bit 13): 1 if displacement is present (D_BIT)
854
M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
855
M1 (bit 11): 1 if index is present (I_BIT)
856
M0 (bit 10): 1 if abase is present (A_BIT)
858
So we parse the memory operand and set bits in the mode as we find
859
things. Then at the end, if we go to MEMB format, we need only set
860
the MEMB bit (M2) and our mode is built for us.
862
Unfortunately, I said "fairly consistent". The exceptions:
865
0100 Would seem illegal, but means "abase-only".
867
0101 Would seem to mean "abase-only" -- it means IP-relative.
868
Must be converted to 0100.
870
0110 Would seem to mean "index-only", but is reserved.
871
We turn on the D bit and provide a 0 displacement.
873
The other thing to observe is that we parse from the right, peeling
874
things * off as we go: first any index spec, then any abase, then
878
parse_memop (memS *memP, /* Where to put the results. */
879
char *argP, /* Text of the operand to be parsed. */
880
int optype) /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16. */
882
char *indexP; /* Pointer to index specification with "[]" removed. */
883
char *p; /* Temp char pointer. */
884
char iprel_flag; /* True if this is an IP-relative operand. */
885
int regnum; /* Register number. */
886
/* Scale factor: 1,2,4,8, or 16. Later converted to internal format
887
(0,1,2,3,4 respectively). */
889
int mode; /* MEMB mode bits. */
890
int *intP; /* Pointer to register number. */
892
/* The following table contains the default scale factors for each
893
type of memory instruction. It is accessed using (optype-MEM1)
894
as an index -- thus it assumes the 'optype' constants are
895
assigned consecutive values, in the order they appear in this
897
static const int def_scale[] =
903
-1, /* MEM12 -- no valid default */
907
iprel_flag = mode = 0;
909
/* Any index present? */
910
indexP = get_ispec (argP);
913
p = strchr (indexP, '*');
916
/* No explicit scale -- use default for this instruction
917
type and assembler mode. */
921
/* GNU960 compatibility */
922
scale = def_scale[optype - MEM1];
926
*p++ = '\0'; /* Eliminate '*' */
928
/* Now indexP->a '\0'-terminated register name,
929
and p->a scale factor. */
931
if (!strcmp (p, "16"))
933
else if (strchr ("1248", *p) && (p[1] == '\0'))
939
regnum = get_regnum (indexP); /* Get index reg. # */
940
if (!IS_RG_REG (regnum))
942
as_bad (_("invalid index register"));
946
/* Convert scale to its binary encoding. */
965
as_bad (_("invalid scale factor"));
969
memP->opcode |= scale | regnum; /* Set index bits in opcode. */
970
mode |= I_BIT; /* Found a valid index spec. */
973
/* Any abase (Register Indirect) specification present? */
974
if ((p = strrchr (argP, '(')) != NULL)
976
/* "(" is there -- does it start a legal abase spec? If not, it
977
could be part of a displacement expression. */
978
intP = (int *) hash_find (areg_hash, p);
981
/* Got an abase here. */
983
*p = '\0'; /* Discard register spec. */
985
/* We have to specialcase ip-rel mode. */
989
memP->opcode |= regnum << 14;
995
/* Any expression present? */
1000
/* Special-case ip-relative addressing. */
1007
memP->opcode |= 5 << 10; /* IP-relative mode. */
1013
/* Handle all other modes. */
1017
/* Go with MEMA instruction format for now (grow to MEMB later
1018
if 12 bits is not enough for the displacement). MEMA format
1019
has a single mode bit: set it to indicate that abase is
1021
memP->opcode |= MEMA_ABASE;
1026
/* Go with MEMA instruction format for now (grow to MEMB later
1027
if 12 bits is not enough for the displacement). */
1032
/* For some reason, the bit string for this mode is not
1033
consistent: it should be 0 (exclusive of the MEMB bit), so we
1034
set it "by hand" here. */
1035
memP->opcode |= MEMB_BIT;
1039
/* set MEMB bit in mode, and OR in mode bits. */
1040
memP->opcode |= mode | MEMB_BIT;
1044
/* Treat missing displacement as displacement of 0. */
1046
/* Fall into next case. */
1047
case D_BIT | A_BIT | I_BIT:
1049
/* Set MEMB bit in mode, and OR in mode bits. */
1050
memP->opcode |= mode | MEMB_BIT;
1060
/* Generate a MEMA- or MEMB-format instruction. */
1063
mem_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */
1064
struct i960_opcode *oP,/* Pointer to description of instruction. */
1065
int callx) /* Is this a callx opcode. */
1067
int i; /* Loop counter. */
1068
struct regop regop; /* Description of register operand. */
1069
char opdesc; /* Operand descriptor byte. */
1070
memS instr; /* Description of binary to be output. */
1071
char *outP; /* Where the binary was output to. */
1072
expressionS exp; /* Parsed expression. */
1073
/* ->description of deferred address fixup. */
1077
/* COFF support isn't in place yet for callx relaxing. */
1081
memset (&instr, '\0', sizeof (memS));
1082
instr.opcode = oP->opcode;
1084
/* Process operands. */
1085
for (i = 1; i <= oP->num_ops; i++)
1087
opdesc = oP->operand[i - 1];
1090
parse_memop (&instr, args[i], oP->format);
1093
parse_regop (®op, args[i], opdesc);
1094
instr.opcode |= regop.n << 19;
1098
/* Parse the displacement; this must be done before emitting the
1099
opcode, in case it is an expression using `.'. */
1100
parse_expr (instr.e, &exp);
1102
/* Output opcode. */
1103
outP = emit (instr.opcode);
1105
if (instr.disp == 0)
1108
/* Process the displacement. */
1112
as_bad (_("expression syntax error"));
1116
if (instr.disp == 32)
1117
(void) emit (offs (exp)); /* Output displacement. */
1120
/* 12-bit displacement. */
1121
if (offs (exp) & ~0xfff)
1123
/* Won't fit in 12 bits: convert already-output
1124
instruction to MEMB format, output
1126
mema_to_memb (outP);
1127
(void) emit (offs (exp));
1131
/* WILL fit in 12 bits: OR into opcode and
1132
overwrite the binary we already put out. */
1133
instr.opcode |= offs (exp);
1134
md_number_to_chars (outP, instr.opcode, 4);
1140
if (instr.disp == 12)
1141
/* Displacement is dependent on a symbol, whose value
1142
may change at link time. We HAVE to reserve 32 bits.
1143
Convert already-output opcode to MEMB format. */
1144
mema_to_memb (outP);
1146
/* Output 0 displacement and set up address fixup for when
1147
this symbol's value becomes known. */
1148
outP = emit ((long) 0);
1149
fixP = fix_new_exp (frag_now,
1150
outP - frag_now->fr_literal,
1151
4, &exp, 0, NO_RELOC);
1152
/* Steve's linker relaxing hack. Mark this 32-bit relocation as
1153
being in the instruction stream, specifically as part of a callx
1155
fixP->fx_bsr = callx;
1162
Return TRUE iff the target architecture supports the indicated
1163
class of instructions. */
1166
targ_has_iclass (int ic) /* Instruction class; one of:
1167
I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2. */
1169
iclasses_seen |= ic;
1171
switch (architecture)
1174
return ic & (I_BASE | I_KX);
1176
return ic & (I_BASE | I_KX | I_FP | I_DEC);
1178
return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
1180
return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
1182
return ic & (I_BASE | I_CX2 | I_JX);
1184
return ic & (I_BASE | I_CX2 | I_JX | I_HX);
1186
if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
1187
&& (iclasses_seen & (I_CX | I_CX2)))
1189
as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
1190
iclasses_seen &= ~ic;
1197
Determine if a "shlo" instruction can be used to implement a "ldconst".
1198
This means that some number X < 32 can be shifted left to produce the
1199
constant of interest.
1201
Return the shift count, or 0 if we can't do it.
1202
Caller calculates X by shifting original constant right 'shift' places. */
1205
shift_ok (int n) /* The constant of interest. */
1207
int shift; /* The shift count. */
1210
/* Can't do it for negative numbers. */
1213
/* Shift 'n' right until a 1 is about to be lost. */
1214
for (shift = 0; (n & 1) == 0; shift++)
1224
Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1227
Assumes the input consists of:
1228
arg[0] opcode mnemonic ('ldconst')
1229
arg[1] first operand (constant)
1230
arg[2] name of register to be loaded
1232
Replaces opcode and/or operands as appropriate.
1234
Returns the new number of arguments, or -1 on failure. */
1237
parse_ldconst (char *arg[]) /* See above. */
1239
int n; /* Constant to be loaded. */
1240
int shift; /* Shift count for "shlo" instruction. */
1241
static char buf[5]; /* Literal for first operand. */
1242
static char buf2[5]; /* Literal for second operand. */
1243
expressionS e; /* Parsed expression. */
1245
arg[3] = NULL; /* So we can tell at the end if it got used or not. */
1247
parse_expr (arg[1], &e);
1251
/* We're dependent on one or more symbols -- use "lda". */
1256
/* Try the following mappings:
1257
ldconst 0,<reg> -> mov 0,<reg>
1258
ldconst 31,<reg> -> mov 31,<reg>
1259
ldconst 32,<reg> -> addo 1,31,<reg>
1260
ldconst 62,<reg> -> addo 31,31,<reg>
1261
ldconst 64,<reg> -> shlo 8,3,<reg>
1262
ldconst -1,<reg> -> subo 1,0,<reg>
1263
ldconst -31,<reg> -> subo 31,0,<reg>
1265
Anything else becomes:
1268
if ((0 <= n) && (n <= 31))
1270
else if ((-31 <= n) && (n <= -1))
1274
sprintf (buf, "%d", -n);
1278
else if ((32 <= n) && (n <= 62))
1283
sprintf (buf, "%d", n - 31);
1286
else if ((shift = shift_ok (n)) != 0)
1290
sprintf (buf, "%d", shift);
1292
sprintf (buf2, "%d", n >> shift);
1300
as_bad (_("invalid constant"));
1304
return (arg[3] == 0) ? 2 : 3;
1307
/* reg_fmt: generate a REG-format instruction. */
1310
reg_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */
1311
struct i960_opcode *oP)/* Pointer to description of instruction. */
1313
long instr; /* Binary to be output. */
1314
struct regop regop; /* Description of register operand. */
1315
int n_ops; /* Number of operands. */
1318
n_ops = oP->num_ops;
1322
parse_regop (®op, args[1], oP->operand[0]);
1324
if ((n_ops == 1) && !(instr & M3))
1326
/* 1-operand instruction in which the dst field should
1327
be used (instead of src1). */
1330
regop.mode = regop.special;
1336
/* regop.n goes in bit 0, needs no shifting. */
1338
regop.special <<= 5;
1340
instr |= regop.n | regop.mode | regop.special;
1345
parse_regop (®op, args[2], oP->operand[1]);
1347
if ((n_ops == 2) && !(instr & M3))
1349
/* 2-operand instruction in which the dst field should
1350
be used instead of src2). */
1353
regop.mode = regop.special;
1361
regop.special <<= 6;
1363
instr |= regop.n | regop.mode | regop.special;
1367
parse_regop (®op, args[3], oP->operand[2]);
1369
regop.mode = regop.special;
1370
instr |= (regop.n <<= 19) | (regop.mode <<= 13);
1375
/* get_args: break individual arguments out of comma-separated list
1378
- all comments and labels have been removed
1379
- all strings of whitespace have been collapsed to a single blank.
1380
- all character constants ('x') have been replaced with decimal
1383
args[0] is untouched. args[1] points to first operand, etc. All args:
1384
- are NULL-terminated
1385
- contain no whitespace
1388
Number of operands (0,1,2, or 3) or -1 on error. */
1391
get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */
1392
char *args[]) /* Output arg: pointers to operands placed in args[1-3].
1393
Must accommodate 4 entries (args[0-3]). */
1396
int n; /* Number of operands. */
1399
/* Skip lead white space. */
1409
/* Squeze blanks out by moving non-blanks toward start of string.
1410
Isolate operands, whenever comma is found. */
1415
&& (! ISALNUM (p[1])
1416
|| ! ISALNUM (p[-1])))
1420
/* Start of operand. */
1423
as_bad (_("too many operands"));
1426
*to++ = '\0'; /* Terminate argument. */
1427
args[++n] = to; /* Start next argument. */
1437
/* i_scan: perform lexical scan of ascii assembler instruction.
1440
- input string is an i80960 instruction (not a pseudo-op)
1441
- all comments and labels have been removed
1442
- all strings of whitespace have been collapsed to a single blank.
1445
args[0] points to opcode, other entries point to operands. All strings:
1446
- are NULL-terminated
1447
- contain no whitespace
1448
- have character constants ('x') replaced with a decimal number
1451
Number of operands (0,1,2, or 3) or -1 on error. */
1454
i_scan (char *iP, /* Pointer to ascii instruction; Mucked by us. */
1455
char *args[]) /* Output arg: pointers to opcode and operands placed here.
1456
Must accommodate 4 entries. */
1458
/* Isolate opcode. */
1463
for (; *iP != ' '; iP++)
1467
/* There are no operands. */
1470
/* We never moved: there was no opcode either! */
1471
as_bad (_("missing opcode"));
1478
return (get_args (iP, args));
1484
/* Emit call to "increment" routine. */
1485
ctrl_fmt (BR_CNT_FUNC, CALL, 1);
1486
/* Emit inline counter to be incremented. */
1493
static char buf[20];
1495
sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1500
ctrl_fmt (char *targP, /* Pointer to text of lone operand (if any). */
1501
long opcode, /* Template of instruction. */
1502
int num_ops) /* Number of operands. */
1504
int instrument; /* TRUE iff we should add instrumentation to track
1505
how often the branch is taken. */
1508
emit (opcode); /* Output opcode. */
1511
instrument = instrument_branches && (opcode != CALL)
1512
&& (opcode != B) && (opcode != RET) && (opcode != BAL);
1517
colon (brlab_next ());
1520
/* The operand MUST be an ip-relative displacement. Parse it
1521
and set up address fix for the instruction we just output. */
1522
get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1530
cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1532
/* Opcode, with branch-prediction bits already set if necessary. */
1534
/* Pointer to description of instruction. */
1535
struct i960_opcode *oP)
1537
long instr; /* 32-bit instruction. */
1538
struct regop regop; /* Description of register operand. */
1539
int n; /* Number of operands. */
1540
int var_frag; /* 1 if varying length code fragment should
1541
be emitted; 0 if an address fix
1542
should be emitted. */
1549
/* First operand (if any) of a COBR is always a register
1550
operand. Parse it. */
1551
parse_regop (®op, arg[1], oP->operand[0]);
1552
instr |= (regop.n << 19) | (regop.mode << 13);
1557
/* Second operand (if any) of a COBR is always a register
1558
operand. Parse it. */
1559
parse_regop (®op, arg[2], oP->operand[1]);
1560
instr |= (regop.n << 14) | regop.special;
1567
if (instrument_branches)
1570
colon (brlab_next ());
1573
/* A third operand to a COBR is always a displacement. Parse
1574
it; if it's relaxable (a cobr "j" directive, or any cobr
1575
other than bbs/bbc when the "-norelax" option is not in use)
1576
set up a variable code fragment; otherwise set up an address
1578
var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1579
get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1581
if (instrument_branches)
1586
/* Assumptions about the passed-in text:
1587
- all comments, labels removed
1588
- text is an instruction
1589
- all white space compressed to single blanks
1590
- all character constants have been replaced with decimal. */
1593
md_assemble (char *textP)
1595
/* Parsed instruction text, containing NO whitespace: arg[0]->opcode
1596
mnemonic arg[1-3]->operands, with char constants replaced by
1599
/* Number of instruction operands. */
1601
/* Pointer to instruction description. */
1602
struct i960_opcode *oP;
1603
/* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
1606
/* Setting of branch-prediction bit(s) to be OR'd into instruction
1607
opcode of CTRL/COBR format instructions. */
1609
/* Offset of last character in opcode mnemonic. */
1611
const char *bp_error_msg = _("branch prediction invalid on this opcode");
1613
/* Parse instruction into opcode and operands. */
1614
memset (args, '\0', sizeof (args));
1616
n_ops = i_scan (textP, args);
1619
return; /* Error message already issued. */
1621
/* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction. */
1622
if (!strcmp (args[0], "ldconst"))
1624
n_ops = parse_ldconst (args);
1629
/* Check for branch-prediction suffix on opcode mnemonic, strip it off. */
1630
n = strlen (args[0]) - 1;
1634
if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
1636
/* We could check here to see if the target architecture
1637
supports branch prediction, but why bother? The bit will
1638
just be ignored by processors that don't use it. */
1640
bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
1641
args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
1644
/* Look up opcode mnemonic in table and check number of operands.
1645
Check that opcode is legal for the target architecture. If all
1646
looks good, assemble instruction. */
1647
oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
1648
if (!oP || !targ_has_iclass (oP->iclass))
1649
as_bad (_("invalid opcode, \"%s\"."), args[0]);
1650
else if (n_ops != oP->num_ops)
1651
as_bad (_("improper number of operands. expecting %d, got %d"),
1652
oP->num_ops, n_ops);
1659
ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
1660
if (oP->format == FBRA)
1661
/* Now generate a 'bno' to same arg */
1662
ctrl_fmt (args[1], BNO | bp_bits, 1);
1666
cobr_fmt (args, oP->opcode | bp_bits, oP);
1670
as_warn ("%s", bp_error_msg);
1674
if (args[0][0] == 'c' && args[0][1] == 'a')
1677
as_warn ("%s", bp_error_msg);
1678
mem_fmt (args, oP, 1);
1687
as_warn ("%s", bp_error_msg);
1688
mem_fmt (args, oP, 0);
1692
as_warn ("%s", bp_error_msg);
1693
/* Output opcode & set up "fixup" (relocation); flag
1694
relocation as 'callj' type. */
1695
know (oP->num_ops == 1);
1696
get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
1699
BAD_CASE (oP->format);
1706
md_number_to_chars (char *buf,
1710
number_to_chars_littleendian (buf, value, n);
1714
md_atof (int type, char *litP, int *sizeP)
1716
return ieee_md_atof (type, litP, sizeP, FALSE);
1720
md_number_to_imm (char *buf, long val, int n)
1722
md_number_to_chars (buf, val, n);
1726
md_number_to_field (char *instrP, /* Pointer to instruction to be fixed. */
1727
long val, /* Address fixup value. */
1728
bit_fixS *bfixP) /* Description of bit field to be fixed up. */
1730
int numbits; /* Length of bit field to be fixed. */
1731
long instr; /* 32-bit instruction to be fixed-up. */
1732
long sign; /* 0 or -1, according to sign bit of 'val'. */
1734
/* Convert instruction back to host byte order. */
1735
instr = md_chars_to_number (instrP, 4);
1737
/* Surprise! -- we stored the number of bits to be modified rather
1738
than a pointer to a structure. */
1739
numbits = (int) (size_t) bfixP;
1741
/* This is a no-op, stuck here by reloc_callj(). */
1744
know ((numbits == 13) || (numbits == 24));
1746
/* Propagate sign bit of 'val' for the given number of bits. Result
1747
should be all 0 or all 1. */
1748
sign = val >> ((int) numbits - 1);
1749
if (((val < 0) && (sign != -1))
1750
|| ((val > 0) && (sign != 0)))
1751
as_bad (_("Fixup of %ld too large for field width of %d"),
1755
/* Put bit field into instruction and write back in target
1757
val &= ~(-1 << (int) numbits); /* Clear unused sign bits. */
1759
md_number_to_chars (instrP, instr, 4);
1765
Invocation line includes a switch not recognized by the base assembler.
1766
See if it's a processor-specific option. For the 960, these are:
1769
Conditional branch instructions that require displacements
1770
greater than 13 bits (or that have external targets) should
1771
generate errors. The default is to replace each such
1772
instruction with the corresponding compare (or chkbit) and
1773
branch instructions. Note that the Intel "j" cobr directives
1774
are ALWAYS "de-optimized" in this way when necessary,
1775
regardless of the setting of this option.
1778
Add code to collect information about branches taken, for
1779
later optimization of branch prediction bits by a separate
1780
tool. COBR and CNTL format instructions have branch
1781
prediction bits (in the CX architecture); if "BR" represents
1782
an instruction in one of these classes, the following rep-
1783
resents the code generated by the assembler:
1785
call <increment routine>
1786
.word 0 # pre-counter
1788
call <increment routine>
1789
.word 0 # post-counter
1791
A table of all such "Labels" is also generated.
1793
-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
1794
Select the 80960 architecture. Instructions or features not
1795
supported by the selected architecture cause fatal errors.
1796
The default is to generate code for any instruction or feature
1797
that is supported by SOME version of the 960 (even if this
1798
means mixing architectures!). */
1800
const char *md_shortopts = "A:b";
1801
struct option md_longopts[] =
1803
#define OPTION_LINKRELAX (OPTION_MD_BASE)
1804
{"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
1805
{"link-relax", no_argument, NULL, OPTION_LINKRELAX},
1806
#define OPTION_NORELAX (OPTION_MD_BASE + 1)
1807
{"norelax", no_argument, NULL, OPTION_NORELAX},
1808
{"no-relax", no_argument, NULL, OPTION_NORELAX},
1809
{NULL, no_argument, NULL, 0}
1811
size_t md_longopts_size = sizeof (md_longopts);
1818
static const struct tabentry arch_tab[] =
1822
{"SA", ARCH_KA}, /* Synonym for KA. */
1823
{"SB", ARCH_KB}, /* Synonym for KB. */
1824
{"KC", ARCH_MC}, /* Synonym for MC. */
1833
md_parse_option (int c, char *arg)
1837
case OPTION_LINKRELAX:
1839
flag_keep_locals = 1;
1842
case OPTION_NORELAX:
1847
instrument_branches = 1;
1852
const struct tabentry *tp;
1855
for (tp = arch_tab; tp->flag != NULL; tp++)
1856
if (!strcmp (p, tp->flag))
1859
if (tp->flag == NULL)
1861
as_bad (_("invalid architecture %s"), p);
1865
architecture = tp->arch;
1877
md_show_usage (FILE *stream)
1881
fprintf (stream, _("I960 options:\n"));
1882
for (i = 0; arch_tab[i].flag; i++)
1883
fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1884
fprintf (stream, _("\n\
1885
specify variant of 960 architecture\n\
1886
-b add code to collect statistics about branches taken\n\
1887
-link-relax preserve individual alignment directives so linker\n\
1888
can do relaxing (b.out format only)\n\
1889
-no-relax don't alter compare-and-branch instructions for\n\
1890
long displacements\n"));
1894
Replace cobr instruction in a code fragment with equivalent branch and
1895
compare instructions, so it can reach beyond a 13-bit displacement.
1896
Set up an address fix/relocation for the new branch instruction. */
1898
/* This "conditional jump" table maps cobr instructions into
1899
equivalent compare and branch opcodes. */
1909
{ /* COBR OPCODE: */
1910
{ CHKBIT, BNO }, /* 0x30 - bbc */
1911
{ CMPO, BG }, /* 0x31 - cmpobg */
1912
{ CMPO, BE }, /* 0x32 - cmpobe */
1913
{ CMPO, BGE }, /* 0x33 - cmpobge */
1914
{ CMPO, BL }, /* 0x34 - cmpobl */
1915
{ CMPO, BNE }, /* 0x35 - cmpobne */
1916
{ CMPO, BLE }, /* 0x36 - cmpoble */
1917
{ CHKBIT, BO }, /* 0x37 - bbs */
1918
{ CMPI, BNO }, /* 0x38 - cmpibno */
1919
{ CMPI, BG }, /* 0x39 - cmpibg */
1920
{ CMPI, BE }, /* 0x3a - cmpibe */
1921
{ CMPI, BGE }, /* 0x3b - cmpibge */
1922
{ CMPI, BL }, /* 0x3c - cmpibl */
1923
{ CMPI, BNE }, /* 0x3d - cmpibne */
1924
{ CMPI, BLE }, /* 0x3e - cmpible */
1925
{ CMPI, BO }, /* 0x3f - cmpibo */
1929
relax_cobr (fragS *fragP) /* fragP->fr_opcode is assumed to point to
1930
the cobr instruction, which comes at the
1931
end of the code fragment. */
1933
int opcode, src1, src2, m1, s2;
1934
/* Bit fields from cobr instruction. */
1935
long bp_bits; /* Branch prediction bits from cobr instruction. */
1936
long instr; /* A single i960 instruction. */
1937
/* ->instruction to be replaced. */
1939
fixS *fixP; /* Relocation that can be done at assembly time. */
1941
/* Pick up & parse cobr instruction. */
1942
iP = fragP->fr_opcode;
1943
instr = md_chars_to_number (iP, 4);
1944
opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index. */
1945
src1 = (instr >> 19) & 0x1f;
1946
m1 = (instr >> 13) & 1;
1948
src2 = (instr >> 14) & 0x1f;
1949
bp_bits = instr & BP_MASK;
1951
/* Generate and output compare instruction. */
1952
instr = coj[opcode].compare
1953
| src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
1954
md_number_to_chars (iP, instr, 4);
1956
/* Output branch instruction. */
1957
md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
1959
/* Set up address fixup/relocation. */
1960
fixP = fix_new (fragP,
1961
iP + 4 - fragP->fr_literal,
1968
fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field. */
1976
Called by base assembler after address relaxation is finished: modify
1977
variable fragments according to how much relaxation was done.
1979
If the fragment substate is still 1, a 13-bit displacement was enough
1980
to reach the symbol in question. Set up an address fixup, but otherwise
1981
leave the cobr instruction alone.
1983
If the fragment substate is 2, a 13-bit displacement was not enough.
1984
Replace the cobr with a two instructions (a compare and a branch). */
1987
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1988
segT sec ATTRIBUTE_UNUSED,
1991
/* Structure describing needed address fix. */
1994
switch (fragP->fr_subtype)
1997
/* Leave single cobr instruction. */
1998
fixP = fix_new (fragP,
1999
fragP->fr_opcode - fragP->fr_literal,
2006
fixP->fx_bit_fixP = (bit_fixS *) 13; /* Size of bit field. */
2009
/* Replace cobr with compare/branch instructions. */
2013
BAD_CASE (fragP->fr_subtype);
2018
/* md_estimate_size_before_relax: How much does it look like *fragP will grow?
2020
Called by base assembler just before address relaxation.
2021
Return the amount by which the fragment will grow.
2023
Any symbol that is now undefined will not become defined; cobr's
2024
based on undefined symbols will have to be replaced with a compare
2025
instruction and a branch instruction, and the code fragment will grow
2029
md_estimate_size_before_relax (fragS *fragP, segT segment_type)
2031
/* If symbol is undefined in this segment, go to "relaxed" state
2032
(compare and branch instructions instead of cobr) right now. */
2033
if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
2039
return md_relax_table[fragP->fr_subtype].rlx_length;
2042
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2045
This routine exists in order to overcome machine byte-order problems
2046
when dealing with bit-field entries in the relocation_info struct.
2048
But relocation info will be used on the host machine only (only
2049
executable code is actually downloaded to the i80960). Therefore,
2050
we leave it in host byte order. */
2053
md_ri_to_chars (char *where, struct relocation_info *ri)
2055
host_number_to_chars (where, ri->r_address, 4);
2056
host_number_to_chars (where + 4, ri->r_index, 3);
2058
where[7] = (ri->r_pcrel << 7
2066
where[7] = (ri->r_pcrel << 0
2076
#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
2079
/* brtab_emit: generate the fetch-prediction branch table.
2081
See the comments above the declaration of 'br_cnt' for details on
2082
branch-prediction instrumentation.
2084
The code emitted here would be functionally equivalent to the following
2085
example assembler source.
2090
.word 0 # link to next table
2091
.word 3 # length of table
2092
.word LBRANCH0 # 1st entry in table proper
2101
/* Where the binary was output to. */
2104
if (!instrument_branches)
2107
subseg_set (data_section, 0); /* .data */
2108
frag_align (2, 0, 0); /* .align 2 */
2109
record_alignment (now_seg, 2);
2110
colon (BR_TAB_NAME); /* BR_TAB_NAME: */
2111
emit (0); /* .word 0 #link to next table */
2112
emit (br_cnt); /* .word n #length of table */
2114
for (i = 0; i < br_cnt; i++)
2116
sprintf (buf, "%s%d", BR_LABEL_BASE, i);
2119
p - frag_now->fr_literal,
2120
4, symbol_find (buf), 0, 0, NO_RELOC);
2124
/* s_leafproc: process .leafproc pseudo-op
2126
.leafproc takes two arguments, the second one is optional:
2127
arg[1]: name of 'call' entry point to leaf procedure
2128
arg[2]: name of 'bal' entry point to leaf procedure
2130
If the two arguments are identical, or if the second one is missing,
2131
the first argument is taken to be the 'bal' entry point.
2133
If there are 2 distinct arguments, we must make sure that the 'bal'
2134
entry point immediately follows the 'call' entry point in the linked
2138
s_leafproc (int n_ops, /* Number of operands. */
2139
char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */
2141
symbolS *callP; /* Pointer to leafproc 'call' entry point symbol. */
2142
symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol. */
2144
if ((n_ops != 1) && (n_ops != 2))
2146
as_bad (_("should have 1 or 2 operands"));
2150
/* Find or create symbol for 'call' entry point. */
2151
callP = symbol_find_or_make (args[1]);
2153
if (TC_S_IS_CALLNAME (callP))
2154
as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2156
/* If that was the only argument, use it as the 'bal' entry point.
2157
Otherwise, mark it as the 'call' entry point and find or create
2158
another symbol for the 'bal' entry point. */
2159
if ((n_ops == 1) || !strcmp (args[1], args[2]))
2161
TC_S_FORCE_TO_BALNAME (callP);
2165
TC_S_FORCE_TO_CALLNAME (callP);
2167
balP = symbol_find_or_make (args[2]);
2168
if (TC_S_IS_CALLNAME (balP))
2169
as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2171
TC_S_FORCE_TO_BALNAME (balP);
2174
tc_set_bal_of_call (callP, balP);
2179
/* s_sysproc: process .sysproc pseudo-op
2181
.sysproc takes two arguments:
2182
arg[1]: name of entry point to system procedure
2183
arg[2]: 'entry_num' (index) of system procedure in the range
2186
For [ab].out, we store the 'entrynum' in the 'n_other' field of
2187
the symbol. Since that entry is normally 0, we bias 'entrynum'
2188
by adding 1 to it. It must be unbiased before it is used. */
2191
s_sysproc (int n_ops, /* Number of operands. */
2192
char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */
2199
as_bad (_("should have two operands"));
2203
/* Parse "entry_num" argument and check it for validity. */
2204
parse_expr (args[2], &exp);
2205
if (exp.X_op != O_constant
2207
|| (offs (exp) > 31))
2209
as_bad (_("'entry_num' must be absolute number in [0,31]"));
2213
/* Find/make symbol and stick entry number (biased by +1) into it. */
2214
symP = symbol_find_or_make (args[1]);
2216
if (TC_S_IS_SYSPROC (symP))
2217
as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2219
TC_S_SET_SYSPROC (symP, offs (exp)); /* Encode entry number. */
2220
TC_S_FORCE_TO_SYSPROC (symP);
2223
/* parse_po: parse machine-dependent pseudo-op
2225
This is a top-level routine for machine-dependent pseudo-ops. It slurps
2226
up the rest of the input line, breaks out the individual arguments,
2227
and dispatches them to the correct handler. */
2230
parse_po (int po_num) /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC. */
2232
/* Pointers operands, with no embedded whitespace.
2233
arg[0] unused, arg[1-3]->operands. */
2235
int n_ops; /* Number of operands. */
2236
char *p; /* Pointer to beginning of unparsed argument string. */
2237
char eol; /* Character that indicated end of line. */
2239
extern char is_end_of_line[];
2241
/* Advance input pointer to end of line. */
2242
p = input_line_pointer;
2243
while (!is_end_of_line[(unsigned char) *input_line_pointer])
2244
input_line_pointer++;
2246
eol = *input_line_pointer; /* Save end-of-line char. */
2247
*input_line_pointer = '\0'; /* Terminate argument list. */
2249
/* Parse out operands. */
2250
n_ops = get_args (p, args);
2254
/* Dispatch to correct handler. */
2258
s_sysproc (n_ops, args);
2261
s_leafproc (n_ops, args);
2268
/* Restore eol, so line numbers get updated correctly. Base
2269
assembler assumes we leave input pointer pointing at char
2270
following the eol. */
2271
*input_line_pointer++ = eol;
2274
/* reloc_callj: Relocate a 'callj' instruction
2276
This is a "non-(GNU)-standard" machine-dependent hook. The base
2277
assembler calls it when it decides it can relocate an address at
2278
assembly time instead of emitting a relocation directive.
2280
Check to see if the relocation involves a 'callj' instruction to a:
2281
sysproc: Replace the default 'call' instruction with a 'calls'
2282
leafproc: Replace the default 'call' instruction with a 'bal'.
2283
other proc: Do nothing.
2285
See b.out.h for details on the 'n_other' field in a symbol structure.
2288
Assumes the caller has already figured out, in the case of a leafproc,
2289
to use the 'bal' entry point, and has substituted that symbol into the
2290
passed fixup structure. */
2293
reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */
2295
/* Points to the binary for the instruction being relocated. */
2298
if (!fixP->fx_tcbit)
2299
/* This wasn't a callj instruction in the first place. */
2302
where = fixP->fx_frag->fr_literal + fixP->fx_where;
2304
if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2306
/* Symbol is a .sysproc: replace 'call' with 'calls'. System
2307
procedure number is (other-1). */
2308
md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2310
/* Nothing else needs to be done for this instruction. Make
2311
sure 'md_number_to_field()' will perform a no-op. */
2312
fixP->fx_bit_fixP = (bit_fixS *) 1;
2314
else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2316
/* Should not happen: see block comment above. */
2317
as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2319
else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2321
/* Replace 'call' with 'bal'; both instructions have the same
2322
format, so calling code should complete relocation as if
2323
nothing happened here. */
2324
md_number_to_chars (where, BAL, 4);
2326
else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2327
as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2329
/* Otherwise Symbol is neither a sysproc nor a leafproc. */
2333
/* Handle the MRI .endian pseudo-op. */
2336
s_endian (int ignore ATTRIBUTE_UNUSED)
2341
name = input_line_pointer;
2342
c = get_symbol_end ();
2343
if (strcasecmp (name, "little") == 0)
2345
else if (strcasecmp (name, "big") == 0)
2346
as_bad (_("big endian mode is not supported"));
2348
as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2350
*input_line_pointer = c;
2352
demand_empty_rest_of_line ();
2355
/* We have no need to default values of symbols. */
2358
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
2363
/* Exactly what point is a PC-relative offset relative TO?
2364
On the i960, they're relative to the address of the instruction,
2365
which we have set up as the address of the fixup too. */
2367
md_pcrel_from (fixS *fixP)
2369
return fixP->fx_where + fixP->fx_frag->fr_address;
2373
md_apply_fix (fixS *fixP,
2375
segT seg ATTRIBUTE_UNUSED)
2378
char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2380
if (!fixP->fx_bit_fixP)
2382
md_number_to_imm (place, val, fixP->fx_size);
2384
else if ((int) (size_t) fixP->fx_bit_fixP == 13
2385
&& fixP->fx_addsy != NULL
2386
&& S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
2388
/* This is a COBR instruction. They have only a
2389
13-bit displacement and are only to be used
2390
for local branches: flag as error, don't generate
2392
as_bad_where (fixP->fx_file, fixP->fx_line,
2393
_("can't use COBR format with external label"));
2394
fixP->fx_addsy = NULL;
2397
md_number_to_field (place, val, fixP->fx_bit_fixP);
2399
if (fixP->fx_addsy == NULL)
2403
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2405
tc_bout_fix_to_chars (char *where,
2407
relax_addressT segment_address_in_file)
2409
static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2410
struct relocation_info ri;
2413
memset ((char *) &ri, '\0', sizeof (ri));
2414
symbolP = fixP->fx_addsy;
2415
know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2416
ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2417
/* These two 'cuz of NS32K */
2418
ri.r_callj = fixP->fx_tcbit;
2419
if (fixP->fx_bit_fixP)
2422
ri.r_length = nbytes_r_length[fixP->fx_size];
2423
ri.r_pcrel = fixP->fx_pcrel;
2424
ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2426
if (fixP->fx_r_type != NO_RELOC)
2428
switch (fixP->fx_r_type)
2433
ri.r_length = fixP->fx_size - 1;
2447
else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2450
ri.r_index = symbolP->sy_number;
2455
ri.r_index = S_GET_TYPE (symbolP);
2458
/* Output the relocation information in machine-dependent form. */
2459
md_ri_to_chars (where, &ri);
2462
#endif /* OBJ_AOUT or OBJ_BOUT */
2464
/* Align an address by rounding it up to the specified boundary. */
2467
md_section_align (segT seg,
2468
valueT addr) /* Address to be rounded up. */
2472
align = bfd_get_section_alignment (stdoutput, seg);
2473
return (addr + (1 << align) - 1) & (-1 << align);
2476
extern int coff_flags;
2478
/* For aout or bout, the bal immediately follows the call.
2480
For coff, we cheat and store a pointer to the bal symbol in the
2481
second aux entry of the call. */
2492
tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
2493
symbolS *balP ATTRIBUTE_UNUSED)
2495
know (TC_S_IS_CALLNAME (callP));
2496
know (TC_S_IS_BALNAME (balP));
2500
callP->sy_tc = balP;
2501
S_SET_NUMBER_AUXILIARY (callP, 2);
2503
#else /* ! OBJ_COFF */
2506
/* If the 'bal' entry doesn't immediately follow the 'call'
2507
symbol, unlink it from the symbol list and re-insert it. */
2508
if (symbol_next (callP) != balP)
2510
symbol_remove (balP, &symbol_rootP, &symbol_lastP);
2511
symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
2512
} /* if not in order */
2514
#else /* ! OBJ_ABOUT */
2515
as_fatal ("Only supported for a.out, b.out, or COFF");
2516
#endif /* ! OBJ_ABOUT */
2517
#endif /* ! OBJ_COFF */
2521
tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
2525
know (TC_S_IS_CALLNAME (callP));
2528
retval = callP->sy_tc;
2531
retval = symbol_next (callP);
2533
as_fatal ("Only supported for a.out, b.out, or COFF");
2534
#endif /* ! OBJ_ABOUT */
2535
#endif /* ! OBJ_COFF */
2537
know (TC_S_IS_BALNAME (retval));
2543
tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
2545
if (TC_S_IS_CALLNAME (symbolP))
2547
symbolS *balP = tc_get_bal_of_call (symbolP);
2549
symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
2550
if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
2551
S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
2553
S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
2554
S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
2555
/* Fix up the bal symbol. */
2556
S_SET_STORAGE_CLASS (balP, C_LABEL);
2559
#endif /* OBJ_COFF */
2562
i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
2568
as_bad (_("option --link-relax is only supported in b.out format"));
2573
/* The text section "ends" with another alignment reloc, to which we
2574
aren't adding padding. */
2575
if (fragp->fr_next == text_last_frag
2576
|| fragp->fr_next == data_last_frag)
2579
/* alignment directive */
2580
fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
2581
(int) fragp->fr_type);
2582
#endif /* OBJ_BOUT */
2586
i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
2588
if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
2590
/* Relocation should be done via the associated 'bal'
2591
entry point symbol. */
2592
if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
2594
as_bad_where (fixP->fx_file, fixP->fx_line,
2595
_("No 'bal' entry point for leafproc %s"),
2596
S_GET_NAME (fixP->fx_addsy));
2599
fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
2608
tc_bfd_fix2rtype (fixS *fixP)
2610
if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2611
return BFD_RELOC_32;
2613
if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2614
return BFD_RELOC_24_PCREL;
2620
/* Translate internal representation of relocation info to BFD target
2623
FIXME: To what extent can we get all relevant targets to use this? */
2626
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
2630
reloc = xmalloc (sizeof (arelent));
2632
/* HACK: Is this right? */
2633
fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
2635
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
2636
if (reloc->howto == NULL)
2638
as_bad_where (fixP->fx_file, fixP->fx_line,
2639
_("internal error: can't export reloc type %d (`%s')"),
2641
bfd_get_reloc_code_name (fixP->fx_r_type));
2645
gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
2647
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
2648
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2649
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
2650
reloc->addend = fixP->fx_addnumber;
2655
/* end from cgen.c */
2657
const pseudo_typeS md_pseudo_table[] =
2659
{"bss", s_lcomm, 1},
2660
{"endian", s_endian, 0},
2661
{"extended", float_cons, 't'},
2662
{"leafproc", parse_po, S_LEAFPROC},
2663
{"sysproc", parse_po, S_SYSPROC},
added
removed
binutils-2.23.52.20130611/gas/config/tc-i960.c
