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#name: ARM V7-A+MP instructions
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#objdump: -dr --prefix-addresses --show-raw-insn
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#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
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0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
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0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
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0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
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0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfff
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0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
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0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
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0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
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0[0-9a-f]+ <[^>]+> f790f001 pldw \[r0, r1\]
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0[0-9a-f]+ <[^>]+> f790f00e pldw \[r0, lr\]
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0[0-9a-f]+ <[^>]+> f790f100 pldw \[r0, r0, lsl #2\]
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0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
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0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
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0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
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0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
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0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
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0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
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0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
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0[0-9a-f]+ <[^>]+> f83e f000 pldw \[lr, r0\]
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0[0-9a-f]+ <[^>]+> f830 f001 pldw \[r0, r1\]
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0[0-9a-f]+ <[^>]+> f830 f00e pldw \[r0, lr\]
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0[0-9a-f]+ <[^>]+> f830 f030 pldw \[r0, r0, lsl #3\]