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@ LDC group relocation tests.
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@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
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.macro ldctest load store
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\load 0, c0, [r0, #:pc_g0:(f + 0x214)]
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\load 0, c0, [r0, #:pc_g1:(f + 0x214)]
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\load 0, c0, [r0, #:pc_g2:(f + 0x214)]
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\load 0, c0, [r0, #:sb_g0:(f + 0x214)]
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\load 0, c0, [r0, #:sb_g1:(f + 0x214)]
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\load 0, c0, [r0, #:sb_g2:(f + 0x214)]
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\store 0, c0, [r0, #:pc_g0:(f + 0x214)]
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\store 0, c0, [r0, #:pc_g1:(f + 0x214)]
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\store 0, c0, [r0, #:pc_g2:(f + 0x214)]
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\store 0, c0, [r0, #:sb_g0:(f + 0x214)]
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\store 0, c0, [r0, #:sb_g1:(f + 0x214)]
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\store 0, c0, [r0, #:sb_g2:(f + 0x214)]
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\load 0, c0, [r0, #:pc_g0:(f - 0x214)]
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\load 0, c0, [r0, #:pc_g1:(f - 0x214)]
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\load 0, c0, [r0, #:pc_g2:(f - 0x214)]
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\load 0, c0, [r0, #:sb_g0:(f - 0x214)]
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\load 0, c0, [r0, #:sb_g1:(f - 0x214)]
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\load 0, c0, [r0, #:sb_g2:(f - 0x214)]
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\store 0, c0, [r0, #:pc_g0:(f - 0x214)]
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\store 0, c0, [r0, #:pc_g1:(f - 0x214)]
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\store 0, c0, [r0, #:pc_g2:(f - 0x214)]
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\store 0, c0, [r0, #:sb_g0:(f - 0x214)]
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\store 0, c0, [r0, #:sb_g1:(f - 0x214)]
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\store 0, c0, [r0, #:sb_g2:(f - 0x214)]
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@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
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.macro fpa_test load store
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\load f0, [r0, #:pc_g0:(f + 0x214)]
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\load f0, [r0, #:pc_g1:(f + 0x214)]
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\load f0, [r0, #:pc_g2:(f + 0x214)]
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\load f0, [r0, #:sb_g0:(f + 0x214)]
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\load f0, [r0, #:sb_g1:(f + 0x214)]
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\load f0, [r0, #:sb_g2:(f + 0x214)]
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\store f0, [r0, #:pc_g0:(f + 0x214)]
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\store f0, [r0, #:pc_g1:(f + 0x214)]
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\store f0, [r0, #:pc_g2:(f + 0x214)]
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\store f0, [r0, #:sb_g0:(f + 0x214)]
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\store f0, [r0, #:sb_g1:(f + 0x214)]
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\store f0, [r0, #:sb_g2:(f + 0x214)]
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\load f0, [r0, #:pc_g0:(f - 0x214)]
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\load f0, [r0, #:pc_g1:(f - 0x214)]
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\load f0, [r0, #:pc_g2:(f - 0x214)]
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\load f0, [r0, #:sb_g0:(f - 0x214)]
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\load f0, [r0, #:sb_g1:(f - 0x214)]
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\load f0, [r0, #:sb_g2:(f - 0x214)]
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\store f0, [r0, #:pc_g0:(f - 0x214)]
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\store f0, [r0, #:pc_g1:(f - 0x214)]
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\store f0, [r0, #:pc_g2:(f - 0x214)]
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\store f0, [r0, #:sb_g0:(f - 0x214)]
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\store f0, [r0, #:sb_g1:(f - 0x214)]
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\store f0, [r0, #:sb_g2:(f - 0x214)]
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.macro vfp_test load store reg
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\load \reg, [r0, #:pc_g0:(f + 0x214)]
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\load \reg, [r0, #:pc_g1:(f + 0x214)]
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\load \reg, [r0, #:pc_g2:(f + 0x214)]
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\load \reg, [r0, #:sb_g0:(f + 0x214)]
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\load \reg, [r0, #:sb_g1:(f + 0x214)]
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\load \reg, [r0, #:sb_g2:(f + 0x214)]
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\store \reg, [r0, #:pc_g0:(f + 0x214)]
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\store \reg, [r0, #:pc_g1:(f + 0x214)]
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\store \reg, [r0, #:pc_g2:(f + 0x214)]
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\store \reg, [r0, #:sb_g0:(f + 0x214)]
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\store \reg, [r0, #:sb_g1:(f + 0x214)]
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\store \reg, [r0, #:sb_g2:(f + 0x214)]
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\load \reg, [r0, #:pc_g0:(f - 0x214)]
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\load \reg, [r0, #:pc_g1:(f - 0x214)]
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\load \reg, [r0, #:pc_g2:(f - 0x214)]
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\load \reg, [r0, #:sb_g0:(f - 0x214)]
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\load \reg, [r0, #:sb_g1:(f - 0x214)]
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\load \reg, [r0, #:sb_g2:(f - 0x214)]
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\store \reg, [r0, #:pc_g0:(f - 0x214)]
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\store \reg, [r0, #:pc_g1:(f - 0x214)]
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\store \reg, [r0, #:pc_g2:(f - 0x214)]
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\store \reg, [r0, #:sb_g0:(f - 0x214)]
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\store \reg, [r0, #:sb_g1:(f - 0x214)]
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\store \reg, [r0, #:sb_g2:(f - 0x214)]
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vfp_test flds fsts s0
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vfp_test fldd fstd d0
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vfp_test vldr vstr d0
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@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
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vfp_test cfldrs cfstrs mvf0
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vfp_test cfldrd cfstrd mvd0
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vfp_test cfldr32 cfstr32 mvfx0
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vfp_test cfldr64 cfstr64 mvdx0