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/* addsub.s Test file for AArch64 add-subtract instructions.
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Copyright 2012 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the license, or
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(at your option) any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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// TODO: also cover the addsub_imm instructions.
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.macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
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// for 64-bit instruction, Rm is Xm when <extend> is explicitely
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// or implicitly UXTX, SXTX or LSL; otherwise it Wm.
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\op \rd, \rn, W\()\rm_n, \extend
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\op \rd, \rn, W\()\rm_n, \extend #\amount
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\op \rd, \rn, \rm_r\()\rm_n, \extend
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\op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
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* Emitting addsub_ext instruction
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.macro do_addsub_ext type, op, Rn, reg, extend, amount
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// normal add/adds/sub/subs
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\op \reg\()16, \Rn, \reg\()1
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adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
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adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
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// adds/subs with ZR as Rd
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\op \reg\()ZR, \Rn, \reg\()1
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adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend
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adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend, \amount
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\op \Rn, \reg\()1, \extend
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\op \Rn, \reg\()1, \extend #\amount
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* Optional extension and optional shift amount
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.macro do_extend type, op, Rn, reg
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// note that when SP is not used, the GAS will encode it as addsub_shift
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do_addsub_ext \type, \op, \Rn, \reg
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// optional absent <amount>
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.irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
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.irp amount, , 0, 1, 2, 3, 4
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do_addsub_ext \type, \op, \Rn, \reg, \extend, \amount
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// when <extend> is LSL, <amount> cannot be absent
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// note that when SP is not used, the GAS will encode it as addsub_shift
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.irp amount, 0, 1, 2, 3, 4
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do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
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* Leaf macro emitting addsub_shift instruction
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.macro do_addsub_shift type, op, R, reg, shift, amount
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// normal add/adds/sub/subs
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\op \reg\()16, \R, \reg\()1
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\op \reg\()16, \R, \reg\()1, \shift #\amount
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// adds/subs with ZR as Rd
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\op \reg\()ZR, \R, \reg\()1
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\op \reg\()ZR, \R, \reg\()1, \shift #\amount
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\op \R, \reg\()1, \shift #\amount
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// sub/subs with ZR as Rn
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\op \R, \reg\()ZR, \reg\()1
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\op \R, \reg\()ZR, \reg\()1, \shift #\amount
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* Optional shift and optional shift amount
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.macro do_shift type, op, R, reg
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do_addsub_shift \type, \op, \R, \reg
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// optional absent <amount>
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.irp shift, LSL, LSR, ASR
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.irp amount, 0, 1, 2, 3, 4, 5, 16, 31
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// amount cannot be absent when shift is present.
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do_addsub_shift \type, \op, \R, \reg, \shift, \amount
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do_addsub_shift \type, \op, \R, \reg, \shift, 63
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* Add-subtract (extended register)
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.irp op, ADD, ADDS, SUB, SUBS
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do_extend 0, \op, W7, W
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do_extend 0, \op, WSP, W
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do_extend 0, \op, X7, X
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do_extend 0, \op, SP, X
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do_extend 1, \op, W7, W
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do_extend 1, \op, WSP, W
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do_extend 1, \op, X7, X
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do_extend 1, \op, SP, X
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do_extend 2, \op, W7, W
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do_extend 2, \op, WSP, W
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do_extend 2, \op, X7, X
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do_extend 2, \op, SP, X
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* Add-subtract (shift register)
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.irp op, ADD, ADDS, SUB, SUBS
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do_shift 0, \op, W7, W
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do_shift 0, \op, X7, X
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do_shift 1, \op, W7, W
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do_shift 1, \op, X7, X
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do_shift 2, \op, W7, W
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do_shift 2, \op, X7, X
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do_shift 3, \op, W7, W
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do_shift 3, \op, X7, X
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do_shift 2, \op, W7, W
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do_shift 2, \op, X7, X