1
/* Instruction building/extraction support for m32r. -*- C -*-
3
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4
- the resultant file is machine generated, cgen-ibld.in isn't
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
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2008, 2010 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
22
along with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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#include "m32r-desc.h"
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#include "cgen/basic-modes.h"
38
#include "safe-ctype.h"
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#define max(a,b) ((a) > (b) ? (a) : (b))
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/* Used by the ifield rtx function. */
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#define FLD(f) (fields->f)
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static const char * insert_normal
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(CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
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static const char * insert_insn_normal
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(CGEN_CPU_DESC, const CGEN_INSN *,
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CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
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static int extract_normal
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
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unsigned int, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, bfd_vma, long *);
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static int extract_insn_normal
59
(CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
62
static void put_insn_int_value
63
(CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
66
static CGEN_INLINE void insert_1
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(CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
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static CGEN_INLINE int fill_cache
69
(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
70
static CGEN_INLINE long extract_1
71
(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
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/* Operand insertion. */
78
/* Subroutine of insert_normal. */
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static CGEN_INLINE void
81
insert_1 (CGEN_CPU_DESC cd,
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x = cgen_get_insn_value (cd, bufp, word_length);
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/* Written this way to avoid undefined behaviour. */
94
mask = (((1L << (length - 1)) - 1) << 1) | 1;
96
shift = (start + 1) - length;
98
shift = (word_length - (start + length));
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x = (x & ~(mask << shift)) | ((value & mask) << shift);
101
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
104
#endif /* ! CGEN_INT_INSN_P */
106
/* Default insertion routine.
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ATTRS is a mask of the boolean attributes.
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WORD_OFFSET is the offset in bits from the start of the insn of the value.
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WORD_LENGTH is the length of the word in bits in which the value resides.
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START is the starting bit number in the word, architecture origin.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn in bits.
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The result is an error message or NULL if success. */
117
/* ??? This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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/* ??? This doesn't handle bfd_vma's. Create another function when
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insert_normal (CGEN_CPU_DESC cd,
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unsigned int word_offset,
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unsigned int word_length,
130
unsigned int total_length,
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CGEN_INSN_BYTES_PTR buffer)
133
static char errbuf[100];
134
/* Written this way to avoid undefined behaviour. */
135
unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
137
/* If LENGTH is zero, this operand doesn't contribute to the value. */
141
if (word_length > 8 * sizeof (CGEN_INSN_INT))
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/* For architectures with insns smaller than the base-insn-bitsize,
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word_length may be too big. */
146
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
149
&& word_length > total_length)
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word_length = total_length;
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/* Ensure VALUE will fit. */
154
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
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long minval = - (1L << (length - 1));
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unsigned long maxval = mask;
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if ((value > 0 && (unsigned long) value > maxval)
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/* xgettext:c-format */
164
_("operand out of range (%ld not between %ld and %lu)"),
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value, minval, maxval);
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else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
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unsigned long maxval = mask;
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unsigned long val = (unsigned long) value;
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/* For hosts with a word size > 32 check to see if value has been sign
175
extended beyond 32 bits. If so then ignore these higher sign bits
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as the user is attempting to store a 32-bit signed value into an
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unsigned 32-bit field which is allowed. */
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if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
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/* xgettext:c-format */
185
_("operand out of range (0x%lx not between 0 and 0x%lx)"),
192
if (! cgen_signed_overflow_ok_p (cd))
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long minval = - (1L << (length - 1));
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long maxval = (1L << (length - 1)) - 1;
197
if (value < minval || value > maxval)
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/* xgettext:c-format */
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(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
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value, minval, maxval);
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if (CGEN_INSN_LSB0_P)
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shift = (word_offset + start + 1) - length;
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shift = total_length - (word_offset + start + length);
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*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
220
#else /* ! CGEN_INT_INSN_P */
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unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
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insert_1 (cd, value, start, length, word_length, bufp);
228
#endif /* ! CGEN_INT_INSN_P */
233
/* Default insn builder (insert handler).
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The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
235
that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
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recorded in host byte order, otherwise BUFFER is an array of bytes
237
and the value is recorded in target byte order).
238
The result is an error message or NULL if success. */
241
insert_insn_normal (CGEN_CPU_DESC cd,
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const CGEN_INSN * insn,
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CGEN_FIELDS * fields,
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CGEN_INSN_BYTES_PTR buffer,
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
249
const CGEN_SYNTAX_CHAR_TYPE * syn;
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CGEN_INIT_INSERT (cd);
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value = CGEN_INSN_BASE_VALUE (insn);
254
/* If we're recording insns as numbers (rather than a string of bytes),
255
target byte order handling is deferred until later. */
259
put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
260
CGEN_FIELDS_BITSIZE (fields), value);
264
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
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(unsigned) CGEN_FIELDS_BITSIZE (fields)),
268
#endif /* ! CGEN_INT_INSN_P */
270
/* ??? It would be better to scan the format's fields.
271
Still need to be able to insert a value based on the operand though;
272
e.g. storing a branch displacement that got resolved later.
273
Needs more thought first. */
275
for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
279
if (CGEN_SYNTAX_CHAR_P (* syn))
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errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
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/* Cover function to store an insn value into an integral insn. Must go here
293
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
296
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
297
CGEN_INSN_BYTES_PTR buf,
302
/* For architectures with insns smaller than the base-insn-bitsize,
303
length may be too big. */
304
if (length > insn_length)
308
int shift = insn_length - length;
309
/* Written this way to avoid undefined behaviour. */
310
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
312
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
317
/* Operand extraction. */
319
#if ! CGEN_INT_INSN_P
321
/* Subroutine of extract_normal.
322
Ensure sufficient bytes are cached in EX_INFO.
323
OFFSET is the offset in bytes from the start of the insn of the value.
324
BYTES is the length of the needed value.
325
Returns 1 for success, 0 for failure. */
327
static CGEN_INLINE int
328
fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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CGEN_EXTRACT_INFO *ex_info,
334
/* It's doubtful that the middle part has already been fetched so
335
we don't optimize that case. kiss. */
337
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
339
/* First do a quick check. */
340
mask = (1 << bytes) - 1;
341
if (((ex_info->valid >> offset) & mask) == mask)
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/* Search for the first byte we need to read. */
345
for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
346
if (! (mask & ex_info->valid))
354
status = (*info->read_memory_func)
355
(pc, ex_info->insn_bytes + offset, bytes, info);
359
(*info->memory_error_func) (status, pc, info);
363
ex_info->valid |= ((1 << bytes) - 1) << offset;
369
/* Subroutine of extract_normal. */
371
static CGEN_INLINE long
372
extract_1 (CGEN_CPU_DESC cd,
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CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED)
383
x = cgen_get_insn_value (cd, bufp, word_length);
385
if (CGEN_INSN_LSB0_P)
386
shift = (start + 1) - length;
388
shift = (word_length - (start + length));
392
#endif /* ! CGEN_INT_INSN_P */
394
/* Default extraction routine.
396
INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
397
or sometimes less for cases like the m32r where the base insn size is 32
398
but some insns are 16 bits.
399
ATTRS is a mask of the boolean attributes. We only need `SIGNED',
400
but for generality we take a bitmask of all of them.
401
WORD_OFFSET is the offset in bits from the start of the insn of the value.
402
WORD_LENGTH is the length of the word in bits in which the value resides.
403
START is the starting bit number in the word, architecture origin.
404
LENGTH is the length of VALUE in bits.
405
TOTAL_LENGTH is the total length of the insn in bits.
407
Returns 1 for success, 0 for failure. */
409
/* ??? The return code isn't properly used. wip. */
411
/* ??? This doesn't handle bfd_vma's. Create another function when
415
extract_normal (CGEN_CPU_DESC cd,
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#if ! CGEN_INT_INSN_P
417
CGEN_EXTRACT_INFO *ex_info,
419
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
421
CGEN_INSN_INT insn_value,
423
unsigned int word_offset,
426
unsigned int word_length,
427
unsigned int total_length,
428
#if ! CGEN_INT_INSN_P
431
bfd_vma pc ATTRIBUTE_UNUSED,
437
/* If LENGTH is zero, this operand doesn't contribute to the value
438
so give it a standard value of zero. */
445
if (word_length > 8 * sizeof (CGEN_INSN_INT))
448
/* For architectures with insns smaller than the insn-base-bitsize,
449
word_length may be too big. */
450
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
452
if (word_offset + word_length > total_length)
453
word_length = total_length - word_offset;
456
/* Does the value reside in INSN_VALUE, and at the right alignment? */
458
if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
460
if (CGEN_INSN_LSB0_P)
461
value = insn_value >> ((word_offset + start + 1) - length);
463
value = insn_value >> (total_length - ( word_offset + start + length));
466
#if ! CGEN_INT_INSN_P
470
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
472
if (word_length > 8 * sizeof (CGEN_INSN_INT))
475
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
478
value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
481
#endif /* ! CGEN_INT_INSN_P */
483
/* Written this way to avoid undefined behaviour. */
484
mask = (((1L << (length - 1)) - 1) << 1) | 1;
488
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
489
&& (value & (1L << (length - 1))))
497
/* Default insn extractor.
499
INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
500
The extracted fields are stored in FIELDS.
501
EX_INFO is used to handle reading variable length insns.
502
Return the length of the insn in bits, or 0 if no match,
503
or -1 if an error occurs fetching data (memory_error_func will have
507
extract_insn_normal (CGEN_CPU_DESC cd,
508
const CGEN_INSN *insn,
509
CGEN_EXTRACT_INFO *ex_info,
510
CGEN_INSN_INT insn_value,
514
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
515
const CGEN_SYNTAX_CHAR_TYPE *syn;
517
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
519
CGEN_INIT_EXTRACT (cd);
521
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
525
if (CGEN_SYNTAX_CHAR_P (*syn))
528
length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
529
ex_info, insn_value, fields, pc);
534
/* We recognized and successfully extracted this insn. */
535
return CGEN_INSN_BITSIZE (insn);
538
/* Machine generated code added here. */
540
const char * m32r_cgen_insert_operand
541
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
543
/* Main entry point for operand insertion.
545
This function is basically just a big switch statement. Earlier versions
546
used tables to look up the function to use, but
547
- if the table contains both assembler and disassembler functions then
548
the disassembler contains much of the assembler and vice-versa,
549
- there's a lot of inlining possibilities as things grow,
550
- using a switch statement avoids the function call overhead.
552
This function could be moved into `parse_insn_normal', but keeping it
553
separate makes clear the interface between `parse_insn_normal' and each of
554
the handlers. It's also needed by GAS to insert operands that couldn't be
555
resolved during parsing. */
558
m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
560
CGEN_FIELDS * fields,
561
CGEN_INSN_BYTES_PTR buffer,
562
bfd_vma pc ATTRIBUTE_UNUSED)
564
const char * errmsg = NULL;
565
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
569
case M32R_OPERAND_ACC :
570
errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
572
case M32R_OPERAND_ACCD :
573
errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
575
case M32R_OPERAND_ACCS :
576
errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
578
case M32R_OPERAND_DCR :
579
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
581
case M32R_OPERAND_DISP16 :
583
long value = fields->f_disp16;
584
value = ((SI) (((value) - (pc))) >> (2));
585
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
588
case M32R_OPERAND_DISP24 :
590
long value = fields->f_disp24;
591
value = ((SI) (((value) - (pc))) >> (2));
592
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
595
case M32R_OPERAND_DISP8 :
597
long value = fields->f_disp8;
598
value = ((SI) (((value) - (((pc) & (-4))))) >> (2));
599
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
602
case M32R_OPERAND_DR :
603
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
605
case M32R_OPERAND_HASH :
607
case M32R_OPERAND_HI16 :
608
errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
610
case M32R_OPERAND_IMM1 :
612
long value = fields->f_imm1;
613
value = ((value) - (1));
614
errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
617
case M32R_OPERAND_SCR :
618
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
620
case M32R_OPERAND_SIMM16 :
621
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
623
case M32R_OPERAND_SIMM8 :
624
errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
626
case M32R_OPERAND_SLO16 :
627
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
629
case M32R_OPERAND_SR :
630
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
632
case M32R_OPERAND_SRC1 :
633
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
635
case M32R_OPERAND_SRC2 :
636
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
638
case M32R_OPERAND_UIMM16 :
639
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
641
case M32R_OPERAND_UIMM24 :
642
errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
644
case M32R_OPERAND_UIMM3 :
645
errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
647
case M32R_OPERAND_UIMM4 :
648
errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
650
case M32R_OPERAND_UIMM5 :
651
errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
653
case M32R_OPERAND_UIMM8 :
654
errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
656
case M32R_OPERAND_ULO16 :
657
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
661
/* xgettext:c-format */
662
fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
670
int m32r_cgen_extract_operand
671
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
673
/* Main entry point for operand extraction.
674
The result is <= 0 for error, >0 for success.
675
??? Actual values aren't well defined right now.
677
This function is basically just a big switch statement. Earlier versions
678
used tables to look up the function to use, but
679
- if the table contains both assembler and disassembler functions then
680
the disassembler contains much of the assembler and vice-versa,
681
- there's a lot of inlining possibilities as things grow,
682
- using a switch statement avoids the function call overhead.
684
This function could be moved into `print_insn_normal', but keeping it
685
separate makes clear the interface between `print_insn_normal' and each of
689
m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
691
CGEN_EXTRACT_INFO *ex_info,
692
CGEN_INSN_INT insn_value,
693
CGEN_FIELDS * fields,
696
/* Assume success (for those operands that are nops). */
698
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
702
case M32R_OPERAND_ACC :
703
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
705
case M32R_OPERAND_ACCD :
706
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
708
case M32R_OPERAND_ACCS :
709
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
711
case M32R_OPERAND_DCR :
712
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
714
case M32R_OPERAND_DISP16 :
717
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
718
value = ((((value) << (2))) + (pc));
719
fields->f_disp16 = value;
722
case M32R_OPERAND_DISP24 :
725
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
726
value = ((((value) << (2))) + (pc));
727
fields->f_disp24 = value;
730
case M32R_OPERAND_DISP8 :
733
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
734
value = ((((value) << (2))) + (((pc) & (-4))));
735
fields->f_disp8 = value;
738
case M32R_OPERAND_DR :
739
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
741
case M32R_OPERAND_HASH :
743
case M32R_OPERAND_HI16 :
744
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
746
case M32R_OPERAND_IMM1 :
749
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
750
value = ((value) + (1));
751
fields->f_imm1 = value;
754
case M32R_OPERAND_SCR :
755
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
757
case M32R_OPERAND_SIMM16 :
758
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
760
case M32R_OPERAND_SIMM8 :
761
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
763
case M32R_OPERAND_SLO16 :
764
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
766
case M32R_OPERAND_SR :
767
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
769
case M32R_OPERAND_SRC1 :
770
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
772
case M32R_OPERAND_SRC2 :
773
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
775
case M32R_OPERAND_UIMM16 :
776
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
778
case M32R_OPERAND_UIMM24 :
779
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
781
case M32R_OPERAND_UIMM3 :
782
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
784
case M32R_OPERAND_UIMM4 :
785
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
787
case M32R_OPERAND_UIMM5 :
788
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
790
case M32R_OPERAND_UIMM8 :
791
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
793
case M32R_OPERAND_ULO16 :
794
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
798
/* xgettext:c-format */
799
fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
807
cgen_insert_fn * const m32r_cgen_insert_handlers[] =
812
cgen_extract_fn * const m32r_cgen_extract_handlers[] =
817
int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
818
bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
820
/* Getting values from cgen_fields is handled by a collection of functions.
821
They are distinguished by the type of the VALUE argument they return.
822
TODO: floating point, inlining support, remove cases where result type
826
m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
828
const CGEN_FIELDS * fields)
834
case M32R_OPERAND_ACC :
835
value = fields->f_acc;
837
case M32R_OPERAND_ACCD :
838
value = fields->f_accd;
840
case M32R_OPERAND_ACCS :
841
value = fields->f_accs;
843
case M32R_OPERAND_DCR :
844
value = fields->f_r1;
846
case M32R_OPERAND_DISP16 :
847
value = fields->f_disp16;
849
case M32R_OPERAND_DISP24 :
850
value = fields->f_disp24;
852
case M32R_OPERAND_DISP8 :
853
value = fields->f_disp8;
855
case M32R_OPERAND_DR :
856
value = fields->f_r1;
858
case M32R_OPERAND_HASH :
861
case M32R_OPERAND_HI16 :
862
value = fields->f_hi16;
864
case M32R_OPERAND_IMM1 :
865
value = fields->f_imm1;
867
case M32R_OPERAND_SCR :
868
value = fields->f_r2;
870
case M32R_OPERAND_SIMM16 :
871
value = fields->f_simm16;
873
case M32R_OPERAND_SIMM8 :
874
value = fields->f_simm8;
876
case M32R_OPERAND_SLO16 :
877
value = fields->f_simm16;
879
case M32R_OPERAND_SR :
880
value = fields->f_r2;
882
case M32R_OPERAND_SRC1 :
883
value = fields->f_r1;
885
case M32R_OPERAND_SRC2 :
886
value = fields->f_r2;
888
case M32R_OPERAND_UIMM16 :
889
value = fields->f_uimm16;
891
case M32R_OPERAND_UIMM24 :
892
value = fields->f_uimm24;
894
case M32R_OPERAND_UIMM3 :
895
value = fields->f_uimm3;
897
case M32R_OPERAND_UIMM4 :
898
value = fields->f_uimm4;
900
case M32R_OPERAND_UIMM5 :
901
value = fields->f_uimm5;
903
case M32R_OPERAND_UIMM8 :
904
value = fields->f_uimm8;
906
case M32R_OPERAND_ULO16 :
907
value = fields->f_uimm16;
911
/* xgettext:c-format */
912
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
921
m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
923
const CGEN_FIELDS * fields)
929
case M32R_OPERAND_ACC :
930
value = fields->f_acc;
932
case M32R_OPERAND_ACCD :
933
value = fields->f_accd;
935
case M32R_OPERAND_ACCS :
936
value = fields->f_accs;
938
case M32R_OPERAND_DCR :
939
value = fields->f_r1;
941
case M32R_OPERAND_DISP16 :
942
value = fields->f_disp16;
944
case M32R_OPERAND_DISP24 :
945
value = fields->f_disp24;
947
case M32R_OPERAND_DISP8 :
948
value = fields->f_disp8;
950
case M32R_OPERAND_DR :
951
value = fields->f_r1;
953
case M32R_OPERAND_HASH :
956
case M32R_OPERAND_HI16 :
957
value = fields->f_hi16;
959
case M32R_OPERAND_IMM1 :
960
value = fields->f_imm1;
962
case M32R_OPERAND_SCR :
963
value = fields->f_r2;
965
case M32R_OPERAND_SIMM16 :
966
value = fields->f_simm16;
968
case M32R_OPERAND_SIMM8 :
969
value = fields->f_simm8;
971
case M32R_OPERAND_SLO16 :
972
value = fields->f_simm16;
974
case M32R_OPERAND_SR :
975
value = fields->f_r2;
977
case M32R_OPERAND_SRC1 :
978
value = fields->f_r1;
980
case M32R_OPERAND_SRC2 :
981
value = fields->f_r2;
983
case M32R_OPERAND_UIMM16 :
984
value = fields->f_uimm16;
986
case M32R_OPERAND_UIMM24 :
987
value = fields->f_uimm24;
989
case M32R_OPERAND_UIMM3 :
990
value = fields->f_uimm3;
992
case M32R_OPERAND_UIMM4 :
993
value = fields->f_uimm4;
995
case M32R_OPERAND_UIMM5 :
996
value = fields->f_uimm5;
998
case M32R_OPERAND_UIMM8 :
999
value = fields->f_uimm8;
1001
case M32R_OPERAND_ULO16 :
1002
value = fields->f_uimm16;
1006
/* xgettext:c-format */
1007
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1015
void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1016
void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
1018
/* Stuffing values in cgen_fields is handled by a collection of functions.
1019
They are distinguished by the type of the VALUE argument they accept.
1020
TODO: floating point, inlining support, remove cases where argument type
1024
m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1026
CGEN_FIELDS * fields,
1031
case M32R_OPERAND_ACC :
1032
fields->f_acc = value;
1034
case M32R_OPERAND_ACCD :
1035
fields->f_accd = value;
1037
case M32R_OPERAND_ACCS :
1038
fields->f_accs = value;
1040
case M32R_OPERAND_DCR :
1041
fields->f_r1 = value;
1043
case M32R_OPERAND_DISP16 :
1044
fields->f_disp16 = value;
1046
case M32R_OPERAND_DISP24 :
1047
fields->f_disp24 = value;
1049
case M32R_OPERAND_DISP8 :
1050
fields->f_disp8 = value;
1052
case M32R_OPERAND_DR :
1053
fields->f_r1 = value;
1055
case M32R_OPERAND_HASH :
1057
case M32R_OPERAND_HI16 :
1058
fields->f_hi16 = value;
1060
case M32R_OPERAND_IMM1 :
1061
fields->f_imm1 = value;
1063
case M32R_OPERAND_SCR :
1064
fields->f_r2 = value;
1066
case M32R_OPERAND_SIMM16 :
1067
fields->f_simm16 = value;
1069
case M32R_OPERAND_SIMM8 :
1070
fields->f_simm8 = value;
1072
case M32R_OPERAND_SLO16 :
1073
fields->f_simm16 = value;
1075
case M32R_OPERAND_SR :
1076
fields->f_r2 = value;
1078
case M32R_OPERAND_SRC1 :
1079
fields->f_r1 = value;
1081
case M32R_OPERAND_SRC2 :
1082
fields->f_r2 = value;
1084
case M32R_OPERAND_UIMM16 :
1085
fields->f_uimm16 = value;
1087
case M32R_OPERAND_UIMM24 :
1088
fields->f_uimm24 = value;
1090
case M32R_OPERAND_UIMM3 :
1091
fields->f_uimm3 = value;
1093
case M32R_OPERAND_UIMM4 :
1094
fields->f_uimm4 = value;
1096
case M32R_OPERAND_UIMM5 :
1097
fields->f_uimm5 = value;
1099
case M32R_OPERAND_UIMM8 :
1100
fields->f_uimm8 = value;
1102
case M32R_OPERAND_ULO16 :
1103
fields->f_uimm16 = value;
1107
/* xgettext:c-format */
1108
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1115
m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1117
CGEN_FIELDS * fields,
1122
case M32R_OPERAND_ACC :
1123
fields->f_acc = value;
1125
case M32R_OPERAND_ACCD :
1126
fields->f_accd = value;
1128
case M32R_OPERAND_ACCS :
1129
fields->f_accs = value;
1131
case M32R_OPERAND_DCR :
1132
fields->f_r1 = value;
1134
case M32R_OPERAND_DISP16 :
1135
fields->f_disp16 = value;
1137
case M32R_OPERAND_DISP24 :
1138
fields->f_disp24 = value;
1140
case M32R_OPERAND_DISP8 :
1141
fields->f_disp8 = value;
1143
case M32R_OPERAND_DR :
1144
fields->f_r1 = value;
1146
case M32R_OPERAND_HASH :
1148
case M32R_OPERAND_HI16 :
1149
fields->f_hi16 = value;
1151
case M32R_OPERAND_IMM1 :
1152
fields->f_imm1 = value;
1154
case M32R_OPERAND_SCR :
1155
fields->f_r2 = value;
1157
case M32R_OPERAND_SIMM16 :
1158
fields->f_simm16 = value;
1160
case M32R_OPERAND_SIMM8 :
1161
fields->f_simm8 = value;
1163
case M32R_OPERAND_SLO16 :
1164
fields->f_simm16 = value;
1166
case M32R_OPERAND_SR :
1167
fields->f_r2 = value;
1169
case M32R_OPERAND_SRC1 :
1170
fields->f_r1 = value;
1172
case M32R_OPERAND_SRC2 :
1173
fields->f_r2 = value;
1175
case M32R_OPERAND_UIMM16 :
1176
fields->f_uimm16 = value;
1178
case M32R_OPERAND_UIMM24 :
1179
fields->f_uimm24 = value;
1181
case M32R_OPERAND_UIMM3 :
1182
fields->f_uimm3 = value;
1184
case M32R_OPERAND_UIMM4 :
1185
fields->f_uimm4 = value;
1187
case M32R_OPERAND_UIMM5 :
1188
fields->f_uimm5 = value;
1190
case M32R_OPERAND_UIMM8 :
1191
fields->f_uimm8 = value;
1193
case M32R_OPERAND_ULO16 :
1194
fields->f_uimm16 = value;
1198
/* xgettext:c-format */
1199
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1205
/* Function to call before using the instruction builder tables. */
1208
m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
1210
cd->insert_handlers = & m32r_cgen_insert_handlers[0];
1211
cd->extract_handlers = & m32r_cgen_extract_handlers[0];
1213
cd->insert_operand = m32r_cgen_insert_operand;
1214
cd->extract_operand = m32r_cgen_extract_operand;
1216
cd->get_int_operand = m32r_cgen_get_int_operand;
1217
cd->set_int_operand = m32r_cgen_set_int_operand;
1218
cd->get_vma_operand = m32r_cgen_get_vma_operand;
1219
cd->set_vma_operand = m32r_cgen_set_vma_operand;