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/* tc-d30v.c -- Assembler code for the Mitsubishi D30V
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Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008,
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2009, 2010 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#include "safe-ctype.h"
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#include "opcode/d30v.h"
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#include "dwarf2dbg.h"
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char *md_shortopts = "OnNcC";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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#define NOP_MULTIPLY 1
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static int warn_nops = 0;
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static int Optimizing = 0;
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static int warn_register_name_conflicts = 1;
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typedef enum _exec_type
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EXEC_UNKNOWN, /* No order specified. */
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EXEC_PARALLEL, /* Done in parallel (FM=00). */
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EXEC_SEQ, /* Sequential (FM=01). */
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EXEC_REVSEQ /* Reverse sequential (FM=10). */
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#define MAX_INSN_FIXUPS 5
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bfd_reloc_code_real_type reloc;
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typedef struct _fixups
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struct d30v_fixup fix[MAX_INSN_FIXUPS];
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static Fixups FixUps[2];
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static Fixups *fixups;
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/* Whether current and previous instruction are word multiply insns. */
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static int cur_mul32_p = 0;
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static int prev_mul32_p = 0;
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/* The flag_explicitly_parallel is true iff the instruction being assembled
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has been explicitly written as a parallel short-instruction pair by the
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human programmer. It is used in parallel_ok () to distinguish between
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those dangerous parallelizations attempted by the human, which are to be
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allowed, and those attempted by the assembler, which are not. It is set
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from md_assemble (). */
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static int flag_explicitly_parallel = 0;
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static int flag_xp_state = 0;
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/* Whether current and previous left sub-instruction disables
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execution of right sub-instruction. */
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static int cur_left_kills_right_p = 0;
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static int prev_left_kills_right_p = 0;
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/* The known current alignment of the current section. */
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static int d30v_current_align;
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static segT d30v_current_align_seg;
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/* The last seen label in the current section. This is used to auto-align
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labels preceding instructions. */
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static symbolS *d30v_last_label;
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#define NOP_LEFT ((long long) NOP << 32)
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#define NOP_RIGHT ((long long) NOP)
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#define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
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struct option md_longopts[] =
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{NULL, no_argument, NULL, 0}
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size_t md_longopts_size = sizeof (md_longopts);
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/* Opcode hash table. */
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static struct hash_control *d30v_hash;
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/* Do a binary search of the pre_defined_registers array to see if
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NAME is a valid regiter name. Return the register number from the
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array on success, or -1 on failure. */
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reg_name_search (char *name)
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int middle, low, high;
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high = reg_name_cnt () - 1;
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middle = (low + high) / 2;
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cmp = strcasecmp (name, pre_defined_registers[middle].name);
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if (symbol_find (name) != NULL)
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if (warn_register_name_conflicts)
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as_warn (_("Register name %s conflicts with symbol of the same name"),
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return pre_defined_registers[middle].value;
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/* Check the string at input_line_pointer to see if it is a valid
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register_name (expressionS *expressionP)
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char c, *p = input_line_pointer;
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while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
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/* Look to see if it's in the register table. */
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reg_number = reg_name_search (input_line_pointer);
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expressionP->X_op = O_register;
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/* Temporarily store a pointer to the string here. */
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expressionP->X_op_symbol = (symbolS *) input_line_pointer;
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expressionP->X_add_number = reg_number;
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input_line_pointer = p;
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check_range (unsigned long num, int bits, int flags)
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/* Don't bother checking 32-bit values. */
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if (sizeof (unsigned long) * CHAR_BIT == 32)
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/* We don't record signed or unsigned for 32-bit quantities.
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min = -((unsigned long) 1 << (bits - 1));
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max = ((unsigned long) 1 << bits) - 1;
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return (long) num < min || (long) num > max;
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if (flags & OPERAND_SHIFT)
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/* We know that all shifts are right by three bits. */
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if (flags & OPERAND_SIGNED)
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unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1;
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num = (num ^ sign_bit) - sign_bit;
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if (flags & OPERAND_SIGNED)
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max = ((unsigned long) 1 << (bits - 1)) - 1;
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min = - ((unsigned long) 1 << (bits - 1));
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return (long) num > max || (long) num < min;
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max = ((unsigned long) 1 << bits) - 1;
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return num > (unsigned long) max;
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md_show_usage (FILE *stream)
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fprintf (stream, _("\nD30V options:\n\
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-O Make adjacent short instructions parallel if possible.\n\
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-n Warn about all NOPs inserted by the assembler.\n\
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-N Warn about NOPs inserted after word multiplies.\n\
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-c Warn about symbols whoes names match register names.\n\
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-C Opposite of -C. -c is the default.\n"));
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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/* Optimize. Will attempt to parallelize operations. */
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/* Warn about all NOPS that the assembler inserts. */
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/* Warn about the NOPS that the assembler inserts because of the
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warn_nops = NOP_MULTIPLY;
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warn_register_name_conflicts = 1;
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warn_register_name_conflicts = 0;
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md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
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md_atof (int type, char *litP, int *sizeP)
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return ieee_md_atof (type, litP, sizeP, TRUE);
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md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
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asection *sec ATTRIBUTE_UNUSED,
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fragS *fragP ATTRIBUTE_UNUSED)
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md_section_align (asection *seg, valueT addr)
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int align = bfd_get_section_alignment (stdoutput, seg);
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return ((addr + (1 << align) - 1) & (-1 << align));
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struct d30v_opcode *opcode;
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d30v_hash = hash_new ();
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/* Insert opcode names into a hash table. */
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for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++)
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hash_insert (d30v_hash, opcode->name, (char *) opcode);
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FixUps[0].next = &FixUps[1];
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FixUps[1].next = &FixUps[0];
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d30v_current_align_seg = now_seg;
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/* Remove the postincrement or postdecrement operator ( '+' or '-' )
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from an expression. */
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while (*p != '-' && *p != '+')
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if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',')
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static bfd_reloc_code_real_type
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get_reloc (const struct d30v_operand *op, int rel_flag)
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if (op->flags & OPERAND_SHIFT)
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return BFD_RELOC_D30V_9_PCREL;
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return BFD_RELOC_D30V_6;
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if (!(op->flags & OPERAND_SHIFT))
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as_warn (_("unexpected 12-bit reloc type"));
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if (rel_flag == RELOC_PCREL)
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return BFD_RELOC_D30V_15_PCREL;
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return BFD_RELOC_D30V_15;
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if (!(op->flags & OPERAND_SHIFT))
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as_warn (_("unexpected 18-bit reloc type"));
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if (rel_flag == RELOC_PCREL)
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return BFD_RELOC_D30V_21_PCREL;
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return BFD_RELOC_D30V_21;
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if (rel_flag == RELOC_PCREL)
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return BFD_RELOC_D30V_32_PCREL;
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return BFD_RELOC_D30V_32;
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/* Parse a string of operands and return an array of expressions. */
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get_operands (expressionS exp[], int cmp_hack)
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char *p = input_line_pointer;
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exp[numops].X_op = O_absent;
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exp[numops++].X_add_number = cmp_hack - 1;
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while (*p == ' ' || *p == '\t' || *p == ',')
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if (*p == 0 || *p == '\n' || *p == '\r')
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exp[numops].X_op = O_absent;
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exp[numops].X_add_number = OPERAND_ATPAR;
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exp[numops].X_add_number = OPERAND_ATMINUS;
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exp[numops].X_add_number = OPERAND_ATSIGN;
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/* Just skip the trailing paren. */
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input_line_pointer = p;
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/* Check to see if it might be a register name. */
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if (!register_name (&exp[numops]))
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/* Parse as an expression. */
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expression (&exp[numops]);
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if (exp[numops].X_op == O_illegal)
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as_bad (_("illegal operand"));
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else if (exp[numops].X_op == O_absent)
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as_bad (_("missing operand"));
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p = input_line_pointer;
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/* Postdecrement mode. */
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exp[numops].X_op = O_absent;
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exp[numops++].X_add_number = OPERAND_MINUS;
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/* Postincrement mode. */
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exp[numops].X_op = O_absent;
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exp[numops++].X_add_number = OPERAND_PLUS;
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exp[numops].X_op = 0;
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/* Generate the instruction.
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It does everything but write the FM bits. */
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build_insn (struct d30v_insn *opcode, expressionS *opers)
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int i, bits, shift, flags;
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unsigned long number, id = 0;
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struct d30v_opcode *op = opcode->op;
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struct d30v_format *form = opcode->form;
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opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
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for (i = 0; form->operands[i]; i++)
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flags = d30v_operand_table[form->operands[i]].flags;
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/* Must be a register or number. */
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if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM)
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&& !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
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bits = d30v_operand_table[form->operands[i]].bits;
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if (flags & OPERAND_SHIFT)
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shift = 12 - d30v_operand_table[form->operands[i]].position;
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if (opers[i].X_op != O_symbol)
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number = opers[i].X_add_number;
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if (flags & OPERAND_REG)
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/* Check for mvfsys or mvtsys control registers. */
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if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
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id = (number & 0x7f) - MAX_CONTROL_REG;
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else if (number & OPERAND_FLAG)
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/* NUMBER is a flag register. */
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else if (flags & OPERAND_SPECIAL)
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if (opers[i].X_op != O_register && opers[i].X_op != O_constant
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&& !(flags & OPERAND_NAME))
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/* Now create a fixup. */
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if (fixups->fc >= MAX_INSN_FIXUPS)
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as_fatal (_("too many fixups"));
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fixups->fix[fixups->fc].reloc =
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get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag);
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fixups->fix[fixups->fc].size = 4;
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fixups->fix[fixups->fc].exp = opers[i];
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fixups->fix[fixups->fc].operand = form->operands[i];
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if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
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fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
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fixups->fix[fixups->fc].pcrel = op->reloc_flag;
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/* Truncate to the proper number of bits. */
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if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
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as_bad (_("operand out of range: %ld"), number);
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number &= 0x7FFFFFFF >> (31 - bits);
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if (flags & OPERAND_SHIFT)
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/* It's a LONG instruction. */
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insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */
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insn <<= 32; /* Shift the first word over. */
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insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */
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insn |= number & 0x0003FFFF; /* Bottom 18 bits. */
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insn |= number << shift;
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d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */
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long long value, /* The value of the bits. */
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int n) /* Number of bytes in the output. */
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buf[n] = value & 0xff;
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/* Write out a long form instruction. */
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write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
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char *f = frag_more (8);
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dwarf2_emit_insn (8);
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d30v_number_to_chars (f, insn, 8);
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for (i = 0; i < fx->fc; i++)
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if (fx->fix[i].reloc)
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where = f - frag_now->fr_literal;
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fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
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fx->fix[i].pcrel, fx->fix[i].reloc);
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/* Write out a short form instruction by itself. */
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write_1_short (struct d30v_insn *opcode,
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char *f = frag_more (8);
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dwarf2_emit_insn (8);
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if (warn_nops == NOP_ALL)
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as_warn (_("%s NOP inserted"), use_sequential ?
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_("sequential") : _("parallel"));
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/* The other container needs to be NOP. */
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/* Use a sequential NOP rather than a parallel one,
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as the current instruction is a FLAG_MUL32 type one
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and the next instruction is a load. */
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/* According to 4.3.1: for FM=01, sub-instructions performed
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only by IU cannot be encoded in L-container. */
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if (opcode->op->unit == IU)
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/* Right then left. */
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insn |= FM10 | NOP_LEFT;
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/* Left then right. */
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insn = FM01 | (insn << 32) | NOP_RIGHT;
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/* According to 4.3.1: for FM=00, sub-instructions performed
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only by IU cannot be encoded in L-container. */
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if (opcode->op->unit == IU)
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/* Right container. */
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insn |= FM00 | NOP_LEFT;
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/* Left container. */
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insn = FM00 | (insn << 32) | NOP_RIGHT;
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d30v_number_to_chars (f, insn, 8);
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for (i = 0; i < fx->fc; i++)
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if (fx->fix[i].reloc)
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where = f - frag_now->fr_literal;
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fix_new_exp (frag_now,
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/* Check 2 instructions and determine if they can be safely
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executed in parallel. Return 1 if they can be. */
680
parallel_ok (struct d30v_insn *op1,
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struct d30v_insn *op2,
684
exec_type_enum exec_type)
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int i, j, shift, regno, bits, ecc;
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unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
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unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
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struct d30v_format *f;
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struct d30v_opcode *op;
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/* Section 4.3: Both instructions must not be IU or MU only. */
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if ((op1->op->unit == IU && op2->op->unit == IU)
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|| (op1->op->unit == MU && op2->op->unit == MU))
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/* First instruction must not be a jump to safely optimize, unless this
698
is an explicit parallel operation. */
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if (exec_type != EXEC_PARALLEL
700
&& (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
703
/* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
704
then it is safe to allow the two to be done as parallel ops, since only
705
one will ever be executed at a time. */
706
if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
707
|| (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
708
|| (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
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|| (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
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[2] a0, a1, flag registers. */
715
for (j = 0; j < 2; j++)
733
mod_reg[j][0] = mod_reg[j][1] = 0;
734
used_reg[j][0] = used_reg[j][1] = 0;
736
if (flag_explicitly_parallel)
738
/* For human specified parallel instructions we have been asked
739
to ignore the possibility that both instructions could modify
740
bits in the PSW, so we initialise the mod & used arrays to 0.
741
We have been asked, however, to refuse to allow parallel
742
instructions which explicitly set the same flag register,
743
eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
744
for the use of a flag register and set a bit in the mod or used
745
array appropriately. */
751
mod_reg[j][2] = (op->flags_set & FLAG_ALL);
752
used_reg[j][2] = (op->flags_used & FLAG_ALL);
755
/* BSR/JSR always sets R62. */
756
if (op->flags_used & FLAG_JSR)
757
mod_reg[j][1] = (1L << (62 - 32));
759
/* Conditional execution affects the flags_used. */
764
used_reg[j][2] |= flag_reg[j] = FLAG_0;
769
used_reg[j][2] |= flag_reg[j] = FLAG_1;
774
used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
778
for (i = 0; f->operands[i]; i++)
780
flags = d30v_operand_table[f->operands[i]].flags;
781
shift = 12 - d30v_operand_table[f->operands[i]].position;
782
bits = d30v_operand_table[f->operands[i]].bits;
786
mask = 0x7FFFFFFF >> (31 - bits);
788
if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
790
/* This is a post-increment or post-decrement.
791
The previous register needs to be marked as modified. */
792
shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
793
regno = (ins >> shift) & 0x3f;
795
mod_reg[j][1] |= 1L << (regno - 32);
797
mod_reg[j][0] |= 1L << regno;
799
else if (flags & OPERAND_REG)
801
regno = (ins >> shift) & mask;
802
/* The memory write functions don't have a destination
804
if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
806
/* MODIFIED registers and flags. */
807
if (flags & OPERAND_ACC)
810
mod_reg[j][2] |= FLAG_A0;
812
mod_reg[j][2] |= FLAG_A1;
816
else if (flags & OPERAND_FLAG)
817
mod_reg[j][2] |= 1L << regno;
818
else if (!(flags & OPERAND_CONTROL))
822
/* Need to check if there are two destination
823
registers, for example ld2w. */
824
if (flags & OPERAND_2REG)
829
for (r = regno; r <= regno + z; r++)
832
mod_reg[j][1] |= 1L << (r - 32);
834
mod_reg[j][0] |= 1L << r;
840
/* USED, but not modified registers and flags. */
841
if (flags & OPERAND_ACC)
844
used_reg[j][2] |= FLAG_A0;
846
used_reg[j][2] |= FLAG_A1;
850
else if (flags & OPERAND_FLAG)
851
used_reg[j][2] |= 1L << regno;
852
else if (!(flags & OPERAND_CONTROL))
856
/* Need to check if there are two source
857
registers, for example st2w. */
858
if (flags & OPERAND_2REG)
863
for (r = regno; r <= regno + z; r++)
866
used_reg[j][1] |= 1L << (r - 32);
868
used_reg[j][0] |= 1L << r;
876
flags_set1 = op1->op->flags_set;
877
flags_set2 = op2->op->flags_set;
878
flags_used1 = op1->op->flags_used;
879
flags_used2 = op2->op->flags_used;
881
/* Check for illegal combinations with ADDppp/SUBppp. */
882
if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
883
&& (flags_used2 & FLAG_ADDSUBppp) != 0)
884
|| ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
885
&& (flags_used1 & FLAG_ADDSUBppp) != 0))
888
/* Load instruction combined with half-word multiply is illegal. */
889
if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
890
|| ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
893
/* Specifically allow add || add by removing carry, overflow bits dependency.
894
This is safe, even if an addc follows since the IU takes the argument in
895
the right container, and it writes its results last.
896
However, don't paralellize add followed by addc or sub followed by
898
if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
899
&& (used_reg[0][2] & ~flag_reg[0]) == 0
900
&& (used_reg[1][2] & ~flag_reg[1]) == 0
901
&& op1->op->unit == EITHER && op2->op->unit == EITHER)
903
mod_reg[0][2] = mod_reg[1][2] = 0;
906
for (j = 0; j < 3; j++)
908
/* If the second instruction depends on the first, we obviously
909
cannot parallelize. Note, the mod flag implies use, so
910
check that as well. */
911
/* If flag_explicitly_parallel is set, then the case of the
912
second instruction using a register the first instruction
913
modifies is assumed to be okay; we trust the human. We
914
don't trust the human if both instructions modify the same
915
register but we do trust the human if they modify the same
917
/* We have now been requested not to trust the human if the
918
instructions modify the same flag registers either. */
919
if (flag_explicitly_parallel)
921
if ((mod_reg[0][j] & mod_reg[1][j]) != 0)
925
if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
932
/* Write out a short form instruction if possible.
933
Return number of instructions not written out. */
936
write_2_short (struct d30v_insn *opcode1,
938
struct d30v_insn *opcode2,
940
exec_type_enum exec_type,
943
long long insn = NOP2;
947
if (exec_type == EXEC_SEQ
948
&& (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
949
&& ((opcode1->op->flags_used & FLAG_DELAY) == 0)
950
&& ((opcode1->ecc == ECC_AL) || ! Optimizing))
952
/* Unconditional, non-delayed branches kill instructions in
953
the right bin. Conditional branches don't always but if
954
we are not optimizing, then we have been asked to produce
955
an error about such constructs. For the purposes of this
956
test, subroutine calls are considered to be branches. */
957
write_1_short (opcode1, insn1, fx->next, FALSE);
961
/* Note: we do not have to worry about subroutine calls occurring
962
in the right hand container. The return address is always
963
aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
966
case EXEC_UNKNOWN: /* Order not specified. */
968
&& parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
969
&& ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU
970
|| opcode1->op->unit == MU)
972
( opcode2->op->unit == EITHER_BUT_PREFER_MU
973
|| opcode2->op->unit == MU)))
976
exec_type = EXEC_PARALLEL;
978
if (opcode1->op->unit == IU
979
|| opcode2->op->unit == MU
980
|| opcode2->op->unit == EITHER_BUT_PREFER_MU)
981
insn = FM00 | (insn2 << 32) | insn1;
984
insn = FM00 | (insn1 << 32) | insn2;
988
else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
989
&& ((opcode1->op->flags_used & FLAG_DELAY) == 0))
990
|| opcode1->op->flags_used & FLAG_RP)
992
/* We must emit (non-delayed) branch type instructions
993
on their own with nothing in the right container. */
994
/* We must treat repeat instructions likewise, since the
995
following instruction has to be separate from the repeat
996
in order to be repeated. */
997
write_1_short (opcode1, insn1, fx->next, FALSE);
1000
else if (prev_left_kills_right_p)
1002
/* The left instruction kils the right slot, so we
1003
must leave it empty. */
1004
write_1_short (opcode1, insn1, fx->next, FALSE);
1007
else if (opcode1->op->unit == IU)
1009
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1011
/* Case 103810 is a request from Mitsubishi that opcodes
1012
with EITHER_BUT_PREFER_MU should not be executed in
1013
reverse sequential order. */
1014
write_1_short (opcode1, insn1, fx->next, FALSE);
1018
/* Reverse sequential. */
1019
insn = FM10 | (insn2 << 32) | insn1;
1020
exec_type = EXEC_REVSEQ;
1025
insn = FM01 | (insn1 << 32) | insn2;
1027
exec_type = EXEC_SEQ;
1031
case EXEC_PARALLEL: /* Parallel. */
1032
flag_explicitly_parallel = flag_xp_state;
1033
if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
1034
as_bad (_("Instructions may not be executed in parallel"));
1035
else if (opcode1->op->unit == IU)
1037
if (opcode2->op->unit == IU)
1038
as_bad (_("Two IU instructions may not be executed in parallel"));
1039
as_warn (_("Swapping instruction order"));
1040
insn = FM00 | (insn2 << 32) | insn1;
1042
else if (opcode2->op->unit == MU)
1044
if (opcode1->op->unit == MU)
1045
as_bad (_("Two MU instructions may not be executed in parallel"));
1046
else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
1047
as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
1048
as_warn (_("Swapping instruction order"));
1049
insn = FM00 | (insn2 << 32) | insn1;
1053
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1054
as_warn (_("Executing %s in IU may not work in parallel execution"),
1057
insn = FM00 | (insn1 << 32) | insn2;
1060
flag_explicitly_parallel = 0;
1063
case EXEC_SEQ: /* Sequential. */
1064
if (opcode1->op->unit == IU)
1065
as_bad (_("IU instruction may not be in the left container"));
1066
if (prev_left_kills_right_p)
1067
as_bad (_("special left instruction `%s' kills instruction "
1068
"`%s' in right container"),
1069
opcode1->op->name, opcode2->op->name);
1070
insn = FM01 | (insn1 << 32) | insn2;
1074
case EXEC_REVSEQ: /* Reverse sequential. */
1075
if (opcode2->op->unit == MU)
1076
as_bad (_("MU instruction may not be in the right container"));
1077
if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
1078
as_warn (_("Executing %s in reverse serial with %s may not work"),
1079
opcode1->op->name, opcode2->op->name);
1080
else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1081
as_warn (_("Executing %s in IU in reverse serial may not work"),
1083
insn = FM10 | (insn1 << 32) | insn2;
1088
as_fatal (_("unknown execution type passed to write_2_short()"));
1092
dwarf2_emit_insn (8);
1093
d30v_number_to_chars (f, insn, 8);
1095
/* If the previous instruction was a 32-bit multiply but it is put into a
1096
parallel container, mark the current instruction as being a 32-bit
1098
if (prev_mul32_p && exec_type == EXEC_PARALLEL)
1101
for (j = 0; j < 2; j++)
1103
for (i = 0; i < fx->fc; i++)
1105
if (fx->fix[i].reloc)
1107
where = (f - frag_now->fr_literal) + 4 * j;
1109
fix_new_exp (frag_now,
1125
/* Get a pointer to an entry in the format table.
1126
It must look at all formats for an opcode and use the operands
1127
to choose the correct one. Return NULL on error. */
1129
static struct d30v_format *
1130
find_format (struct d30v_opcode *opcode,
1131
expressionS myops[],
1135
int match, opcode_index, i = 0, j, k;
1136
struct d30v_format *fm;
1141
/* Get all the operands and save them as expressions. */
1142
get_operands (myops, cmp_hack);
1144
while ((opcode_index = opcode->format[i++]) != 0)
1146
if (fsize == FORCE_SHORT && opcode_index >= LONG)
1149
if (fsize == FORCE_LONG && opcode_index < LONG)
1152
fm = (struct d30v_format *) &d30v_format_table[opcode_index];
1154
while (fm->form == opcode_index)
1157
/* Now check the operands for compatibility. */
1158
for (j = 0; match && fm->operands[j]; j++)
1160
int flags = d30v_operand_table[fm->operands[j]].flags;
1161
int bits = d30v_operand_table[fm->operands[j]].bits;
1162
int X_op = myops[j].X_op;
1163
int num = myops[j].X_add_number;
1165
if (flags & OPERAND_SPECIAL)
1167
else if (X_op == O_illegal)
1169
else if (flags & OPERAND_REG)
1171
if (X_op != O_register
1172
|| ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
1173
|| (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
1174
|| ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
1175
|| (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
1176
|| ((flags & OPERAND_CONTROL)
1177
&& !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
1180
else if (((flags & OPERAND_MINUS)
1181
&& (X_op != O_absent || num != OPERAND_MINUS))
1182
|| ((flags & OPERAND_PLUS)
1183
&& (X_op != O_absent || num != OPERAND_PLUS))
1184
|| ((flags & OPERAND_ATMINUS)
1185
&& (X_op != O_absent || num != OPERAND_ATMINUS))
1186
|| ((flags & OPERAND_ATPAR)
1187
&& (X_op != O_absent || num != OPERAND_ATPAR))
1188
|| ((flags & OPERAND_ATSIGN)
1189
&& (X_op != O_absent || num != OPERAND_ATSIGN)))
1191
else if (flags & OPERAND_NUM)
1193
/* A number can be a constant or symbol expression. */
1195
/* If we have found a register name, but that name
1196
also matches a symbol, then re-parse the name as
1198
if (X_op == O_register
1199
&& symbol_find ((char *) myops[j].X_op_symbol))
1201
input_line_pointer = (char *) myops[j].X_op_symbol;
1202
expression (&myops[j]);
1205
/* Turn an expression into a symbol for later resolution. */
1206
if (X_op != O_absent && X_op != O_constant
1207
&& X_op != O_symbol && X_op != O_register
1210
symbolS *sym = make_expr_symbol (&myops[j]);
1211
myops[j].X_op = X_op = O_symbol;
1212
myops[j].X_add_symbol = sym;
1213
myops[j].X_add_number = num = 0;
1216
if (fm->form >= LONG)
1218
/* If we're testing for a LONG format, either fits. */
1219
if (X_op != O_constant && X_op != O_symbol)
1222
else if (fm->form < LONG
1223
&& ((fsize == FORCE_SHORT && X_op == O_symbol)
1224
|| (fm->form == SHORT_D2 && j == 0)))
1227
/* This is the tricky part. Will the constant or symbol
1228
fit into the space in the current format? */
1229
else if (X_op == O_constant)
1231
if (check_range (num, bits, flags))
1234
else if (X_op == O_symbol
1235
&& S_IS_DEFINED (myops[j].X_add_symbol)
1236
&& S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
1237
&& opcode->reloc_flag == RELOC_PCREL)
1239
/* If the symbol is defined, see if the value will fit
1240
into the form we're considering. */
1244
/* Calculate the current address by running through the
1245
previous frags and adding our current offset. */
1247
for (f = frchain_now->frch_root; f; f = f->fr_next)
1248
value += f->fr_fix + f->fr_offset;
1249
value = (S_GET_VALUE (myops[j].X_add_symbol) - value
1250
- (obstack_next_free (&frchain_now->frch_obstack)
1251
- frag_now->fr_literal));
1252
if (check_range (value, bits, flags))
1259
/* We're only done if the operands matched so far AND there
1260
are no more to check. */
1261
if (match && myops[j].X_op == 0)
1263
/* Final check - issue a warning if an odd numbered register
1264
is used as the first register in an instruction that reads
1265
or writes 2 registers. */
1267
for (j = 0; fm->operands[j]; j++)
1268
if (myops[j].X_op == O_register
1269
&& (myops[j].X_add_number & 1)
1270
&& (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
1271
as_warn (_("Odd numbered register used as target of multi-register instruction"));
1275
fm = (struct d30v_format *) &d30v_format_table[++k];
1281
/* Assemble a single instruction and return an opcode.
1282
Return -1 (an invalid opcode) on error. */
1284
#define NAME_BUF_LEN 20
1287
do_assemble (char *str,
1288
struct d30v_insn *opcode,
1295
char name[NAME_BUF_LEN];
1298
int fsize = (shortp ? FORCE_SHORT : 0);
1299
expressionS myops[6];
1302
/* Drop leading whitespace. */
1306
/* Find the opcode end. */
1307
for (op_start = op_end = str;
1309
&& nlen < (NAME_BUF_LEN - 1)
1311
&& !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
1314
name[nlen] = TOLOWER (op_start[nlen]);
1323
/* If there is an execution condition code, handle it. */
1327
while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
1333
strncpy (tmp, op_end + 1, 2);
1335
as_bad (_("unknown condition code: %s"), tmp);
1342
opcode->ecc = ECC_AL;
1344
/* CMP and CMPU change their name based on condition codes. */
1345
if (!strncmp (name, "cmp", 3))
1348
char **d30v_str = (char **) d30v_cc_names;
1355
for (i = 1; *d30v_str && strncmp (*d30v_str, &name[p], 2); i++, d30v_str++)
1358
/* cmpu only supports some condition codes. */
1364
as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
1371
as_bad (_("unknown condition code: %s"), &name[p]);
1380
/* Need to look for .s or .l. */
1381
if (name[nlen - 2] == '.')
1383
switch (name[nlen - 1])
1386
fsize = FORCE_SHORT;
1395
/* Find the first opcode with the proper name. */
1396
opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
1397
if (opcode->op == NULL)
1399
as_bad (_("unknown opcode: %s"), name);
1403
save = input_line_pointer;
1404
input_line_pointer = op_end;
1405
while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
1408
if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
1410
as_bad (_("operands for opcode `%s' do not match any valid format"),
1415
input_line_pointer = save;
1417
insn = build_insn (opcode, myops);
1419
/* Propagate multiply status. */
1422
if (is_parallel && prev_mul32_p)
1426
prev_mul32_p = cur_mul32_p;
1427
cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
1431
/* Propagate left_kills_right status. */
1434
prev_left_kills_right_p = cur_left_kills_right_p;
1436
if (opcode->op->flags_set & FLAG_LKR)
1438
cur_left_kills_right_p = 1;
1440
if (strcmp (opcode->op->name, "mvtsys") == 0)
1442
/* Left kills right for only mvtsys only for
1443
PSW/PSWH/PSWL/flags target. */
1444
if ((myops[0].X_op == O_register) &&
1445
((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
1446
(myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
1447
(myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
1448
(myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
1449
(myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
1450
(myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
1451
(myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
1452
(myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
1453
(myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
1454
(myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
1455
(myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
1457
cur_left_kills_right_p = 1;
1461
/* Other mvtsys target registers don't kill right
1463
cur_left_kills_right_p = 0;
1468
cur_left_kills_right_p = 0;
1474
/* Called internally to handle all alignment needs. This takes care
1475
of eliding calls to frag_align if'n the cached current alignment
1476
says we've already got it, as well as taking care of the auto-aligning
1480
d30v_align (int n, char *pfill, symbolS *label)
1482
/* The front end is prone to changing segments out from under us
1483
temporarily when -g is in effect. */
1484
int switched_seg_p = (d30v_current_align_seg != now_seg);
1486
/* Do not assume that if 'd30v_current_align >= n' and
1487
'! switched_seg_p' that it is safe to avoid performing
1488
this alignment request. The alignment of the current frag
1489
can be changed under our feet, for example by a .ascii
1490
directive in the source code. cf testsuite/gas/d30v/reloc.s */
1491
d30v_cleanup (FALSE);
1496
&& (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
1498
static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
1500
/* First, make sure we're on a four-byte boundary, in case
1501
someone has been putting .byte values the text section. */
1502
if (d30v_current_align < 2 || switched_seg_p)
1503
frag_align (2, 0, 0);
1504
frag_align_pattern (n, nop, sizeof nop, 0);
1507
frag_align (n, 0, 0);
1510
frag_align (n, *pfill, 0);
1512
if (!switched_seg_p)
1513
d30v_current_align = n;
1518
int label_seen = FALSE;
1519
struct frag *old_frag;
1523
gas_assert (S_GET_SEGMENT (label) == now_seg);
1525
old_frag = symbol_get_frag (label);
1526
old_value = S_GET_VALUE (label);
1527
new_value = (valueT) frag_now_fix ();
1529
/* It is possible to have more than one label at a particular
1530
address, especially if debugging is enabled, so we must
1531
take care to adjust all the labels at this address in this
1532
fragment. To save time we search from the end of the symbol
1533
list, backwards, since the symbols we are interested in are
1534
almost certainly the ones that were most recently added.
1535
Also to save time we stop searching once we have seen at least
1536
one matching label, and we encounter a label that is no longer
1537
in the target fragment. Note, this search is guaranteed to
1538
find at least one match when sym == label, so no special case
1539
code is necessary. */
1540
for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
1542
if (symbol_get_frag (sym) == old_frag
1543
&& S_GET_VALUE (sym) == old_value)
1546
symbol_set_frag (sym, frag_now);
1547
S_SET_VALUE (sym, new_value);
1549
else if (label_seen && symbol_get_frag (sym) != old_frag)
1554
record_alignment (now_seg, n);
1557
/* This is the main entry point for the machine-dependent assembler.
1558
STR points to a machine-dependent instruction. This function is
1559
supposed to emit the frags/bytes it assembles to. For the D30V, it
1560
mostly handles the special VLIW parsing and packing and leaves the
1561
difficult stuff to do_assemble (). */
1563
static long long prev_insn = -1;
1564
static struct d30v_insn prev_opcode;
1565
static subsegT prev_subseg;
1566
static segT prev_seg = 0;
1569
md_assemble (char *str)
1571
struct d30v_insn opcode;
1573
/* Execution type; parallel, etc. */
1574
exec_type_enum extype = EXEC_UNKNOWN;
1575
/* Saved extype. Used for multiline instructions. */
1576
static exec_type_enum etype = EXEC_UNKNOWN;
1579
if ((prev_insn != -1) && prev_seg
1580
&& ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1581
d30v_cleanup (FALSE);
1583
if (d30v_current_align < 3)
1584
d30v_align (3, NULL, d30v_last_label);
1585
else if (d30v_current_align > 3)
1586
d30v_current_align = 3;
1587
d30v_last_label = NULL;
1589
flag_explicitly_parallel = 0;
1591
if (etype == EXEC_UNKNOWN)
1593
/* Look for the special multiple instruction separators. */
1594
str2 = strstr (str, "||");
1597
extype = EXEC_PARALLEL;
1602
str2 = strstr (str, "->");
1607
str2 = strstr (str, "<-");
1609
extype = EXEC_REVSEQ;
1613
/* STR2 points to the separator, if one. */
1618
/* If two instructions are present and we already have one saved,
1619
then first write it out. */
1620
d30v_cleanup (FALSE);
1622
/* Assemble first instruction and save it. */
1623
prev_insn = do_assemble (str, &prev_opcode, 1, 0);
1624
if (prev_insn == -1)
1625
as_bad (_("Cannot assemble instruction"));
1626
if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
1627
as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1628
fixups = fixups->next;
1631
prev_subseg = now_subseg;
1635
insn = do_assemble (str, &opcode,
1636
(extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
1637
extype == EXEC_PARALLEL);
1640
if (extype != EXEC_UNKNOWN)
1642
as_bad (_("Cannot assemble instruction"));
1646
if (etype != EXEC_UNKNOWN)
1649
etype = EXEC_UNKNOWN;
1652
/* Word multiply instructions must not be followed by either a load or a
1653
16-bit multiply instruction in the next cycle. */
1654
if ( (extype != EXEC_REVSEQ)
1656
&& (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1658
/* However, load and multiply should able to be combined in a parallel
1659
operation, so check for that first. */
1661
&& (opcode.op->flags_used & FLAG_MEM)
1662
&& opcode.form->form < LONG
1663
&& (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
1664
&& parallel_ok (&prev_opcode, (long) prev_insn,
1665
&opcode, (long) insn, extype)
1666
&& write_2_short (&prev_opcode, (long) prev_insn,
1667
&opcode, (long) insn, extype, fixups) == 0)
1669
/* No instructions saved. */
1675
/* Can't parallelize, flush previous instruction and emit a
1676
word of NOPS, unless the previous instruction is a NOP,
1677
in which case just flush it, as this will generate a word
1680
if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
1681
d30v_cleanup (FALSE);
1686
if (prev_insn != -1)
1687
d30v_cleanup (TRUE);
1691
dwarf2_emit_insn (8);
1692
d30v_number_to_chars (f, NOP2, 8);
1694
if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
1696
if (opcode.op->flags_used & FLAG_MEM)
1697
as_warn (_("word of NOPs added between word multiply and load"));
1699
as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1704
extype = EXEC_UNKNOWN;
1707
else if ( (extype == EXEC_REVSEQ)
1709
&& (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1711
/* Can't parallelize, flush current instruction and add a
1713
write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
1715
/* Make the previous instruction the current one. */
1716
extype = EXEC_UNKNOWN;
1719
now_subseg = prev_subseg;
1721
cur_mul32_p = prev_mul32_p;
1723
memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
1726
/* If this is a long instruction, write it and any previous short
1728
if (opcode.form->form >= LONG)
1730
if (extype != EXEC_UNKNOWN)
1731
as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1732
d30v_cleanup (FALSE);
1733
write_long (&opcode, insn, fixups);
1736
else if ((prev_insn != -1)
1738
(&prev_opcode, (long) prev_insn, &opcode,
1739
(long) insn, extype, fixups) == 0))
1741
/* No instructions saved. */
1746
if (extype != EXEC_UNKNOWN)
1747
as_bad (_("Unable to mix instructions as specified"));
1749
/* Save off last instruction so it may be packed on next pass. */
1750
memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
1753
prev_subseg = now_subseg;
1754
fixups = fixups->next;
1755
prev_mul32_p = cur_mul32_p;
1759
/* If while processing a fixup, a reloc really needs to be created,
1760
then it is done here. */
1763
tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1766
reloc = xmalloc (sizeof (arelent));
1767
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1768
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1769
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1770
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1771
if (reloc->howto == NULL)
1773
as_bad_where (fixp->fx_file, fixp->fx_line,
1774
_("reloc %d not supported by object file format"),
1775
(int) fixp->fx_r_type);
1784
md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1785
asection *seg ATTRIBUTE_UNUSED)
1792
md_pcrel_from_section (fixS *fixp, segT sec)
1794
if (fixp->fx_addsy != (symbolS *) NULL
1795
&& (!S_IS_DEFINED (fixp->fx_addsy)
1796
|| (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1798
return fixp->fx_frag->fr_address + fixp->fx_where;
1801
/* Called after the assembler has finished parsing the input file or
1802
after a label is defined. Because the D30V assembler sometimes
1803
saves short instructions to see if it can package them with the
1804
next instruction, there may be a short instruction that still needs
1808
d30v_cleanup (int use_sequential)
1813
if (prev_insn != -1)
1816
subseg = now_subseg;
1817
subseg_set (prev_seg, prev_subseg);
1818
write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
1820
subseg_set (seg, subseg);
1823
prev_mul32_p = FALSE;
1829
/* This function is called at the start of every line. It checks to
1830
see if the first character is a '.', which indicates the start of a
1831
pseudo-op. If it is, then write out any unwritten instructions. */
1834
d30v_start_line (void)
1836
char *c = input_line_pointer;
1838
while (ISSPACE (*c))
1842
d30v_cleanup (FALSE);
1846
check_size (long value, int bits, char *file, int line)
1855
max = (1 << (bits - 1)) - 1;
1858
as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
1861
/* d30v_frob_label() is called when after a label is recognized. */
1864
d30v_frob_label (symbolS *lab)
1866
/* Emit any pending instructions. */
1867
d30v_cleanup (FALSE);
1869
/* Update the label's address with the current output pointer. */
1870
symbol_set_frag (lab, frag_now);
1871
S_SET_VALUE (lab, (valueT) frag_now_fix ());
1873
/* Record this label for future adjustment after we find out what
1874
kind of data it references, and the required alignment therewith. */
1875
d30v_last_label = lab;
1877
dwarf2_emit_label (lab);
1880
/* Hook into cons for capturing alignment changes. */
1883
d30v_cons_align (int size)
1887
/* Don't specially align anything in debug sections. */
1888
if ((now_seg->flags & SEC_ALLOC) == 0
1889
|| strcmp (now_seg->name, ".eh_frame") == 0)
1893
while ((size >>= 1) != 0)
1896
if (d30v_current_align < log_size)
1897
d30v_align (log_size, (char *) NULL, NULL);
1898
else if (d30v_current_align > log_size)
1899
d30v_current_align = log_size;
1900
d30v_last_label = NULL;
1904
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1907
unsigned long insn, insn2;
1910
if (fixP->fx_addsy == (symbolS *) NULL)
1913
/* We don't support subtracting a symbol. */
1914
if (fixP->fx_subsy != (symbolS *) NULL)
1915
as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1917
/* Fetch the instruction, insert the fully resolved operand
1918
value, and stuff the instruction back again. */
1919
where = fixP->fx_frag->fr_literal + fixP->fx_where;
1920
insn = bfd_getb32 ((unsigned char *) where);
1922
switch (fixP->fx_r_type)
1924
case BFD_RELOC_8: /* Check for a bad .byte directive. */
1925
if (fixP->fx_addsy != NULL)
1926
as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1927
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1928
else if (((unsigned)value) > 0xff)
1929
as_bad (_("line %d: unable to place value %lx into a byte"),
1930
fixP->fx_line, value);
1932
*(unsigned char *) where = value;
1935
case BFD_RELOC_16: /* Check for a bad .short directive. */
1936
if (fixP->fx_addsy != NULL)
1937
as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1938
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1939
else if (((unsigned)value) > 0xffff)
1940
as_bad (_("line %d: unable to place value %lx into a short"),
1941
fixP->fx_line, value);
1943
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1946
case BFD_RELOC_64: /* Check for a bad .quad directive. */
1947
if (fixP->fx_addsy != NULL)
1948
as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1949
fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1952
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1953
bfd_putb32 (0, ((unsigned char *) where) + 4);
1957
case BFD_RELOC_D30V_6:
1958
check_size (value, 6, fixP->fx_file, fixP->fx_line);
1959
insn |= value & 0x3F;
1960
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1963
case BFD_RELOC_D30V_9_PCREL:
1964
if (fixP->fx_where & 0x7)
1969
fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
1971
check_size (value, 9, fixP->fx_file, fixP->fx_line);
1972
insn |= ((value >> 3) & 0x3F) << 12;
1973
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1976
case BFD_RELOC_D30V_15:
1977
check_size (value, 15, fixP->fx_file, fixP->fx_line);
1978
insn |= (value >> 3) & 0xFFF;
1979
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1982
case BFD_RELOC_D30V_15_PCREL:
1983
if (fixP->fx_where & 0x7)
1988
fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
1990
check_size (value, 15, fixP->fx_file, fixP->fx_line);
1991
insn |= (value >> 3) & 0xFFF;
1992
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1995
case BFD_RELOC_D30V_21:
1996
check_size (value, 21, fixP->fx_file, fixP->fx_line);
1997
insn |= (value >> 3) & 0x3FFFF;
1998
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2001
case BFD_RELOC_D30V_21_PCREL:
2002
if (fixP->fx_where & 0x7)
2007
fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
2009
check_size (value, 21, fixP->fx_file, fixP->fx_line);
2010
insn |= (value >> 3) & 0x3FFFF;
2011
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2014
case BFD_RELOC_D30V_32:
2015
insn2 = bfd_getb32 ((unsigned char *) where + 4);
2016
insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
2017
insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
2018
insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
2019
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2020
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
2023
case BFD_RELOC_D30V_32_PCREL:
2024
insn2 = bfd_getb32 ((unsigned char *) where + 4);
2025
insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
2026
insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
2027
insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
2028
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2029
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
2033
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
2037
as_bad (_("line %d: unknown relocation type: 0x%x"),
2038
fixP->fx_line, fixP->fx_r_type);
2042
/* Handle the .align pseudo-op. This aligns to a power of two. We
2043
hook here to latch the current alignment. */
2046
s_d30v_align (int ignore ATTRIBUTE_UNUSED)
2049
char fill, *pfill = NULL;
2050
long max_alignment = 15;
2052
align = get_absolute_expression ();
2053
if (align > max_alignment)
2055
align = max_alignment;
2056
as_warn (_("Alignment too large: %d assumed"), align);
2060
as_warn (_("Alignment negative: 0 assumed"));
2064
if (*input_line_pointer == ',')
2066
input_line_pointer++;
2067
fill = get_absolute_expression ();
2071
d30v_last_label = NULL;
2072
d30v_align (align, pfill, NULL);
2074
demand_empty_rest_of_line ();
2077
/* Handle the .text pseudo-op. This is like the usual one, but it
2078
clears the saved last label and resets known alignment. */
2085
d30v_last_label = NULL;
2086
d30v_current_align = 0;
2087
d30v_current_align_seg = now_seg;
2090
/* Handle the .data pseudo-op. This is like the usual one, but it
2091
clears the saved last label and resets known alignment. */
2097
d30v_last_label = NULL;
2098
d30v_current_align = 0;
2099
d30v_current_align_seg = now_seg;
2102
/* Handle the .section pseudo-op. This is like the usual one, but it
2103
clears the saved last label and resets known alignment. */
2106
s_d30v_section (int ignore)
2108
obj_elf_section (ignore);
2109
d30v_last_label = NULL;
2110
d30v_current_align = 0;
2111
d30v_current_align_seg = now_seg;
2114
/* The target specific pseudo-ops which we support. */
2115
const pseudo_typeS md_pseudo_table[] =
2117
{ "word", cons, 4 },
2118
{ "hword", cons, 2 },
2119
{ "align", s_d30v_align, 0 },
2120
{ "text", s_d30v_text, 0 },
2121
{ "data", s_d30v_data, 0 },
2122
{ "section", s_d30v_section, 0 },
2123
{ "section.s", s_d30v_section, 0 },
2124
{ "sect", s_d30v_section, 0 },
2125
{ "sect.s", s_d30v_section, 0 },