1
/* Disassembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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- the resultant file is machine generated, cgen-dis.in isn't
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
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2008, 2010 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
13
it under the terms of the GNU General Public License as published by
14
the Free Software Foundation; either version 3, or (at your option)
17
It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20
License for more details.
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You should have received a copy of the GNU General Public License
23
along with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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#include "libiberty.h"
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/* Default text to print if an instruction isn't recognized. */
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#define UNKNOWN_INSN_MSG _("*unknown*")
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static void print_normal
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(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
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static void print_address
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(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47
static void print_keyword
48
(CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
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static void print_insn_normal
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(CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
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(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
53
static int default_print_insn
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(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
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(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
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/* -- disassembler routines inserted here. */
63
print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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long reloc_ann ATTRIBUTE_UNUSED,
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long value ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "@");
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print_spr (CGEN_CPU_DESC cd,
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/* Use the register index format for any unnamed registers. */
83
if (cgen_keyword_lookup_value (names, regno) == NULL)
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "spr[%ld]", regno);
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print_keyword (cd, dis_info, names, regno, attrs);
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print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value);
106
print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
113
disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "0x%lx", value);
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(*info->fprintf_func) (info->stream, "lo(0x%lx)", value);
122
void frv_cgen_print_operand
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(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
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/* Main entry point for printing operands.
126
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
127
of dis-asm.h on cgen.h.
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This function is basically just a big switch statement. Earlier versions
130
used tables to look up the function to use, but
131
- if the table contains both assembler and disassembler functions then
132
the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
134
- using a switch statement avoids the function call overhead.
136
This function could be moved into `print_insn_normal', but keeping it
137
separate makes clear the interface between `print_insn_normal' and each of
141
frv_cgen_print_operand (CGEN_CPU_DESC cd,
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void const *attrs ATTRIBUTE_UNUSED,
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disassemble_info *info = (disassemble_info *) xinfo;
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case FRV_OPERAND_A0 :
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print_normal (cd, info, fields->f_A, 0, pc, length);
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case FRV_OPERAND_A1 :
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print_normal (cd, info, fields->f_A, 0, pc, length);
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case FRV_OPERAND_ACC40SI :
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print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);
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case FRV_OPERAND_ACC40SK :
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print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0);
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case FRV_OPERAND_ACC40UI :
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print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0);
168
case FRV_OPERAND_ACC40UK :
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print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0);
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case FRV_OPERAND_ACCGI :
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print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0);
174
case FRV_OPERAND_ACCGK :
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print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0);
177
case FRV_OPERAND_CCI :
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print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0);
180
case FRV_OPERAND_CPRDOUBLEK :
181
print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
183
case FRV_OPERAND_CPRI :
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print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0);
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case FRV_OPERAND_CPRJ :
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print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0);
189
case FRV_OPERAND_CPRK :
190
print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
192
case FRV_OPERAND_CRI :
193
print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0);
195
case FRV_OPERAND_CRJ :
196
print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0);
198
case FRV_OPERAND_CRJ_FLOAT :
199
print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0);
201
case FRV_OPERAND_CRJ_INT :
202
print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0);
204
case FRV_OPERAND_CRK :
205
print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0);
207
case FRV_OPERAND_FCCI_1 :
208
print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0);
210
case FRV_OPERAND_FCCI_2 :
211
print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0);
213
case FRV_OPERAND_FCCI_3 :
214
print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0);
216
case FRV_OPERAND_FCCK :
217
print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0);
219
case FRV_OPERAND_FRDOUBLEI :
220
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
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case FRV_OPERAND_FRDOUBLEJ :
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print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
225
case FRV_OPERAND_FRDOUBLEK :
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print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
228
case FRV_OPERAND_FRI :
229
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
231
case FRV_OPERAND_FRINTI :
232
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
234
case FRV_OPERAND_FRINTIEVEN :
235
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
237
case FRV_OPERAND_FRINTJ :
238
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
240
case FRV_OPERAND_FRINTJEVEN :
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print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
243
case FRV_OPERAND_FRINTK :
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print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
246
case FRV_OPERAND_FRINTKEVEN :
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print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
249
case FRV_OPERAND_FRJ :
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print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
252
case FRV_OPERAND_FRK :
253
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
255
case FRV_OPERAND_FRKHI :
256
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
258
case FRV_OPERAND_FRKLO :
259
print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
261
case FRV_OPERAND_GRDOUBLEK :
262
print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
264
case FRV_OPERAND_GRI :
265
print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0);
267
case FRV_OPERAND_GRJ :
268
print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0);
270
case FRV_OPERAND_GRK :
271
print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
273
case FRV_OPERAND_GRKHI :
274
print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
276
case FRV_OPERAND_GRKLO :
277
print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
279
case FRV_OPERAND_ICCI_1 :
280
print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0);
282
case FRV_OPERAND_ICCI_2 :
283
print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0);
285
case FRV_OPERAND_ICCI_3 :
286
print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0);
288
case FRV_OPERAND_LI :
289
print_normal (cd, info, fields->f_LI, 0, pc, length);
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case FRV_OPERAND_LRAD :
292
print_normal (cd, info, fields->f_LRAD, 0, pc, length);
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case FRV_OPERAND_LRAE :
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print_normal (cd, info, fields->f_LRAE, 0, pc, length);
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case FRV_OPERAND_LRAS :
298
print_normal (cd, info, fields->f_LRAS, 0, pc, length);
300
case FRV_OPERAND_TLBPRL :
301
print_normal (cd, info, fields->f_TLBPRL, 0, pc, length);
303
case FRV_OPERAND_TLBPROPX :
304
print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length);
306
case FRV_OPERAND_AE :
307
print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
309
case FRV_OPERAND_CALLANN :
310
print_at (cd, info, fields->f_reloc_ann, 0, pc, length);
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case FRV_OPERAND_CCOND :
313
print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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case FRV_OPERAND_COND :
316
print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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case FRV_OPERAND_D12 :
319
print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
321
case FRV_OPERAND_DEBUG :
322
print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
324
case FRV_OPERAND_EIR :
325
print_normal (cd, info, fields->f_eir, 0, pc, length);
327
case FRV_OPERAND_HINT :
328
print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
330
case FRV_OPERAND_HINT_NOT_TAKEN :
331
print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0);
333
case FRV_OPERAND_HINT_TAKEN :
334
print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0);
336
case FRV_OPERAND_LABEL16 :
337
print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
339
case FRV_OPERAND_LABEL24 :
340
print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
342
case FRV_OPERAND_LDANN :
343
print_at (cd, info, fields->f_reloc_ann, 0, pc, length);
345
case FRV_OPERAND_LDDANN :
346
print_at (cd, info, fields->f_reloc_ann, 0, pc, length);
348
case FRV_OPERAND_LOCK :
349
print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
351
case FRV_OPERAND_PACK :
352
print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0);
354
case FRV_OPERAND_S10 :
355
print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
357
case FRV_OPERAND_S12 :
358
print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
360
case FRV_OPERAND_S16 :
361
print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
363
case FRV_OPERAND_S5 :
364
print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
366
case FRV_OPERAND_S6 :
367
print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
369
case FRV_OPERAND_S6_1 :
370
print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
372
case FRV_OPERAND_SLO16 :
373
print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
375
case FRV_OPERAND_SPR :
376
print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL));
378
case FRV_OPERAND_U12 :
379
print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
381
case FRV_OPERAND_U16 :
382
print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
384
case FRV_OPERAND_U6 :
385
print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
387
case FRV_OPERAND_UHI16 :
388
print_hi (cd, info, fields->f_u16, 0, pc, length);
390
case FRV_OPERAND_ULO16 :
391
print_lo (cd, info, fields->f_u16, 0, pc, length);
395
/* xgettext:c-format */
396
fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
402
cgen_print_fn * const frv_cgen_print_handlers[] =
409
frv_cgen_init_dis (CGEN_CPU_DESC cd)
411
frv_cgen_init_opcode_table (cd);
412
frv_cgen_init_ibld_table (cd);
413
cd->print_handlers = & frv_cgen_print_handlers[0];
414
cd->print_operand = frv_cgen_print_operand;
418
/* Default print handler. */
421
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
425
bfd_vma pc ATTRIBUTE_UNUSED,
426
int length ATTRIBUTE_UNUSED)
428
disassemble_info *info = (disassemble_info *) dis_info;
430
/* Print the operand as directed by the attributes. */
431
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
432
; /* nothing to do */
433
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
434
(*info->fprintf_func) (info->stream, "%ld", value);
436
(*info->fprintf_func) (info->stream, "0x%lx", value);
439
/* Default address handler. */
442
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
446
bfd_vma pc ATTRIBUTE_UNUSED,
447
int length ATTRIBUTE_UNUSED)
449
disassemble_info *info = (disassemble_info *) dis_info;
451
/* Print the operand as directed by the attributes. */
452
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
453
; /* Nothing to do. */
454
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
455
(*info->print_address_func) (value, info);
456
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
457
(*info->print_address_func) (value, info);
458
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
459
(*info->fprintf_func) (info->stream, "%ld", (long) value);
461
(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
464
/* Keyword print handler. */
467
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
469
CGEN_KEYWORD *keyword_table,
471
unsigned int attrs ATTRIBUTE_UNUSED)
473
disassemble_info *info = (disassemble_info *) dis_info;
474
const CGEN_KEYWORD_ENTRY *ke;
476
ke = cgen_keyword_lookup_value (keyword_table, value);
478
(*info->fprintf_func) (info->stream, "%s", ke->name);
480
(*info->fprintf_func) (info->stream, "???");
483
/* Default insn printer.
485
DIS_INFO is defined as `void *' so the disassembler needn't know anything
486
about disassemble_info. */
489
print_insn_normal (CGEN_CPU_DESC cd,
491
const CGEN_INSN *insn,
496
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
497
disassemble_info *info = (disassemble_info *) dis_info;
498
const CGEN_SYNTAX_CHAR_TYPE *syn;
500
CGEN_INIT_PRINT (cd);
502
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
504
if (CGEN_SYNTAX_MNEMONIC_P (*syn))
506
(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
509
if (CGEN_SYNTAX_CHAR_P (*syn))
511
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
515
/* We have an operand. */
516
frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
517
fields, CGEN_INSN_ATTRS (insn), pc, length);
521
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
523
Returns 0 if all is well, non-zero otherwise. */
526
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
528
disassemble_info *info,
531
CGEN_EXTRACT_INFO *ex_info,
532
unsigned long *insn_value)
534
int status = (*info->read_memory_func) (pc, buf, buflen, info);
538
(*info->memory_error_func) (status, pc, info);
542
ex_info->dis_info = info;
543
ex_info->valid = (1 << buflen) - 1;
544
ex_info->insn_bytes = buf;
546
*insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
550
/* Utility to print an insn.
551
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
552
The result is the size of the insn in bytes or zero for an unknown insn
553
or -1 if an error occurs fetching data (memory_error_func will have
557
print_insn (CGEN_CPU_DESC cd,
559
disassemble_info *info,
563
CGEN_INSN_INT insn_value;
564
const CGEN_INSN_LIST *insn_list;
565
CGEN_EXTRACT_INFO ex_info;
568
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
569
basesize = cd->base_insn_bitsize < buflen * 8 ?
570
cd->base_insn_bitsize : buflen * 8;
571
insn_value = cgen_get_insn_value (cd, buf, basesize);
574
/* Fill in ex_info fields like read_insn would. Don't actually call
575
read_insn, since the incoming buffer is already read (and possibly
576
modified a la m32r). */
577
ex_info.valid = (1 << buflen) - 1;
578
ex_info.dis_info = info;
579
ex_info.insn_bytes = buf;
581
/* The instructions are stored in hash lists.
582
Pick the first one and keep trying until we find the right one. */
584
insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
585
while (insn_list != NULL)
587
const CGEN_INSN *insn = insn_list->insn;
590
unsigned long insn_value_cropped;
592
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
593
/* Not needed as insn shouldn't be in hash lists if not supported. */
594
/* Supported by this cpu? */
595
if (! frv_cgen_insn_supported (cd, insn))
597
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
602
/* Basic bit mask must be correct. */
603
/* ??? May wish to allow target to defer this check until the extract
606
/* Base size may exceed this instruction's size. Extract the
607
relevant part from the buffer. */
608
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
609
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
610
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
611
info->endian == BFD_ENDIAN_BIG);
613
insn_value_cropped = insn_value;
615
if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
616
== CGEN_INSN_BASE_VALUE (insn))
618
/* Printing is handled in two passes. The first pass parses the
619
machine insn and extracts the fields. The second pass prints
622
/* Make sure the entire insn is loaded into insn_value, if it
624
if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
625
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
627
unsigned long full_insn_value;
628
int rc = read_insn (cd, pc, info, buf,
629
CGEN_INSN_BITSIZE (insn) / 8,
630
& ex_info, & full_insn_value);
633
length = CGEN_EXTRACT_FN (cd, insn)
634
(cd, insn, &ex_info, full_insn_value, &fields, pc);
637
length = CGEN_EXTRACT_FN (cd, insn)
638
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
640
/* Length < 0 -> error. */
645
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
646
/* Length is in bits, result is in bytes. */
651
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
657
/* Default value for CGEN_PRINT_INSN.
658
The result is the size of the insn in bytes or zero for an unknown insn
659
or -1 if an error occured fetching bytes. */
661
#ifndef CGEN_PRINT_INSN
662
#define CGEN_PRINT_INSN default_print_insn
666
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
668
bfd_byte buf[CGEN_MAX_INSN_SIZE];
672
/* Attempt to read the base part of the insn. */
673
buflen = cd->base_insn_bitsize / 8;
674
status = (*info->read_memory_func) (pc, buf, buflen, info);
676
/* Try again with the minimum part, if min < base. */
677
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
679
buflen = cd->min_insn_bitsize / 8;
680
status = (*info->read_memory_func) (pc, buf, buflen, info);
685
(*info->memory_error_func) (status, pc, info);
689
return print_insn (cd, pc, info, buf, buflen);
693
Print one instruction from PC on INFO->STREAM.
694
Return the size of the instruction (in bytes). */
696
typedef struct cpu_desc_list
698
struct cpu_desc_list *next;
706
print_insn_frv (bfd_vma pc, disassemble_info *info)
708
static cpu_desc_list *cd_list = 0;
709
cpu_desc_list *cl = 0;
710
static CGEN_CPU_DESC cd = 0;
711
static CGEN_BITSET *prev_isa;
712
static int prev_mach;
713
static int prev_endian;
717
int endian = (info->endian == BFD_ENDIAN_BIG
719
: CGEN_ENDIAN_LITTLE);
720
enum bfd_architecture arch;
722
/* ??? gdb will set mach but leave the architecture as "unknown" */
723
#ifndef CGEN_BFD_ARCH
724
#define CGEN_BFD_ARCH bfd_arch_frv
727
if (arch == bfd_arch_unknown)
728
arch = CGEN_BFD_ARCH;
730
/* There's no standard way to compute the machine or isa number
731
so we leave it to the target. */
732
#ifdef CGEN_COMPUTE_MACH
733
mach = CGEN_COMPUTE_MACH (info);
738
#ifdef CGEN_COMPUTE_ISA
740
static CGEN_BITSET *permanent_isa;
743
permanent_isa = cgen_bitset_create (MAX_ISAS);
745
cgen_bitset_clear (isa);
746
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
749
isa = info->insn_sets;
752
/* If we've switched cpu's, try to find a handle we've used before */
754
&& (cgen_bitset_compare (isa, prev_isa) != 0
756
|| endian != prev_endian))
759
for (cl = cd_list; cl; cl = cl->next)
761
if (cgen_bitset_compare (cl->isa, isa) == 0 &&
763
cl->endian == endian)
772
/* If we haven't initialized yet, initialize the opcode table. */
775
const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
776
const char *mach_name;
780
mach_name = arch_type->printable_name;
782
prev_isa = cgen_bitset_copy (isa);
784
prev_endian = endian;
785
cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
786
CGEN_CPU_OPEN_BFDMACH, mach_name,
787
CGEN_CPU_OPEN_ENDIAN, prev_endian,
792
/* Save this away for future reference. */
793
cl = xmalloc (sizeof (struct cpu_desc_list));
801
frv_cgen_init_dis (cd);
804
/* We try to have as much common code as possible.
805
But at this point some targets need to take over. */
806
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
807
but if not possible try to move this hook elsewhere rather than
809
length = CGEN_PRINT_INSN (cd, pc, info);
815
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
816
return cd->default_insn_bitsize / 8;