327
328
for (; i < nvc0->state.num_vtxelts; ++i) {
328
329
BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
329
330
OUT_RING (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
331
if (unlikely(nvc0->state.instance_elts & (1 << i)))
332
IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
330
333
BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
331
334
OUT_RING (chan, 0);
368
371
nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
370
struct nvc0_context *nvc0 = chan->user_private;
372
nouveau_fence_update(&nvc0->screen->base, TRUE);
374
nvc0_bufctx_emit_relocs(nvc0);
373
struct nvc0_screen *screen = chan->user_private;
375
nouveau_fence_update(&screen->base, TRUE);
377
nvc0_bufctx_emit_relocs(screen->cur_ctx);
382
385
struct nouveau_channel *chan = nvc0->screen->base.channel;
388
if (nvc0->state.index_bias) {
389
IMMED_RING(chan, RING_3D(VB_ELEMENT_BASE), 0);
390
nvc0->state.index_bias = 0;
385
393
prim = nvc0_prim_gl(mode);
387
395
while (instance_count--) {
574
nvc0_draw_stream_output(struct nvc0_context *nvc0,
575
const struct pipe_draw_info *info)
577
struct nouveau_channel *chan = nvc0->screen->base.channel;
578
struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
579
struct nv04_resource *res = nv04_resource(so->pipe.buffer);
580
unsigned mode = nvc0_prim_gl(info->mode);
581
unsigned num_instances = info->instance_count;
583
if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
584
res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
585
IMMED_RING(chan, RING_3D(SERIALIZE), 0);
586
nvc0_query_fifo_wait(chan, so->pq);
587
IMMED_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 0);
590
while (num_instances--) {
591
BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
592
OUT_RING (chan, mode);
593
BEGIN_RING(chan, RING_3D(DRAW_TFB_BASE), 1);
595
BEGIN_RING(chan, RING_3D(DRAW_TFB_STRIDE), 1);
596
OUT_RING (chan, so->stride);
597
BEGIN_RING(chan, RING_3D(DRAW_TFB_BYTES), 1);
598
nvc0_query_pushbuf_submit(chan, so->pq, 0x4);
599
IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
601
mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
566
606
nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
584
624
if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
585
625
nvc0_update_user_vbufs(nvc0);
587
nvc0_state_validate(nvc0);
627
/* 8 as minimum to avoid immediate double validation of new buffers */
628
nvc0_state_validate(nvc0, ~0, 8);
589
630
chan->flush_notify = nvc0_draw_vbo_flush_notify;
590
chan->user_private = nvc0;
592
632
if (nvc0->vbo_fifo) {
593
633
nvc0_push_vbo(nvc0, info);
608
648
nvc0->base.vbo_dirty = FALSE;
651
if (unlikely(info->count_from_stream_output)) {
652
nvc0_draw_stream_output(nvc0, info);
611
654
if (!info->indexed) {
612
655
nvc0_draw_arrays(nvc0,
613
656
info->mode, info->start, info->count,