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Viewing changes to src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c

  • Committer: Package Import Robot
  • Author(s): Robert Hooker
  • Date: 2012-02-02 12:05:48 UTC
  • mfrom: (1.7.1) (3.3.27 sid)
  • Revision ID: package-import@ubuntu.com-20120202120548-nvkma85jq0h4coix
Tags: 8.0~rc2-0ubuntu4
Drop drisearchdir handling, it is no longer needed with multiarch
and dri-alternates being removed.

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added added

removed removed

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src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
1
 
/*
2
 
 * Copyright (C) 2009 Nicolai Haehnle.
3
 
 *
4
 
 * All Rights Reserved.
5
 
 *
6
 
 * Permission is hereby granted, free of charge, to any person obtaining
7
 
 * a copy of this software and associated documentation files (the
8
 
 * "Software"), to deal in the Software without restriction, including
9
 
 * without limitation the rights to use, copy, modify, merge, publish,
10
 
 * distribute, sublicense, and/or sell copies of the Software, and to
11
 
 * permit persons to whom the Software is furnished to do so, subject to
12
 
 * the following conditions:
13
 
 *
14
 
 * The above copyright notice and this permission notice (including the
15
 
 * next paragraph) shall be included in all copies or substantial
16
 
 * portions of the Software.
17
 
 *
18
 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19
 
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20
 
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21
 
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22
 
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23
 
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24
 
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
 
 *
26
 
 */
27
 
 
28
 
#include "radeon_opcodes.h"
29
 
#include "radeon_program.h"
30
 
 
31
 
#include "radeon_program_constants.h"
32
 
 
33
 
struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
34
 
        {
35
 
                .Opcode = RC_OPCODE_NOP,
36
 
                .Name = "NOP"
37
 
        },
38
 
        {
39
 
                .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
40
 
                .Name = "ILLEGAL OPCODE"
41
 
        },
42
 
        {
43
 
                .Opcode = RC_OPCODE_ABS,
44
 
                .Name = "ABS",
45
 
                .NumSrcRegs = 1,
46
 
                .HasDstReg = 1,
47
 
                .IsComponentwise = 1
48
 
        },
49
 
        {
50
 
                .Opcode = RC_OPCODE_ADD,
51
 
                .Name = "ADD",
52
 
                .NumSrcRegs = 2,
53
 
                .HasDstReg = 1,
54
 
                .IsComponentwise = 1
55
 
        },
56
 
        {
57
 
                .Opcode = RC_OPCODE_ARL,
58
 
                .Name = "ARL",
59
 
                .NumSrcRegs = 1,
60
 
                .HasDstReg = 1
61
 
        },
62
 
        {
63
 
                .Opcode = RC_OPCODE_CEIL,
64
 
                .Name = "CEIL",
65
 
                .NumSrcRegs = 1,
66
 
                .HasDstReg = 1,
67
 
                .IsComponentwise = 1
68
 
        },
69
 
        {
70
 
                .Opcode = RC_OPCODE_CLAMP,
71
 
                .Name = "CLAMP",
72
 
                .NumSrcRegs = 3,
73
 
                .HasDstReg = 1,
74
 
                .IsComponentwise = 1
75
 
        },
76
 
        {
77
 
                .Opcode = RC_OPCODE_CMP,
78
 
                .Name = "CMP",
79
 
                .NumSrcRegs = 3,
80
 
                .HasDstReg = 1,
81
 
                .IsComponentwise = 1
82
 
        },
83
 
        {
84
 
                .Opcode = RC_OPCODE_CND,
85
 
                .Name = "CND",
86
 
                .NumSrcRegs = 3,
87
 
                .HasDstReg = 1,
88
 
                .IsComponentwise = 1
89
 
        },
90
 
        {
91
 
                .Opcode = RC_OPCODE_COS,
92
 
                .Name = "COS",
93
 
                .NumSrcRegs = 1,
94
 
                .HasDstReg = 1,
95
 
                .IsStandardScalar = 1
96
 
        },
97
 
        {
98
 
                .Opcode = RC_OPCODE_DDX,
99
 
                .Name = "DDX",
100
 
                .NumSrcRegs = 2,
101
 
                .HasDstReg = 1,
102
 
                .IsComponentwise = 1
103
 
        },
104
 
        {
105
 
                .Opcode = RC_OPCODE_DDY,
106
 
                .Name = "DDY",
107
 
                .NumSrcRegs = 2,
108
 
                .HasDstReg = 1,
109
 
                .IsComponentwise = 1
110
 
        },
111
 
        {
112
 
                .Opcode = RC_OPCODE_DP2,
113
 
                .Name = "DP2",
114
 
                .NumSrcRegs = 2,
115
 
                .HasDstReg = 1
116
 
        },
117
 
        {
118
 
                .Opcode = RC_OPCODE_DP3,
119
 
                .Name = "DP3",
120
 
                .NumSrcRegs = 2,
121
 
                .HasDstReg = 1
122
 
        },
123
 
        {
124
 
                .Opcode = RC_OPCODE_DP4,
125
 
                .Name = "DP4",
126
 
                .NumSrcRegs = 2,
127
 
                .HasDstReg = 1
128
 
        },
129
 
        {
130
 
                .Opcode = RC_OPCODE_DPH,
131
 
                .Name = "DPH",
132
 
                .NumSrcRegs = 2,
133
 
                .HasDstReg = 1
134
 
        },
135
 
        {
136
 
                .Opcode = RC_OPCODE_DST,
137
 
                .Name = "DST",
138
 
                .NumSrcRegs = 2,
139
 
                .HasDstReg = 1
140
 
        },
141
 
        {
142
 
                .Opcode = RC_OPCODE_EX2,
143
 
                .Name = "EX2",
144
 
                .NumSrcRegs = 1,
145
 
                .HasDstReg = 1,
146
 
                .IsStandardScalar = 1
147
 
        },
148
 
        {
149
 
                .Opcode = RC_OPCODE_EXP,
150
 
                .Name = "EXP",
151
 
                .NumSrcRegs = 1,
152
 
                .HasDstReg = 1
153
 
        },
154
 
        {
155
 
                .Opcode = RC_OPCODE_FLR,
156
 
                .Name = "FLR",
157
 
                .NumSrcRegs = 1,
158
 
                .HasDstReg = 1,
159
 
                .IsComponentwise = 1
160
 
        },
161
 
        {
162
 
                .Opcode = RC_OPCODE_FRC,
163
 
                .Name = "FRC",
164
 
                .NumSrcRegs = 1,
165
 
                .HasDstReg = 1,
166
 
                .IsComponentwise = 1
167
 
        },
168
 
        {
169
 
                .Opcode = RC_OPCODE_KIL,
170
 
                .Name = "KIL",
171
 
                .NumSrcRegs = 1
172
 
        },
173
 
        {
174
 
                .Opcode = RC_OPCODE_LG2,
175
 
                .Name = "LG2",
176
 
                .NumSrcRegs = 1,
177
 
                .HasDstReg = 1,
178
 
                .IsStandardScalar = 1
179
 
        },
180
 
        {
181
 
                .Opcode = RC_OPCODE_LIT,
182
 
                .Name = "LIT",
183
 
                .NumSrcRegs = 1,
184
 
                .HasDstReg = 1
185
 
        },
186
 
        {
187
 
                .Opcode = RC_OPCODE_LOG,
188
 
                .Name = "LOG",
189
 
                .NumSrcRegs = 1,
190
 
                .HasDstReg = 1
191
 
        },
192
 
        {
193
 
                .Opcode = RC_OPCODE_LRP,
194
 
                .Name = "LRP",
195
 
                .NumSrcRegs = 3,
196
 
                .HasDstReg = 1,
197
 
                .IsComponentwise = 1
198
 
        },
199
 
        {
200
 
                .Opcode = RC_OPCODE_MAD,
201
 
                .Name = "MAD",
202
 
                .NumSrcRegs = 3,
203
 
                .HasDstReg = 1,
204
 
                .IsComponentwise = 1
205
 
        },
206
 
        {
207
 
                .Opcode = RC_OPCODE_MAX,
208
 
                .Name = "MAX",
209
 
                .NumSrcRegs = 2,
210
 
                .HasDstReg = 1,
211
 
                .IsComponentwise = 1
212
 
        },
213
 
        {
214
 
                .Opcode = RC_OPCODE_MIN,
215
 
                .Name = "MIN",
216
 
                .NumSrcRegs = 2,
217
 
                .HasDstReg = 1,
218
 
                .IsComponentwise = 1
219
 
        },
220
 
        {
221
 
                .Opcode = RC_OPCODE_MOV,
222
 
                .Name = "MOV",
223
 
                .NumSrcRegs = 1,
224
 
                .HasDstReg = 1,
225
 
                .IsComponentwise = 1
226
 
        },
227
 
        {
228
 
                .Opcode = RC_OPCODE_MUL,
229
 
                .Name = "MUL",
230
 
                .NumSrcRegs = 2,
231
 
                .HasDstReg = 1,
232
 
                .IsComponentwise = 1
233
 
        },
234
 
        {
235
 
                .Opcode = RC_OPCODE_POW,
236
 
                .Name = "POW",
237
 
                .NumSrcRegs = 2,
238
 
                .HasDstReg = 1,
239
 
                .IsStandardScalar = 1
240
 
        },
241
 
        {
242
 
                .Opcode = RC_OPCODE_RCP,
243
 
                .Name = "RCP",
244
 
                .NumSrcRegs = 1,
245
 
                .HasDstReg = 1,
246
 
                .IsStandardScalar = 1
247
 
        },
248
 
        {
249
 
                .Opcode = RC_OPCODE_RSQ,
250
 
                .Name = "RSQ",
251
 
                .NumSrcRegs = 1,
252
 
                .HasDstReg = 1,
253
 
                .IsStandardScalar = 1
254
 
        },
255
 
        {
256
 
                .Opcode = RC_OPCODE_SCS,
257
 
                .Name = "SCS",
258
 
                .NumSrcRegs = 1,
259
 
                .HasDstReg = 1
260
 
        },
261
 
        {
262
 
                .Opcode = RC_OPCODE_SEQ,
263
 
                .Name = "SEQ",
264
 
                .NumSrcRegs = 2,
265
 
                .HasDstReg = 1,
266
 
                .IsComponentwise = 1
267
 
        },
268
 
        {
269
 
                .Opcode = RC_OPCODE_SFL,
270
 
                .Name = "SFL",
271
 
                .NumSrcRegs = 0,
272
 
                .HasDstReg = 1,
273
 
                .IsComponentwise = 1
274
 
        },
275
 
        {
276
 
                .Opcode = RC_OPCODE_SGE,
277
 
                .Name = "SGE",
278
 
                .NumSrcRegs = 2,
279
 
                .HasDstReg = 1,
280
 
                .IsComponentwise = 1
281
 
        },
282
 
        {
283
 
                .Opcode = RC_OPCODE_SGT,
284
 
                .Name = "SGT",
285
 
                .NumSrcRegs = 2,
286
 
                .HasDstReg = 1,
287
 
                .IsComponentwise = 1
288
 
        },
289
 
        {
290
 
                .Opcode = RC_OPCODE_SIN,
291
 
                .Name = "SIN",
292
 
                .NumSrcRegs = 1,
293
 
                .HasDstReg = 1,
294
 
                .IsStandardScalar = 1
295
 
        },
296
 
        {
297
 
                .Opcode = RC_OPCODE_SLE,
298
 
                .Name = "SLE",
299
 
                .NumSrcRegs = 2,
300
 
                .HasDstReg = 1,
301
 
                .IsComponentwise = 1
302
 
        },
303
 
        {
304
 
                .Opcode = RC_OPCODE_SLT,
305
 
                .Name = "SLT",
306
 
                .NumSrcRegs = 2,
307
 
                .HasDstReg = 1,
308
 
                .IsComponentwise = 1
309
 
        },
310
 
        {
311
 
                .Opcode = RC_OPCODE_SNE,
312
 
                .Name = "SNE",
313
 
                .NumSrcRegs = 2,
314
 
                .HasDstReg = 1,
315
 
                .IsComponentwise = 1
316
 
        },
317
 
        {
318
 
                .Opcode = RC_OPCODE_SSG,
319
 
                .Name = "SSG",
320
 
                .NumSrcRegs = 1,
321
 
                .HasDstReg = 1,
322
 
                .IsComponentwise = 1
323
 
        },
324
 
        {
325
 
                .Opcode = RC_OPCODE_SUB,
326
 
                .Name = "SUB",
327
 
                .NumSrcRegs = 2,
328
 
                .HasDstReg = 1,
329
 
                .IsComponentwise = 1
330
 
        },
331
 
        {
332
 
                .Opcode = RC_OPCODE_SWZ,
333
 
                .Name = "SWZ",
334
 
                .NumSrcRegs = 1,
335
 
                .HasDstReg = 1,
336
 
                .IsComponentwise = 1
337
 
        },
338
 
        {
339
 
                .Opcode = RC_OPCODE_XPD,
340
 
                .Name = "XPD",
341
 
                .NumSrcRegs = 2,
342
 
                .HasDstReg = 1
343
 
        },
344
 
        {
345
 
                .Opcode = RC_OPCODE_TEX,
346
 
                .Name = "TEX",
347
 
                .HasTexture = 1,
348
 
                .NumSrcRegs = 1,
349
 
                .HasDstReg = 1
350
 
        },
351
 
        {
352
 
                .Opcode = RC_OPCODE_TXB,
353
 
                .Name = "TXB",
354
 
                .HasTexture = 1,
355
 
                .NumSrcRegs = 1,
356
 
                .HasDstReg = 1
357
 
        },
358
 
        {
359
 
                .Opcode = RC_OPCODE_TXD,
360
 
                .Name = "TXD",
361
 
                .HasTexture = 1,
362
 
                .NumSrcRegs = 3,
363
 
                .HasDstReg = 1
364
 
        },
365
 
        {
366
 
                .Opcode = RC_OPCODE_TXL,
367
 
                .Name = "TXL",
368
 
                .HasTexture = 1,
369
 
                .NumSrcRegs = 1,
370
 
                .HasDstReg = 1
371
 
        },
372
 
        {
373
 
                .Opcode = RC_OPCODE_TXP,
374
 
                .Name = "TXP",
375
 
                .HasTexture = 1,
376
 
                .NumSrcRegs = 1,
377
 
                .HasDstReg = 1
378
 
        },
379
 
        {
380
 
                .Opcode = RC_OPCODE_IF,
381
 
                .Name = "IF",
382
 
                .IsFlowControl = 1,
383
 
                .NumSrcRegs = 1
384
 
        },
385
 
        {
386
 
                .Opcode = RC_OPCODE_ELSE,
387
 
                .Name = "ELSE",
388
 
                .IsFlowControl = 1,
389
 
                .NumSrcRegs = 0
390
 
        },
391
 
        {
392
 
                .Opcode = RC_OPCODE_ENDIF,
393
 
                .Name = "ENDIF",
394
 
                .IsFlowControl = 1,
395
 
                .NumSrcRegs = 0
396
 
        },
397
 
        {
398
 
                .Opcode = RC_OPCODE_BGNLOOP,
399
 
                .Name = "BGNLOOP",
400
 
                .IsFlowControl = 1,
401
 
                .NumSrcRegs = 0
402
 
        },
403
 
        {
404
 
                .Opcode = RC_OPCODE_BRK,
405
 
                .Name = "BRK",
406
 
                .IsFlowControl = 1,
407
 
                .NumSrcRegs = 0
408
 
        },
409
 
        {
410
 
                .Opcode = RC_OPCODE_ENDLOOP,
411
 
                .Name = "ENDLOOP",
412
 
                .IsFlowControl = 1,
413
 
                .NumSrcRegs = 0,
414
 
        },
415
 
        {
416
 
                .Opcode = RC_OPCODE_CONT,
417
 
                .Name = "CONT",
418
 
                .IsFlowControl = 1,
419
 
                .NumSrcRegs = 0
420
 
        },
421
 
        {
422
 
                .Opcode = RC_OPCODE_REPL_ALPHA,
423
 
                .Name = "REPL_ALPHA",
424
 
                .HasDstReg = 1
425
 
        },
426
 
        {
427
 
                .Opcode = RC_OPCODE_BEGIN_TEX,
428
 
                .Name = "BEGIN_TEX"
429
 
        },
430
 
        {
431
 
                .Opcode = RC_OPCODE_KILP,
432
 
                .Name = "KILP",
433
 
        }
434
 
};
435
 
 
436
 
void rc_compute_sources_for_writemask(
437
 
                const struct rc_instruction *inst,
438
 
                unsigned int writemask,
439
 
                unsigned int *srcmasks)
440
 
{
441
 
        const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
442
 
        srcmasks[0] = 0;
443
 
        srcmasks[1] = 0;
444
 
        srcmasks[2] = 0;
445
 
 
446
 
        if (opcode->Opcode == RC_OPCODE_KIL)
447
 
                srcmasks[0] |= RC_MASK_XYZW;
448
 
        else if (opcode->Opcode == RC_OPCODE_IF)
449
 
                srcmasks[0] |= RC_MASK_X;
450
 
 
451
 
        if (!writemask)
452
 
                return;
453
 
 
454
 
        if (opcode->IsComponentwise) {
455
 
                for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
456
 
                        srcmasks[src] |= writemask;
457
 
        } else if (opcode->IsStandardScalar) {
458
 
                for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
459
 
                        srcmasks[src] |= RC_MASK_X;
460
 
        } else {
461
 
                switch(opcode->Opcode) {
462
 
                case RC_OPCODE_ARL:
463
 
                        srcmasks[0] |= RC_MASK_X;
464
 
                        break;
465
 
                case RC_OPCODE_DP2:
466
 
                        srcmasks[0] |= RC_MASK_XY;
467
 
                        srcmasks[1] |= RC_MASK_XY;
468
 
                        break;
469
 
                case RC_OPCODE_DP3:
470
 
                case RC_OPCODE_XPD:
471
 
                        srcmasks[0] |= RC_MASK_XYZ;
472
 
                        srcmasks[1] |= RC_MASK_XYZ;
473
 
                        break;
474
 
                case RC_OPCODE_DP4:
475
 
                        srcmasks[0] |= RC_MASK_XYZW;
476
 
                        srcmasks[1] |= RC_MASK_XYZW;
477
 
                        break;
478
 
                case RC_OPCODE_DPH:
479
 
                        srcmasks[0] |= RC_MASK_XYZ;
480
 
                        srcmasks[1] |= RC_MASK_XYZW;
481
 
                        break;
482
 
                case RC_OPCODE_TXB:
483
 
                case RC_OPCODE_TXP:
484
 
                case RC_OPCODE_TXL:
485
 
                        srcmasks[0] |= RC_MASK_W;
486
 
                        /* Fall through */
487
 
                case RC_OPCODE_TEX:
488
 
                        switch (inst->U.I.TexSrcTarget) {
489
 
                                case RC_TEXTURE_1D:
490
 
                                        srcmasks[0] |= RC_MASK_X;
491
 
                                        break;
492
 
                                case RC_TEXTURE_2D:
493
 
                                case RC_TEXTURE_RECT:
494
 
                                case RC_TEXTURE_1D_ARRAY:
495
 
                                        srcmasks[0] |= RC_MASK_XY;
496
 
                                        break;
497
 
                                case RC_TEXTURE_3D:
498
 
                                case RC_TEXTURE_CUBE:
499
 
                                case RC_TEXTURE_2D_ARRAY:
500
 
                                        srcmasks[0] |= RC_MASK_XYZ;
501
 
                                        break;
502
 
                        }
503
 
                        break;
504
 
                case RC_OPCODE_TXD:
505
 
                        switch (inst->U.I.TexSrcTarget) {
506
 
                                case RC_TEXTURE_1D_ARRAY:
507
 
                                        srcmasks[0] |= RC_MASK_Y;
508
 
                                        /* Fall through. */
509
 
                                case RC_TEXTURE_1D:
510
 
                                        srcmasks[0] |= RC_MASK_X;
511
 
                                        srcmasks[1] |= RC_MASK_X;
512
 
                                        srcmasks[2] |= RC_MASK_X;
513
 
                                        break;
514
 
                                case RC_TEXTURE_2D_ARRAY:
515
 
                                        srcmasks[0] |= RC_MASK_Z;
516
 
                                        /* Fall through. */
517
 
                                case RC_TEXTURE_2D:
518
 
                                case RC_TEXTURE_RECT:
519
 
                                        srcmasks[0] |= RC_MASK_XY;
520
 
                                        srcmasks[1] |= RC_MASK_XY;
521
 
                                        srcmasks[2] |= RC_MASK_XY;
522
 
                                        break;
523
 
                                case RC_TEXTURE_3D:
524
 
                                case RC_TEXTURE_CUBE:
525
 
                                        srcmasks[0] |= RC_MASK_XYZ;
526
 
                                        srcmasks[1] |= RC_MASK_XYZ;
527
 
                                        srcmasks[2] |= RC_MASK_XYZ;
528
 
                                        break;
529
 
                        }
530
 
                        break;
531
 
                case RC_OPCODE_DST:
532
 
                        srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
533
 
                        srcmasks[1] |= RC_MASK_Y | RC_MASK_W;
534
 
                        break;
535
 
                case RC_OPCODE_EXP:
536
 
                case RC_OPCODE_LOG:
537
 
                        srcmasks[0] |= RC_MASK_XY;
538
 
                        break;
539
 
                case RC_OPCODE_LIT:
540
 
                        srcmasks[0] |= RC_MASK_X | RC_MASK_Y | RC_MASK_W;
541
 
                        break;
542
 
                default:
543
 
                        break;
544
 
                }
545
 
        }
546
 
}