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#ifndef RADEON_CS_WRAPPER_H
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#define RADEON_CS_WRAPPER_H
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/* to be used to build locally in mesa with no libdrm bits */
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#include "../radeon/radeon_bo_drm.h"
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#include "../radeon/radeon_cs_drm.h"
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#ifdef HAVE_LIBDRM_RADEON
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#include "radeon_bo.h"
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#include "radeon_bo_gem.h"
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#include "radeon_cs.h"
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#include "radeon_cs_gem.h"
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#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
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#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
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#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
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#define RADEON_TILING_MACRO 0x1
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#define RADEON_TILING_MICRO 0x2
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#define RADEON_TILING_SWAP 0x4
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#ifndef RADEON_TILING_SURFACE
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#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
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* when mapped - i.e. front buffer */
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#ifndef DRM_RADEON_GEM_INFO
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#define DRM_RADEON_GEM_INFO 0x1c
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struct drm_radeon_gem_info {
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uint64_t vram_visible;
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struct drm_radeon_info {
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#ifndef RADEON_PARAM_DEVICE_ID
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#define RADEON_PARAM_DEVICE_ID 16
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#ifndef RADEON_PARAM_NUM_Z_PIPES
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#define RADEON_PARAM_NUM_Z_PIPES 17
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#ifndef RADEON_INFO_DEVICE_ID
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#define RADEON_INFO_DEVICE_ID 0
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#ifndef RADEON_INFO_NUM_GB_PIPES
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#define RADEON_INFO_NUM_GB_PIPES 0
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#ifndef RADEON_INFO_NUM_Z_PIPES
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#define RADEON_INFO_NUM_Z_PIPES 0
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#ifndef DRM_RADEON_INFO
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#define DRM_RADEON_INFO 0x1
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static inline void radeon_gem_get_kernel_name(struct radeon_bo *dummy, uint32_t *value)
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static inline uint32_t radeon_gem_name_bo(struct radeon_bo *dummy)
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static inline void *radeon_bo_manager_gem_ctor(int fd)
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static inline void radeon_bo_manager_gem_dtor(void *dummy)
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static inline void *radeon_cs_manager_gem_ctor(int fd)
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static inline void radeon_cs_manager_gem_dtor(void *dummy)
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static inline void radeon_tracker_print(void *ptr, int io)
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#include "radeon_bo_legacy.h"
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#include "radeon_cs_legacy.h"