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* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
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* CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
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#include "main/imports.h"
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#include "program/prog_parameter.h"
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#include "program/prog_statevars.h"
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#include "program/program.h"
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#include "r600_context.h"
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#include "r600_cmdbuf.h"
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#include "r600_emit.h"
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#include "r700_fragprog.h"
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#include "r700_debug.h"
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void insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog)
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static const gl_state_index winstate[STATE_LENGTH]
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= { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0};
51
struct prog_instruction *newInst, *inst;
52
GLint win_size; /* state reference */
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GLuint wpos_temp; /* temp register */
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/* PARAM win_size = STATE_FB_WPOS_Y_TRANSFORM */
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win_size = _mesa_add_state_reference(fprog->Base.Parameters, winstate);
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wpos_temp = fprog->Base.NumTemporaries++;
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/* scan program where WPOS is used and replace with wpos_temp */
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inst = fprog->Base.Instructions;
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for (i = 0; i < fprog->Base.NumInstructions; i++) {
64
for (j=0; j < 3; j++) {
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if(inst->SrcReg[j].File == PROGRAM_INPUT &&
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inst->SrcReg[j].Index == FRAG_ATTRIB_WPOS) {
67
inst->SrcReg[j].File = PROGRAM_TEMPORARY;
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inst->SrcReg[j].Index = wpos_temp;
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_mesa_insert_instructions(&(fprog->Base), 0, 1);
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newInst = fprog->Base.Instructions;
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/* possibly invert wpos.y depending on STATE_FB_WPOS_Y_TRANSFORM var */
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newInst[0].Opcode = OPCODE_MAD;
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newInst[0].DstReg.File = PROGRAM_TEMPORARY;
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newInst[0].DstReg.Index = wpos_temp;
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newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
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newInst[0].SrcReg[0].File = PROGRAM_INPUT;
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newInst[0].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
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newInst[0].SrcReg[0].Swizzle = SWIZZLE_XYZW;
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newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR;
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newInst[0].SrcReg[1].Index = win_size;
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newInst[0].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE);
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newInst[0].SrcReg[2].File = PROGRAM_STATE_VAR;
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newInst[0].SrcReg[2].Index = win_size;
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newInst[0].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO);
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//TODO : Validate FP input with VP output.
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void Map_Fragment_Program(r700_AssemblerBase *pAsm,
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struct gl_fragment_program *mesa_fp,
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struct gl_context *ctx)
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/* match fp inputs with vp exports. */
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struct r700_vertex_program_cont *vpc =
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(struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
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GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
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pAsm->number_used_registers = 0;
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//Input mapping : mesa_fp->Base.InputsRead set the flag, set in
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//The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
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//MUST match order in Map_Vertex_Output
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unBit = 1 << FRAG_ATTRIB_WPOS;
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if(mesa_fp->Base.InputsRead & unBit)
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pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
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unBit = 1 << VERT_RESULT_COL0;
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if(OutputsWritten & unBit)
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pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++;
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unBit = 1 << VERT_RESULT_COL1;
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if(OutputsWritten & unBit)
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pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
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unBit = 1 << VERT_RESULT_FOGC;
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if(OutputsWritten & unBit)
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pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
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unBit = 1 << (VERT_RESULT_TEX0 + i);
142
if(OutputsWritten & unBit)
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pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++;
148
/* order has been taken care of */
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for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
153
if(OutputsWritten & unBit)
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pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0] = pAsm->number_used_registers++;
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if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 )
161
struct r700_vertex_program_cont *vpc =
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(struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
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struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying;
164
struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying;
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struct gl_program_parameter * pVsParam;
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struct gl_program_parameter * pPsParam;
168
GLuint unMaxVarying = 0;
170
for(i=0; i<VsVarying->NumParameters; i++)
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pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0;
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for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
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if(mesa_fp->Base.InputsRead & unBit)
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j = i - FRAG_ATTRIB_VAR0;
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pPsParam = PsVarying->Parameters + j;
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for(k=0; k<VsVarying->NumParameters; k++)
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pVsParam = VsVarying->Parameters + k;
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if( strcmp(pPsParam->Name, pVsParam->Name) == 0)
189
pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k;
200
pAsm->number_used_registers += unMaxVarying + 1;
203
unBit = 1 << FRAG_ATTRIB_FACE;
204
if(mesa_fp->Base.InputsRead & unBit)
206
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE] = pAsm->number_used_registers++;
209
unBit = 1 << FRAG_ATTRIB_PNTC;
210
if(mesa_fp->Base.InputsRead & unBit)
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pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC] = pAsm->number_used_registers++;
215
/* Map temporary registers (GPRs) */
216
pAsm->starting_temp_register_number = pAsm->number_used_registers;
218
if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries)
220
pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries;
224
pAsm->number_used_registers += mesa_fp->Base.NumTemporaries;
228
pAsm->number_of_exports = 0;
229
pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */
230
pAsm->starting_export_register_number = pAsm->number_used_registers;
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for (i = 0; i < FRAG_RESULT_MAX; ++i)
235
if (mesa_fp->Base.OutputsWritten & unBit)
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if (i == FRAG_RESULT_DEPTH)
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pAsm->depth_export_register_number = pAsm->number_used_registers;
240
pAsm->pR700Shader->depthIsExported = 1;
243
pAsm->uiFP_OutputMap[i] = pAsm->number_used_registers++;
244
++pAsm->number_of_exports;
245
++pAsm->number_of_colorandz_exports;
249
pAsm->flag_reg_index = pAsm->number_used_registers++;
251
pAsm->uFirstHelpReg = pAsm->number_used_registers;
254
GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp,
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struct gl_fragment_program *mesa_fp)
258
GLint * puiTEMPwrites;
259
GLint * puiTEMPreads;
260
struct prog_instruction * pILInst;
262
struct prog_instruction * texcoord_DepInst;
265
puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
266
puiTEMPreads = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
268
for(i=0; i<mesa_fp->Base.NumTemporaries; i++)
270
puiTEMPwrites[i] = -1;
271
puiTEMPreads[i] = -1;
274
pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions);
276
for(i=0; i<mesa_fp->Base.NumInstructions; i++)
278
pInstDeps[i].nDstDep = -1;
279
pILInst = &(mesa_fp->Base.Instructions[i]);
282
if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
284
//Set lastwrite for the temp
285
puiTEMPwrites[pILInst->DstReg.Index] = i;
291
if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
294
pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
296
if(puiTEMPreads[pILInst->SrcReg[j].Index] < 0 )
298
puiTEMPreads[pILInst->SrcReg[j].Index] = i;
303
pInstDeps[i].nSrcDeps[j] = -1;
308
fp->r700AsmCode.pInstDeps = pInstDeps;
310
//Find dep for tex inst
311
for(i=0; i<mesa_fp->Base.NumInstructions; i++)
313
pILInst = &(mesa_fp->Base.Instructions[i]);
315
if(GL_TRUE == IsTex(pILInst->Opcode))
316
{ //src0 is the tex coord register, src1 is texunit, src2 is textype
317
nDepInstID = pInstDeps[i].nSrcDeps[0];
320
texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
321
if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
323
pInstDeps[nDepInstID].nDstDep = i;
324
pInstDeps[i].nDstDep = i;
326
else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) )
328
pInstDeps[i].nDstDep = i;
334
// make sure that we dont overwrite src used earlier
335
nDepInstID = puiTEMPreads[pILInst->DstReg.Index];
338
pInstDeps[i].nDstDep = puiTEMPreads[pILInst->DstReg.Index];
339
texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
340
if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
342
pInstDeps[nDepInstID].nDstDep = i;
356
GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
357
struct gl_fragment_program *mesa_fp,
358
struct gl_context *ctx)
360
context_t *context = R700_CONTEXT(ctx);
361
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
363
GLuint number_of_colors_exported;
364
GLboolean z_enabled = GL_FALSE;
365
GLuint unBit, shadow_unit;
367
struct prog_instruction *inst;
368
gl_state_index shadow_ambient[STATE_LENGTH]
369
= { STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0};
372
Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
374
if(GL_TRUE == r700->bShaderUseMemConstant)
376
fp->r700AsmCode.bUseMemConstant = GL_TRUE;
380
fp->r700AsmCode.bUseMemConstant = GL_FALSE;
383
fp->r700AsmCode.unAsic = 7;
385
if(mesa_fp->Base.InputsRead & FRAG_BIT_WPOS)
387
insert_wpos_code(ctx, mesa_fp);
390
/* add/map consts for ARB_shadow_ambient */
391
if(mesa_fp->Base.ShadowSamplers)
393
inst = mesa_fp->Base.Instructions;
394
for (i = 0; i < mesa_fp->Base.NumInstructions; i++)
396
if(inst->TexShadow == 1)
398
shadow_unit = inst->TexSrcUnit;
399
shadow_ambient[2] = shadow_unit;
400
fp->r700AsmCode.shadow_regs[shadow_unit] =
401
_mesa_add_state_reference(mesa_fp->Base.Parameters, shadow_ambient);
407
Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp, ctx);
409
if( GL_FALSE == Find_Instruction_Dependencies_fp(fp, mesa_fp) )
414
InitShaderProgram(&(fp->r700AsmCode));
416
for(i=0; i < MAX_SAMPLERS; i++)
418
fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i];
421
fp->r700AsmCode.unCurNumILInsts = mesa_fp->Base.NumInstructions;
423
if( GL_FALSE == AssembleInstr(0,
425
mesa_fp->Base.NumInstructions,
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&(mesa_fp->Base.Instructions[0]),
427
&(fp->r700AsmCode)) )
432
if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) )
437
if( GL_FALSE == RelocProgram(&(fp->r700AsmCode), &(mesa_fp->Base)) )
442
fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
443
: (fp->r700AsmCode.number_used_registers - 1);
445
fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports;
447
number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports;
449
unBit = 1 << FRAG_RESULT_DEPTH;
450
if(mesa_fp->Base.OutputsWritten & unBit)
453
number_of_colors_exported--;
456
/* illegal to set this to 0 */
457
if(number_of_colors_exported || z_enabled)
459
fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled;
463
fp->r700Shader.exportMode = (1 << 1);
466
fp->translated = GL_TRUE;
471
void r700SelectFragmentShader(struct gl_context *ctx)
473
context_t *context = R700_CONTEXT(ctx);
474
struct r700_fragment_program *fp = (struct r700_fragment_program *)
475
(ctx->FragmentProgram._Current);
476
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
478
fp->r700AsmCode.bR6xx = 1;
481
if (GL_FALSE == fp->translated)
482
r700TranslateFragmentShader(fp, &(fp->mesa_program), ctx);
485
void * r700GetActiveFpShaderBo(struct gl_context * ctx)
487
struct r700_fragment_program *fp = (struct r700_fragment_program *)
488
(ctx->FragmentProgram._Current);
493
void * r700GetActiveFpShaderConstBo(struct gl_context * ctx)
495
struct r700_fragment_program *fp = (struct r700_fragment_program *)
496
(ctx->FragmentProgram._Current);
501
GLboolean r700SetupFragmentProgram(struct gl_context * ctx)
503
context_t *context = R700_CONTEXT(ctx);
504
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
505
struct r700_fragment_program *fp = (struct r700_fragment_program *)
506
(ctx->FragmentProgram._Current);
507
r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
508
struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
509
struct gl_program_parameter_list *paramList;
510
unsigned int unNumParamData;
512
unsigned int unNumOfReg;
514
unsigned int num_sq_ps_gprs;
516
GLboolean point_sprite = GL_FALSE;
518
if(GL_FALSE == fp->loaded)
520
if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
522
Assemble( &(fp->r700Shader) );
528
(GLvoid *)(fp->r700Shader.pProgram),
529
fp->r700Shader.uShaderBinaryDWORDSize,
532
fp->loaded = GL_TRUE;
535
DumpHwBinary(DUMP_PIXEL_SHADER, (GLvoid *)(fp->r700Shader.pProgram),
536
fp->r700Shader.uShaderBinaryDWORDSize);
538
/* TODO : enable this after MemUse fixed *=
539
(context->chipobj.MemUse)(context, fp->shadercode.buf->id);
542
R600_STATECHANGE(context, ps);
544
r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
545
SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
547
r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */
549
R600_STATECHANGE(context, spi);
551
unNumOfReg = fp->r700Shader.nRegs + 1;
553
ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
555
/* PS uses fragment.position */
556
if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
559
SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
560
SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
561
SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
562
SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
566
CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
567
CLEARbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
570
if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_FACE))
573
SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
574
SETbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
575
SETbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ALL_BITS_bit);
576
SETfield(r700->SPI_PS_IN_CONTROL_1.u32All, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE], FRONT_FACE_ADDR_shift, FRONT_FACE_ADDR_mask);
580
CLEARbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
583
/* see if we need any point_sprite replacements, also increase num_interp
584
* as there's no vp output for them */
585
if (ctx->Point.PointSprite)
587
for (i = FRAG_ATTRIB_TEX0; i<= FRAG_ATTRIB_TEX7; i++)
589
if (ctx->Point.CoordReplace[i - FRAG_ATTRIB_TEX0] == GL_TRUE)
592
point_sprite = GL_TRUE;
597
if( mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC))
600
if ((mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC)) || point_sprite)
602
SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
603
SETbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
604
SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_S, PNT_SPRITE_OVRD_X_shift, PNT_SPRITE_OVRD_X_mask);
605
SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_T, PNT_SPRITE_OVRD_Y_shift, PNT_SPRITE_OVRD_Y_mask);
606
SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_0, PNT_SPRITE_OVRD_Z_shift, PNT_SPRITE_OVRD_Z_mask);
607
SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_1, PNT_SPRITE_OVRD_W_shift, PNT_SPRITE_OVRD_W_mask);
608
/* Like e.g. viewport and winding, point sprite coordinates are
609
* inverted when rendering to FBO. */
610
if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) == !ctx->DrawBuffer->Name)
611
SETbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
613
CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
617
CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
621
ui = (unNumOfReg < ui) ? ui : unNumOfReg;
623
SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
625
num_sq_ps_gprs = ((r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All & NUM_PS_GPRS_mask) >> NUM_PS_GPRS_shift);
627
if(ui > num_sq_ps_gprs)
629
/* care! thich changes sq - needs idle state */
630
R600_STATECHANGE(context, sq);
631
SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, ui, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
634
CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
636
if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
638
SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize,
639
STACK_SIZE_shift, STACK_SIZE_mask);
642
SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
643
EXPORT_MODE_shift, EXPORT_MODE_mask);
646
struct r700_vertex_program_cont *vpc =
647
(struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
648
GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
650
for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
651
r700->SPI_PS_INPUT_CNTL[ui].u32All = 0;
653
unBit = 1 << FRAG_ATTRIB_WPOS;
654
if(mesa_fp->Base.InputsRead & unBit)
656
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
657
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
658
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
659
SEMANTIC_shift, SEMANTIC_mask);
660
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
663
unBit = 1 << VERT_RESULT_COL0;
664
if(OutputsWritten & unBit)
666
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
667
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
668
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
669
SEMANTIC_shift, SEMANTIC_mask);
670
if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
671
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
673
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
676
unBit = 1 << VERT_RESULT_COL1;
677
if(OutputsWritten & unBit)
679
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
680
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
681
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
682
SEMANTIC_shift, SEMANTIC_mask);
683
if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
684
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
686
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
689
unBit = 1 << VERT_RESULT_FOGC;
690
if(OutputsWritten & unBit)
692
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
693
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
694
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
695
SEMANTIC_shift, SEMANTIC_mask);
696
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
701
GLboolean coord_replace = ctx->Point.PointSprite && ctx->Point.CoordReplace[i];
702
unBit = 1 << (VERT_RESULT_TEX0 + i);
703
if ((OutputsWritten & unBit) || coord_replace)
705
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
706
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
707
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
708
SEMANTIC_shift, SEMANTIC_mask);
709
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
710
/* ARB_point_sprite */
713
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
718
unBit = 1 << FRAG_ATTRIB_FACE;
719
if(mesa_fp->Base.InputsRead & unBit)
721
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE];
722
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
723
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
724
SEMANTIC_shift, SEMANTIC_mask);
725
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
727
unBit = 1 << FRAG_ATTRIB_PNTC;
728
if(mesa_fp->Base.InputsRead & unBit)
730
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC];
731
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
732
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
733
SEMANTIC_shift, SEMANTIC_mask);
734
if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
735
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
737
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
738
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
744
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
747
if(OutputsWritten & unBit)
749
ui = pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0];
750
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
751
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
752
SEMANTIC_shift, SEMANTIC_mask);
753
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
757
exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
758
if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1))
760
R600_STATECHANGE(context, cb);
761
r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
764
/* sent out shader constants. */
765
paramList = fp->mesa_program.Base.Parameters;
767
if(NULL != paramList)
769
_mesa_load_state_parameters(ctx, paramList);
771
if (paramList->NumParameters > R700_MAX_DX9_CONSTS)
774
R600_STATECHANGE(context, ps_consts);
776
r700->ps.num_consts = paramList->NumParameters;
778
unNumParamData = paramList->NumParameters;
780
for(ui=0; ui<unNumParamData; ui++) {
781
r700->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0];
782
r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1];
783
r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
784
r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
787
/* Load fp constants to gpu */
788
if( (GL_TRUE == r700->bShaderUseMemConstant) && (unNumParamData > 0) )
792
(GLvoid *)&(paramList->ParameterValues[0][0]),
798
r700->ps.num_consts = 0;
800
COMPILED_SUB * pCompiledSub;
802
GLuint unConstOffset = r700->ps.num_consts;
803
for(ui=0; ui<pAsm->unNumPresub; ui++)
805
pCompiledSub = pAsm->presubs[ui].pCompiledSub;
807
r700->ps.num_consts += pCompiledSub->NumParameters;
809
for(uj=0; uj<pCompiledSub->NumParameters; uj++)
811
r700->ps.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
812
r700->ps.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
813
r700->ps.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
814
r700->ps.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
816
unConstOffset += pCompiledSub->NumParameters;