295
293
alu.bank_swizzle_force = SQ_ALU_VEC_210;
296
294
if ((i % 4) == 3)
298
r = r600_bc_add_alu(ctx->bc, &alu);
296
r = r600_bytecode_add_alu(ctx->bc, &alu);
303
static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
306
struct r600_bytecode_alu alu;
308
for (i = 0; i < 4; i++) {
309
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
311
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0;
313
alu.dst.sel = ctx->shader->input[input].gpr;
318
alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
323
r = r600_bytecode_add_alu(ctx->bc, &alu);
331
* Special export handling in shaders
333
* shader export ARRAY_BASE for EXPORT_POS:
336
* 62, 63 are clip distance vectors
338
* The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
339
* VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
340
* USE_VTX_POINT_SIZE - point size in the X channel of export 61
341
* USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
342
* USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
343
* USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
344
* USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
345
* exclusive from render target index)
346
* VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
349
* shader export ARRAY_BASE for EXPORT_PIXEL:
351
* 61 computed Z vector
353
* The use of the values exported in the computed Z vector are controlled
354
* by DB_SHADER_CONTROL:
355
* Z_EXPORT_ENABLE - Z as a float in RED
356
* STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
357
* COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
358
* MASK_EXPORT_ENABLE - pixel sample mask in BLUE
359
* DB_SOURCE_FORMAT - export control restrictions
364
/* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
365
static int r600_spi_sid(struct r600_shader_io * io)
367
int index, name = io->name;
369
/* These params are handled differently, they don't need
370
* semantic indices, so we'll use 0 for them.
372
if (name == TGSI_SEMANTIC_POSITION ||
373
name == TGSI_SEMANTIC_PSIZE ||
374
name == TGSI_SEMANTIC_FACE)
377
if (name == TGSI_SEMANTIC_GENERIC) {
378
/* For generic params simply use sid from tgsi */
381
/* For non-generic params - pack name and sid into 8 bits */
382
index = 0x80 | (name<<3) | (io->sid);
385
/* Make sure that all really used indices have nonzero value, so
386
* we can just compare it to 0 later instead of comparing the name
387
* with different values to detect special cases. */
394
/* turn input into interpolate on EG */
395
static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
399
if (ctx->shader->input[index].spi_sid) {
400
ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
401
if (ctx->shader->input[index].interpolate > 0) {
402
r = evergreen_interp_alu(ctx, index);
404
r = evergreen_interp_flat(ctx, index);
410
static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
412
struct r600_bytecode_alu alu;
414
int gpr_front = ctx->shader->input[front].gpr;
415
int gpr_back = ctx->shader->input[back].gpr;
417
for (i = 0; i < 4; i++) {
418
memset(&alu, 0, sizeof(alu));
419
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
422
alu.dst.sel = gpr_front;
423
alu.src[0].sel = ctx->face_gpr;
424
alu.src[1].sel = gpr_front;
425
alu.src[2].sel = gpr_back;
432
if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
306
439
static int tgsi_declaration(struct r600_shader_ctx *ctx)
751
static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
753
int i, r, count = ctx->shader->ninput;
755
/* additional inputs will be allocated right after the existing inputs,
756
* we won't need them after the color selection, so we don't need to
757
* reserve these gprs for the rest of the shader code and to adjust
758
* output offsets etc. */
759
int gpr = ctx->file_offset[TGSI_FILE_INPUT] +
760
ctx->info.file_max[TGSI_FILE_INPUT] + 1;
762
if (ctx->face_gpr == -1) {
763
i = ctx->shader->ninput++;
764
ctx->shader->input[i].name = TGSI_SEMANTIC_FACE;
765
ctx->shader->input[i].spi_sid = 0;
766
ctx->shader->input[i].gpr = gpr++;
767
ctx->face_gpr = ctx->shader->input[i].gpr;
770
for (i = 0; i < count; i++) {
771
if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
772
int ni = ctx->shader->ninput++;
773
memcpy(&ctx->shader->input[ni],&ctx->shader->input[i], sizeof(struct r600_shader_io));
774
ctx->shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
775
ctx->shader->input[ni].spi_sid = r600_spi_sid(&ctx->shader->input[ni]);
776
ctx->shader->input[ni].gpr = gpr++;
778
if (ctx->bc->chip_class >= EVERGREEN) {
779
r = evergreen_interp_input(ctx, ni);
784
r = select_twoside_color(ctx, i, ni);
599
792
static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pipe_shader *pipeshader)
601
794
struct r600_shader *shader = &pipeshader->shader;
602
795
struct tgsi_token *tokens = pipeshader->tokens;
796
struct pipe_stream_output_info so = pipeshader->so;
603
797
struct tgsi_full_immediate *immediate;
604
798
struct tgsi_full_property *property;
605
799
struct r600_shader_ctx ctx;
606
struct r600_bc_output output[32];
800
struct r600_bytecode_output output[32];
607
801
unsigned output_done, noutput;
609
int i, j, r = 0, pos0;
804
int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
611
806
ctx.bc = &shader->bc;
612
807
ctx.shader = shader;
613
r = r600_bc_init(ctx.bc, shader->family);
808
r600_bytecode_init(ctx.bc, rctx->chip_class, rctx->family);
616
809
ctx.tokens = tokens;
617
810
tgsi_scan_shader(tokens, &ctx.info);
618
811
tgsi_parse_init(&ctx.parse, tokens);
724
case TGSI_TOKEN_TYPE_PROPERTY:
725
property = &ctx.parse.FullToken.FullProperty;
726
if (property->Property.PropertyName == TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) {
727
if (property->u[0].Data == 1)
728
shader->fs_write_all = TRUE;
732
R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
738
959
noutput = shader->noutput;
961
if (ctx.clip_vertex_write) {
962
/* need to convert a clipvertex write into clipdistance writes and not export
963
the clip vertex anymore */
965
memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
966
shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
967
shader->output[noutput].gpr = ctx.temp_reg;
969
shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
970
shader->output[noutput].gpr = ctx.temp_reg+1;
973
/* reset spi_sid for clipvertex output to avoid confusing spi */
974
shader->output[ctx.cv_output].spi_sid = 0;
976
shader->clip_dist_write = 0xFF;
978
for (i = 0; i < 8; i++) {
982
for (j = 0; j < 4; j++) {
983
struct r600_bytecode_alu alu;
984
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
985
alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4);
986
alu.src[0].sel = shader->output[ctx.cv_output].gpr;
989
alu.src[1].sel = 512 + i;
990
alu.src[1].kc_bank = 1;
993
alu.dst.sel = ctx.temp_reg + oreg;
995
alu.dst.write = (j == ochan);
998
r = r600_bytecode_add_alu(ctx.bc, &alu);
740
1005
/* clamp color outputs */
741
1006
if (shader->clamp_color) {
742
1007
for (i = 0; i < noutput; i++) {
1036
/* Add stream outputs. */
1037
if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs) {
1038
unsigned buffer_offset[PIPE_MAX_SO_BUFFERS] = {0};
1040
for (i = 0; i < so.num_outputs; i++) {
1041
struct r600_bytecode_output output;
1044
if (so.output[i].output_buffer >= 4) {
1045
R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1046
so.output[i].output_buffer);
1051
switch (so.output[i].register_mask) {
1052
case TGSI_WRITEMASK_XYZW:
1055
case TGSI_WRITEMASK_XYZ:
1058
case TGSI_WRITEMASK_XY:
1061
case TGSI_WRITEMASK_X:
1065
R600_ERR("streamout: invalid register_mask, got: %x\n",
1066
so.output[i].register_mask);
1071
memset(&output, 0, sizeof(struct r600_bytecode_output));
1072
output.gpr = shader->output[so.output[i].register_index].gpr;
1073
output.elem_size = 0;
1074
output.array_base = buffer_offset[so.output[i].output_buffer];
1075
output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1076
output.burst_count = 1;
1078
output.array_size = 0;
1079
output.comp_mask = so.output[i].register_mask;
1080
if (ctx.bc->chip_class >= EVERGREEN) {
1081
switch (so.output[i].output_buffer) {
1083
output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0;
1086
output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1;
1089
output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2;
1092
output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3;
1096
switch (so.output[i].output_buffer) {
1098
output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0;
1101
output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1;
1104
output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2;
1107
output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3;
1111
r = r600_bytecode_add_output(ctx.bc, &output);
1115
buffer_offset[so.output[i].output_buffer] += comps;
1118
for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
1119
pipeshader->so_strides[i] = buffer_offset[i] * 4;
771
1123
/* export output */
773
for (i = 0, pos0 = 0; i < noutput; i++) {
774
memset(&output[i], 0, sizeof(struct r600_bc_output));
775
output[i + j].gpr = shader->output[i].gpr;
776
output[i + j].elem_size = 3;
777
output[i + j].swizzle_x = 0;
778
output[i + j].swizzle_y = 1;
779
output[i + j].swizzle_z = 2;
780
output[i + j].swizzle_w = 3;
781
output[i + j].burst_count = 1;
782
output[i + j].barrier = 1;
783
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
784
output[i + j].array_base = i - pos0;
785
output[i + j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1124
for (i = 0, j = 0; i < noutput; i++, j++) {
1125
memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1126
output[j].gpr = shader->output[i].gpr;
1127
output[j].elem_size = 3;
1128
output[j].swizzle_x = 0;
1129
output[j].swizzle_y = 1;
1130
output[j].swizzle_z = 2;
1131
output[j].swizzle_w = 3;
1132
output[j].burst_count = 1;
1133
output[j].barrier = 1;
1134
output[j].type = -1;
1135
output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
786
1136
switch (ctx.type) {
787
1137
case TGSI_PROCESSOR_VERTEX:
788
if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
789
output[i + j].array_base = 60;
790
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
791
/* position doesn't count in array_base */
794
if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
795
output[i + j].array_base = 61;
796
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
797
/* position doesn't count in array_base */
1138
switch (shader->output[i].name) {
1139
case TGSI_SEMANTIC_POSITION:
1140
output[j].array_base = next_pos_base++;
1141
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1144
case TGSI_SEMANTIC_PSIZE:
1145
output[j].array_base = next_pos_base++;
1146
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1148
case TGSI_SEMANTIC_CLIPVERTEX:
1151
case TGSI_SEMANTIC_CLIPDIST:
1152
output[j].array_base = next_pos_base++;
1153
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1154
/* spi_sid is 0 for clipdistance outputs that were generated
1155
* for clipvertex - we don't need to pass them to PS */
1156
if (shader->output[i].spi_sid) {
1158
/* duplicate it as PARAM to pass to the pixel shader */
1159
memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1160
output[j].array_base = next_param_base++;
1161
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1164
case TGSI_SEMANTIC_FOG:
1165
output[j].swizzle_y = 4; /* 0 */
1166
output[j].swizzle_z = 4; /* 0 */
1167
output[j].swizzle_w = 5; /* 1 */
801
1171
case TGSI_PROCESSOR_FRAGMENT:
802
1172
if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
803
output[i + j].array_base = shader->output[i].sid;
804
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
805
if (shader->fs_write_all && (shader->family >= CHIP_CEDAR)) {
806
for (j = 1; j < shader->nr_cbufs; j++) {
807
memset(&output[i + j], 0, sizeof(struct r600_bc_output));
808
output[i + j].gpr = shader->output[i].gpr;
809
output[i + j].elem_size = 3;
810
output[i + j].swizzle_x = 0;
811
output[i + j].swizzle_y = 1;
812
output[i + j].swizzle_z = 2;
813
output[i + j].swizzle_w = 3;
814
output[i + j].burst_count = 1;
815
output[i + j].barrier = 1;
816
output[i + j].array_base = shader->output[i].sid + j;
817
output[i + j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
818
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1173
output[j].array_base = next_pixel_base++;
1174
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1175
if (shader->fs_write_all && (rctx->chip_class >= EVERGREEN)) {
1176
for (k = 1; k < shader->nr_cbufs; k++) {
1178
memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1179
output[j].gpr = shader->output[i].gpr;
1180
output[j].elem_size = 3;
1181
output[j].swizzle_x = 0;
1182
output[j].swizzle_y = 1;
1183
output[j].swizzle_z = 2;
1184
output[j].swizzle_w = 3;
1185
output[j].burst_count = 1;
1186
output[j].barrier = 1;
1187
output[j].array_base = next_pixel_base++;
1188
output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1189
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
822
1192
} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
823
output[i + j].array_base = 61;
824
output[i + j].swizzle_x = 2;
825
output[i + j].swizzle_y = 7;
826
output[i + j].swizzle_z = output[i + j].swizzle_w = 7;
827
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1193
output[j].array_base = 61;
1194
output[j].swizzle_x = 2;
1195
output[j].swizzle_y = 7;
1196
output[j].swizzle_z = output[j].swizzle_w = 7;
1197
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
828
1198
} else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
829
output[i + j].array_base = 61;
830
output[i + j].swizzle_x = 7;
831
output[i + j].swizzle_y = 1;
832
output[i + j].swizzle_z = output[i + j].swizzle_w = 7;
833
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1199
output[j].array_base = 61;
1200
output[j].swizzle_x = 7;
1201
output[j].swizzle_y = 1;
1202
output[j].swizzle_z = output[j].swizzle_w = 7;
1203
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
835
1205
R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1216
if (output[j].type==-1) {
1217
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1218
output[j].array_base = next_param_base++;
847
1222
/* add fake param output for vertex shader if no param is exported */
848
if (ctx.type == TGSI_PROCESSOR_VERTEX) {
849
for (i = 0, pos0 = 0; i < noutput; i++) {
850
if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
856
memset(&output[i], 0, sizeof(struct r600_bc_output));
858
output[i].elem_size = 3;
859
output[i].swizzle_x = 0;
860
output[i].swizzle_y = 1;
861
output[i].swizzle_z = 2;
862
output[i].swizzle_w = 3;
863
output[i].burst_count = 1;
864
output[i].barrier = 1;
865
output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
866
output[i].array_base = 0;
867
output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1223
if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1224
memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1226
output[j].elem_size = 3;
1227
output[j].swizzle_x = 7;
1228
output[j].swizzle_y = 7;
1229
output[j].swizzle_z = 7;
1230
output[j].swizzle_w = 7;
1231
output[j].burst_count = 1;
1232
output[j].barrier = 1;
1233
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1234
output[j].array_base = 0;
1235
output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
871
1239
/* add fake pixel export */
872
if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
873
memset(&output[0], 0, sizeof(struct r600_bc_output));
875
output[0].elem_size = 3;
876
output[0].swizzle_x = 7;
877
output[0].swizzle_y = 7;
878
output[0].swizzle_z = 7;
879
output[0].swizzle_w = 7;
880
output[0].burst_count = 1;
881
output[0].barrier = 1;
882
output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
883
output[0].array_base = 0;
884
output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1240
if (ctx.type == TGSI_PROCESSOR_FRAGMENT && j == 0) {
1241
memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1243
output[j].elem_size = 3;
1244
output[j].swizzle_x = 7;
1245
output[j].swizzle_y = 7;
1246
output[j].swizzle_z = 7;
1247
output[j].swizzle_w = 7;
1248
output[j].burst_count = 1;
1249
output[j].barrier = 1;
1250
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1251
output[j].array_base = 0;
1252
output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
887
1258
/* set export done on last export of each type */
888
1259
for (i = noutput - 1, output_done = 0; i >= 0; i--) {
889
if (ctx.bc->chiprev < CHIPREV_CAYMAN) {
1260
if (ctx.bc->chip_class < CAYMAN) {
890
1261
if (i == (noutput - 1)) {
891
1262
output[i].end_of_program = 1;
1027
1398
static int tgsi_op2(struct r600_shader_ctx *ctx)
1029
return tgsi_op2_s(ctx, 0);
1400
return tgsi_op2_s(ctx, 0, 0);
1032
1403
static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1034
return tgsi_op2_s(ctx, 1);
1405
return tgsi_op2_s(ctx, 1, 0);
1408
static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1410
return tgsi_op2_s(ctx, 0, 1);
1413
static int tgsi_ineg(struct r600_shader_ctx *ctx)
1415
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1416
struct r600_bytecode_alu alu;
1418
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1420
for (i = 0; i < lasti + 1; i++) {
1422
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1424
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1425
alu.inst = ctx->inst_info->r600_opcode;
1427
alu.src[0].sel = V_SQ_ALU_SRC_0;
1429
r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1431
tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1436
r = r600_bytecode_add_alu(ctx->bc, &alu);
1037
1444
static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1039
1446
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1041
struct r600_bc_alu alu;
1448
struct r600_bytecode_alu alu;
1042
1449
int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1044
1451
for (i = 0 ; i < last_slot; i++) {
1045
memset(&alu, 0, sizeof(struct r600_bc_alu));
1452
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1046
1453
alu.inst = ctx->inst_info->r600_opcode;
1047
1454
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1048
r600_bc_src(&alu.src[j], &ctx->src[j], 0);
1455
r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1050
1457
tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1051
1458
alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1053
1460
if (i == last_slot - 1)
1055
r = r600_bc_add_alu(ctx->bc, &alu);
1462
r = r600_bytecode_add_alu(ctx->bc, &alu);
1463
1870
alu.dst.write = 0;
1464
r = r600_bc_add_alu(ctx->bc, &alu);
1871
r = r600_bytecode_add_alu(ctx->bc, &alu);
1469
1876
/* dst.z = exp(tmp.x) */
1470
memset(&alu, 0, sizeof(struct r600_bc_alu));
1877
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1471
1878
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1472
1879
alu.src[0].sel = ctx->temp_reg;
1473
1880
alu.src[0].chan = 0;
1474
1881
tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1476
r = r600_bc_add_alu(ctx->bc, &alu);
1883
r = r600_bytecode_add_alu(ctx->bc, &alu);
1482
1889
/* dst.x, <- 1.0 */
1483
memset(&alu, 0, sizeof(struct r600_bc_alu));
1890
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1484
1891
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1485
1892
alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1486
1893
alu.src[0].chan = 0;
1487
1894
tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1488
1895
alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1489
r = r600_bc_add_alu(ctx->bc, &alu);
1896
r = r600_bytecode_add_alu(ctx->bc, &alu);
1493
1900
/* dst.y = max(src.x, 0.0) */
1494
memset(&alu, 0, sizeof(struct r600_bc_alu));
1901
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1495
1902
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1496
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1903
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1497
1904
alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1498
1905
alu.src[1].chan = 0;
1499
1906
tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1500
1907
alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1501
r = r600_bc_add_alu(ctx->bc, &alu);
1908
r = r600_bytecode_add_alu(ctx->bc, &alu);
1505
1912
/* dst.w, <- 1.0 */
1506
memset(&alu, 0, sizeof(struct r600_bc_alu));
1913
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1507
1914
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1508
1915
alu.src[0].sel = V_SQ_ALU_SRC_1;
1509
1916
alu.src[0].chan = 0;
1510
1917
tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1511
1918
alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1513
r = r600_bc_add_alu(ctx->bc, &alu);
1920
r = r600_bytecode_add_alu(ctx->bc, &alu);
1593
2000
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1595
struct r600_bc_alu alu;
2002
struct r600_bytecode_alu alu;
1596
2003
int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1598
2005
for (i = 0; i < 3; i++) {
1599
memset(&alu, 0, sizeof(struct r600_bc_alu));
2006
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1600
2007
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1601
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2008
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1602
2009
alu.dst.sel = ctx->temp_reg;
1603
2010
alu.dst.chan = i;
1604
2011
alu.dst.write = 1;
1607
r = r600_bc_add_alu(ctx->bc, &alu);
2014
r = r600_bytecode_add_alu(ctx->bc, &alu);
1612
2019
/* b * LOG2(a) */
1613
memset(&alu, 0, sizeof(struct r600_bc_alu));
2020
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1614
2021
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1615
r600_bc_src(&alu.src[0], &ctx->src[1], 0);
2022
r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
1616
2023
alu.src[1].sel = ctx->temp_reg;
1617
2024
alu.dst.sel = ctx->temp_reg;
1618
2025
alu.dst.write = 1;
1620
r = r600_bc_add_alu(ctx->bc, &alu);
2027
r = r600_bytecode_add_alu(ctx->bc, &alu);
1624
2031
for (i = 0; i < last_slot; i++) {
1625
2032
/* POW(a,b) = EXP2(b * LOG2(a))*/
1626
memset(&alu, 0, sizeof(struct r600_bc_alu));
2033
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1627
2034
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1628
2035
alu.src[0].sel = ctx->temp_reg;
1641
2048
static int tgsi_pow(struct r600_shader_ctx *ctx)
1643
struct r600_bc_alu alu;
2050
struct r600_bytecode_alu alu;
1647
memset(&alu, 0, sizeof(struct r600_bc_alu));
2054
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1648
2055
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1649
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2056
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1650
2057
alu.dst.sel = ctx->temp_reg;
1651
2058
alu.dst.write = 1;
1653
r = r600_bc_add_alu(ctx->bc, &alu);
2060
r = r600_bytecode_add_alu(ctx->bc, &alu);
1656
2063
/* b * LOG2(a) */
1657
memset(&alu, 0, sizeof(struct r600_bc_alu));
2064
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1658
2065
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1659
r600_bc_src(&alu.src[0], &ctx->src[1], 0);
2066
r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
1660
2067
alu.src[1].sel = ctx->temp_reg;
1661
2068
alu.dst.sel = ctx->temp_reg;
1662
2069
alu.dst.write = 1;
1664
r = r600_bc_add_alu(ctx->bc, &alu);
2071
r = r600_bytecode_add_alu(ctx->bc, &alu);
1667
2074
/* POW(a,b) = EXP2(b * LOG2(a))*/
1668
memset(&alu, 0, sizeof(struct r600_bc_alu));
2075
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1669
2076
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1670
2077
alu.src[0].sel = ctx->temp_reg;
1671
2078
alu.dst.sel = ctx->temp_reg;
1672
2079
alu.dst.write = 1;
1674
r = r600_bc_add_alu(ctx->bc, &alu);
2081
r = r600_bytecode_add_alu(ctx->bc, &alu);
1677
2084
return tgsi_helper_tempx_replicate(ctx);
1680
2087
static int tgsi_ssg(struct r600_shader_ctx *ctx)
1682
2089
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1683
struct r600_bc_alu alu;
2090
struct r600_bytecode_alu alu;
1686
2093
/* tmp = (src > 0 ? 1 : src) */
1687
2094
for (i = 0; i < 4; i++) {
1688
memset(&alu, 0, sizeof(struct r600_bc_alu));
2095
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1689
2096
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1690
2097
alu.is_op3 = 1;
1692
2099
alu.dst.sel = ctx->temp_reg;
1693
2100
alu.dst.chan = i;
1695
r600_bc_src(&alu.src[0], &ctx->src[0], i);
2102
r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
1696
2103
alu.src[1].sel = V_SQ_ALU_SRC_1;
1697
r600_bc_src(&alu.src[2], &ctx->src[0], i);
2104
r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
1701
r = r600_bc_add_alu(ctx->bc, &alu);
2108
r = r600_bytecode_add_alu(ctx->bc, &alu);
1706
2113
/* dst = (-tmp > 0 ? -1 : tmp) */
1707
2114
for (i = 0; i < 4; i++) {
1708
memset(&alu, 0, sizeof(struct r600_bc_alu));
2115
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1709
2116
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1710
2117
alu.is_op3 = 1;
1711
2118
tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1939
2356
if (out_chan == i)
1940
2357
alu.dst.write = 1;
1941
r = r600_bc_add_alu(ctx->bc, &alu);
2358
r = r600_bytecode_add_alu(ctx->bc, &alu);
1948
memset(&alu, 0, sizeof(struct r600_bc_alu));
2365
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1949
2366
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1950
r600_bc_src(&alu.src[0], &ctx->src[0], 3);
2367
r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
1952
2369
alu.dst.sel = ctx->temp_reg;
1953
2370
alu.dst.chan = out_chan;
1955
2372
alu.dst.write = 1;
1956
r = r600_bc_add_alu(ctx->bc, &alu);
2373
r = r600_bytecode_add_alu(ctx->bc, &alu);
1961
2378
for (i = 0; i < 3; i++) {
1962
memset(&alu, 0, sizeof(struct r600_bc_alu));
2379
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1963
2380
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1964
2381
alu.src[0].sel = ctx->temp_reg;
1965
2382
alu.src[0].chan = out_chan;
1966
r600_bc_src(&alu.src[1], &ctx->src[0], i);
2383
r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1967
2384
alu.dst.sel = ctx->temp_reg;
1968
2385
alu.dst.chan = i;
1969
2386
alu.dst.write = 1;
1970
r = r600_bc_add_alu(ctx->bc, &alu);
2387
r = r600_bytecode_add_alu(ctx->bc, &alu);
1974
memset(&alu, 0, sizeof(struct r600_bc_alu));
2391
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1975
2392
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1976
2393
alu.src[0].sel = V_SQ_ALU_SRC_1;
1977
2394
alu.src[0].chan = 0;
2154
2578
tex.src_sel_w = 1;
2157
if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
2581
if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
2582
inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
2158
2583
tex.coord_type_x = 1;
2159
2584
tex.coord_type_y = 1;
2160
tex.coord_type_z = 1;
2161
tex.coord_type_w = 1;
2164
if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY) {
2165
tex.coord_type_z = 0;
2166
tex.src_sel_z = tex.src_sel_y;
2167
} else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY)
2168
tex.coord_type_z = 0;
2170
if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
2586
tex.coord_type_z = 1;
2587
tex.coord_type_w = 1;
2589
tex.offset_x = offset_x;
2590
tex.offset_y = offset_y;
2591
tex.offset_z = offset_z;
2593
/* Put the depth for comparison in W.
2594
* TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
2595
* Some instructions expect the depth in Z. */
2596
if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
2597
inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
2598
inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
2599
inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
2600
opcode != SQ_TEX_INST_SAMPLE_C_L &&
2601
opcode != SQ_TEX_INST_SAMPLE_C_LB) {
2171
2602
tex.src_sel_w = tex.src_sel_z;
2173
r = r600_bc_add_tex(ctx->bc, &tex);
2605
if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
2606
inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
2607
if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
2608
opcode == SQ_TEX_INST_SAMPLE_C_LB) {
2609
/* the array index is read from Y */
2610
tex.coord_type_y = 0;
2612
/* the array index is read from Z */
2613
tex.coord_type_z = 0;
2614
tex.src_sel_z = tex.src_sel_y;
2616
} else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
2617
inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
2618
/* the array index is read from Z */
2619
tex.coord_type_z = 0;
2621
r = r600_bytecode_add_tex(ctx->bc, &tex);
2784
3232
case TGSI_OPCODE_ARR:
2785
3233
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
3235
case TGSI_OPCODE_UARL:
3236
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
2792
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
3243
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2794
alu.dst.sel = ctx->ar_reg;
3245
alu.dst.sel = ctx->bc->ar_reg;
2795
3246
alu.dst.write = 1;
2796
r = r600_bc_add_alu(ctx->bc, &alu);
3247
r = r600_bytecode_add_alu(ctx->bc, &alu);
2800
/* TODO: Note that the MOVA can be avoided if we never use AR for
2801
* indexing non-CB registers in the current ALU clause. Similarly, we
2802
* need to load AR from ar_reg again if we started a new clause
2803
* between ARL and AR usage. The easy way to do that is to remove
2804
* the MOVA here, and load it for the first AR access after ar_reg
2805
* has been modified in each clause. */
2806
memset(&alu, 0, sizeof(struct r600_bc_alu));
2807
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2808
alu.src[0].sel = ctx->ar_reg;
2809
alu.src[0].chan = 0;
2811
r = r600_bc_add_alu(ctx->bc, &alu);
3251
ctx->bc->ar_loaded = 0;
2816
3254
static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2818
/* TODO from r600c, ar values don't persist between clauses */
2819
3256
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2820
struct r600_bc_alu alu;
3257
struct r600_bytecode_alu alu;
2823
3260
switch (inst->Instruction.Opcode) {
2824
3261
case TGSI_OPCODE_ARL:
2825
3262
memset(&alu, 0, sizeof(alu));
2826
3263
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
2827
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2828
alu.dst.sel = ctx->ar_reg;
3264
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3265
alu.dst.sel = ctx->bc->ar_reg;
2829
3266
alu.dst.write = 1;
2832
if ((r = r600_bc_add_alu(ctx->bc, &alu)))
3269
if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2835
3272
memset(&alu, 0, sizeof(alu));
2836
3273
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2837
alu.src[0].sel = ctx->ar_reg;
2838
alu.dst.sel = ctx->ar_reg;
3274
alu.src[0].sel = ctx->bc->ar_reg;
3275
alu.dst.sel = ctx->bc->ar_reg;
2839
3276
alu.dst.write = 1;
2842
if ((r = r600_bc_add_alu(ctx->bc, &alu)))
3279
if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2845
3282
case TGSI_OPCODE_ARR:
2846
3283
memset(&alu, 0, sizeof(alu));
2847
3284
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2848
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2849
alu.dst.sel = ctx->ar_reg;
2853
if ((r = r600_bc_add_alu(ctx->bc, &alu)))
3285
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3286
alu.dst.sel = ctx->bc->ar_reg;
3290
if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3293
case TGSI_OPCODE_UARL:
3294
memset(&alu, 0, sizeof(alu));
3295
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
3296
r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3297
alu.dst.sel = ctx->bc->ar_reg;
3301
if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3647
static int tgsi_umad(struct r600_shader_ctx *ctx)
3649
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3650
struct r600_bytecode_alu alu;
3652
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3655
for (i = 0; i < lasti + 1; i++) {
3656
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3659
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3662
alu.dst.sel = ctx->temp_reg;
3665
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
3666
for (j = 0; j < 2; j++) {
3667
r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3671
r = r600_bytecode_add_alu(ctx->bc, &alu);
3677
for (i = 0; i < lasti + 1; i++) {
3678
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3681
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3682
tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3684
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3686
alu.src[0].sel = ctx->temp_reg;
3687
alu.src[0].chan = i;
3689
r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
3693
r = r600_bytecode_add_alu(ctx->bc, &alu);
3198
3700
static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
3199
3701
{TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
3200
3702
{TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3291
3793
{TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3292
3794
{TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3293
3795
{TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3294
{TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3295
{TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3796
{TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
3797
{TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
3296
3798
{TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
3297
3799
{TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3299
3801
{88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3300
{TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3301
{TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3802
{TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
3803
{TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
3302
3804
{TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3303
{TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3805
{TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
3304
3806
{TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3305
{TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3306
{TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3807
{TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
3808
{TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
3307
3809
{TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3308
3810
{TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3309
3811
{TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3330
3832
{TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3332
3834
{118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3333
{TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3835
{TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
3334
3836
{TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3335
{TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3336
{TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3337
{TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3338
{TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3837
{TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
3838
{TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
3839
{TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_op2},
3840
{TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
3339
3841
{TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3340
{TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3341
{TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3342
{TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3343
{TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3842
{TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2},
3843
{TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
3844
{TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
3845
{TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
3344
3846
{TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3345
{TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3346
{TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3347
{TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3847
{TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
3848
{TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
3849
{TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
3348
3850
{TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3349
{TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3350
{TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3351
{TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3851
{TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2},
3852
{TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
3853
{TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
3352
3854
{TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3353
{TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3354
{TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3855
{TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
3856
{TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
3355
3857
{TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3356
3858
{TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3357
3859
{TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3358
3860
{TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3861
{TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
3862
{TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
3863
{TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
3864
{TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
3865
{TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
3866
{TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
3867
{TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
3868
{TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
3869
{TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
3870
{TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
3871
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
3872
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
3873
{TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
3874
{TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
3359
3875
{TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3449
3965
{TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3450
3966
{TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3451
3967
{TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3452
{TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3453
{TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3968
{TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
3969
{TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
3454
3970
{TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
3455
3971
{TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3457
3973
{88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3458
{TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3459
{TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3974
{TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
3975
{TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
3460
3976
{TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3461
{TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3977
{TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
3462
3978
{TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3463
{TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3464
{TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3979
{TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
3980
{TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
3465
3981
{TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3466
3982
{TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3467
3983
{TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3488
4004
{TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3490
4006
{118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3491
{TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4007
{TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
3492
4008
{TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3493
{TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3494
{TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3495
{TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3496
{TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4009
{TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4010
{TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4011
{TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
4012
{TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
3497
4013
{TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3498
{TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4014
{TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
3499
4015
{TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3500
{TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3501
{TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4016
{TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
4017
{TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
3502
4018
{TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3503
{TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3504
{TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3505
{TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4019
{TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
4020
{TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
4021
{TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
3506
4022
{TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3507
{TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3508
{TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3509
{TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4023
{TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
4024
{TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
4025
{TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
3510
4026
{TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3511
{TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3512
{TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4027
{TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
4028
{TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
3513
4029
{TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3514
4030
{TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3515
4031
{TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3516
4032
{TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4033
{TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4034
{TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4035
{TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4036
{TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4037
{TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4038
{TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4039
{TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4040
{TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4041
{TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4042
{TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4043
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4044
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4045
{TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
4046
{TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
3517
4047
{TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3616
4146
{TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3617
4147
{TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3618
4148
{TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3619
{TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4149
{TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
3620
4150
{TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3621
{TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3622
{TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4151
{TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4152
{TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
3623
4153
{TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3624
4154
{TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3625
4155
{TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3672
4202
{TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3673
4203
{TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3674
4204
{TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4205
{TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4206
{TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4207
{TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4208
{TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4209
{TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4210
{TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4211
{TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4212
{TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4213
{TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4214
{TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4215
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4216
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4217
{TGSI_OPCODE_UARL, 0, 0, tgsi_unsupported},
4218
{TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
3675
4219
{TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},