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* Copyright (C) 2009 Nicolai Haehnle.
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#ifndef RADEON_OPCODES_H
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#define RADEON_OPCODES_H
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* Opcodes understood by the Radeon compiler.
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RC_OPCODE_ILLEGAL_OPCODE,
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/** vec4 instruction: dst.c = abs(src0.c); */
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/** vec4 instruction: dst.c = src0.c + src1.c; */
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/** special instruction: load address register
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* dst.x = floor(src.x), where dst must be an address register */
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/** vec4 instruction: dst.c = ceil(src0.c) */
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/** vec4 instruction: dst.c = clamp(src0.c, src1.c, src2.c) */
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/** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
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/** vec4 instruction: dst.c = src2.c > 0.5 ? src0.c : src1.c */
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/** scalar instruction: dst = cos(src0.x) */
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/** special instruction: take vec4 partial derivative in X direction
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* dst.c = d src0.c / dx */
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/** special instruction: take vec4 partial derivative in Y direction
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* dst.c = d src0.c / dy */
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/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y */
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/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z */
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/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src0.w*src1.w */
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/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src1.w */
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/** special instruction, see ARB_fragment_program */
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/** scalar instruction: dst = 2**src0.x */
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/** special instruction, see ARB_vertex_program */
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/** vec4 instruction: dst.c = floor(src0.c) */
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/** vec4 instruction: dst.c = src0.c - floor(src0.c) */
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/** special instruction: stop execution if any component of src0 is negative */
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/** scalar instruction: dst = log_2(src0.x) */
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/** special instruction, see ARB_vertex_program */
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/** special instruction, see ARB_vertex_program */
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/** vec4 instruction: dst.c = src0.c*src1.c + (1 - src0.c)*src2.c */
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/** vec4 instruction: dst.c = src0.c*src1.c + src2.c */
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/** vec4 instruction: dst.c = max(src0.c, src1.c) */
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/** vec4 instruction: dst.c = min(src0.c, src1.c) */
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/** vec4 instruction: dst.c = src0.c */
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/** vec4 instruction: dst.c = src0.c*src1.c */
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/** scalar instruction: dst = src0.x ** src1.x */
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/** scalar instruction: dst = 1 / src0.x */
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/** scalar instruction: dst = 1 / sqrt(src0.x) */
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/** special instruction, see ARB_fragment_program */
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/** vec4 instruction: dst.c = (src0.c == src1.c) ? 1.0 : 0.0 */
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/** vec4 instruction: dst.c = 0.0 */
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/** vec4 instruction: dst.c = (src0.c >= src1.c) ? 1.0 : 0.0 */
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/** vec4 instruction: dst.c = (src0.c > src1.c) ? 1.0 : 0.0 */
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/** scalar instruction: dst = sin(src0.x) */
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/** vec4 instruction: dst.c = (src0.c <= src1.c) ? 1.0 : 0.0 */
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/** vec4 instruction: dst.c = (src0.c < src1.c) ? 1.0 : 0.0 */
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/** vec4 instruction: dst.c = (src0.c != src1.c) ? 1.0 : 0.0 */
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/** vec4 instruction: dst.c = (src0.c < 0 ?) -1 : ((src0.c > 0) : 1 : 0) */
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/** vec4 instruction: dst.c = src0.c - src1.c */
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/** vec4 instruction: dst.c = src0.c */
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/** special instruction, see ARB_fragment_program */
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/** branch instruction:
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* If src0.x != 0.0, continue with the next instruction;
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* otherwise, jump to matching RC_OPCODE_ELSE or RC_OPCODE_ENDIF.
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/** branch instruction: jump to matching RC_OPCODE_ENDIF */
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/** branch instruction: has no effect */
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/** special instruction, used in R300-R500 fragment program pair instructions
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* indicates that the result of the alpha operation shall be replicated
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* across all other channels */
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RC_OPCODE_REPL_ALPHA,
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/** special instruction, used in R300-R500 fragment programs
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* to indicate the start of a block of texture instructions that
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* can run simultaneously. */
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/** Stop execution of the shader (GLSL discard) */
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struct rc_opcode_info {
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/** true if the instruction reads from a texture.
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* \note This is false for the KIL instruction, even though KIL is
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* a texture instruction from a hardware point of view. */
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unsigned int HasTexture:1;
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unsigned int NumSrcRegs:2;
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unsigned int HasDstReg:1;
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/** true if this instruction affects control flow */
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unsigned int IsFlowControl:1;
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/** true if this is a vector instruction that operates on components in parallel
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* without any cross-component interaction */
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unsigned int IsComponentwise:1;
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/** true if this instruction sources only its operands X components
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* to compute one result which is smeared across all output channels */
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unsigned int IsStandardScalar:1;
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extern struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE];
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static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
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assert((unsigned int)opcode < MAX_RC_OPCODE);
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assert(rc_opcodes[opcode].Opcode == opcode);
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return &rc_opcodes[opcode];
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struct rc_instruction;
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void rc_compute_sources_for_writemask(
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const struct rc_instruction *inst,
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unsigned int writemask,
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unsigned int *srcmasks);
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#endif /* RADEON_OPCODES_H */