74
radeon_get_pointer(struct gl_context *ctx, struct gl_renderbuffer *rb,
77
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
73
#if defined(RADEON_R100)
74
static GLuint get_depth_z32(const struct radeon_renderbuffer * rrb,
77
GLuint ba, address = 0;
79
ba = (y >> 4) * (rrb->pitch >> 6) + (x >> 4);
81
address |= (x & 0x7) << 2;
82
address |= (y & 0x3) << 5;
83
address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;
84
address |= (ba & 3) << 8;
85
address |= (y & 0x8) << 7;
86
address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7;
87
address |= (ba & ~0x3) << 10;
91
static GLuint get_depth_z16(const struct radeon_renderbuffer * rrb,
94
GLuint ba, address = 0; /* a[0] = 0 */
96
ba = (y / 16) * (rrb->pitch >> 6) + (x / 32);
98
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
99
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
100
address |= (x & 0x8) << 4; /* a[7] = x[3] */
101
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
102
address |= (y & 0x8) << 7; /* a[10] = y[3] */
103
address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
104
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
109
#if defined(RADEON_R200)
110
static GLuint get_depth_z32(const struct radeon_renderbuffer * rrb,
116
b = (((y & 0x7ff) >> 4) * (rrb->pitch >> 7) + (x >> 5));
117
offset += (b >> 1) << 12;
118
offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
119
offset += ((y >> 2) & 0x3) << 9;
120
offset += ((x >> 2) & 0x1) << 8;
121
offset += ((x >> 3) & 0x3) << 6;
122
offset += ((y >> 1) & 0x1) << 5;
123
offset += ((x >> 1) & 0x1) << 4;
124
offset += (y & 0x1) << 3;
125
offset += (x & 0x1) << 2;
130
static GLuint get_depth_z16(const struct radeon_renderbuffer *rrb,
137
b = (((y >> 4) * (rrb->pitch >> 7) + (x >> 6)));
138
offset += (b >> 1) << 12;
139
offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
140
offset += ((y >> 2) & 0x3) << 9;
141
offset += ((x >> 3) & 0x1) << 8;
142
offset += ((x >> 4) & 0x3) << 6;
143
offset += ((x >> 2) & 0x1) << 5;
144
offset += ((y >> 1) & 0x1) << 4;
145
offset += ((x >> 1) & 0x1) << 3;
146
offset += (y & 0x1) << 2;
147
offset += (x & 0x1) << 1;
154
radeon_map_renderbuffer_s8z24(struct gl_context *ctx,
155
struct gl_renderbuffer *rb,
156
GLuint x, GLuint y, GLuint w, GLuint h,
161
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
162
uint32_t *untiled_s8z24_map, *tiled_s8z24_map;
164
int y_flip = (rb->Name == 0) ? -1 : 1;
165
int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0;
166
uint32_t pitch = w * rrb->cpp;
168
rrb->map_pitch = pitch;
170
rrb->map_buffer = malloc(w * h * 4);
171
ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
173
untiled_s8z24_map = rrb->map_buffer;
174
tiled_s8z24_map = rrb->bo->ptr;
176
for (uint32_t pix_y = 0; pix_y < h; ++ pix_y) {
177
for (uint32_t pix_x = 0; pix_x < w; ++pix_x) {
178
uint32_t flipped_y = y_flip * (int32_t)(y + pix_y) + y_bias;
179
uint32_t src_offset = get_depth_z32(rrb, x + pix_x, flipped_y);
180
uint32_t dst_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
181
untiled_s8z24_map[dst_offset/4] = tiled_s8z24_map[src_offset/4];
185
radeon_bo_unmap(rrb->bo);
187
*out_map = rrb->map_buffer;
188
*out_stride = rrb->map_pitch;
192
radeon_map_renderbuffer_z16(struct gl_context *ctx,
193
struct gl_renderbuffer *rb,
194
GLuint x, GLuint y, GLuint w, GLuint h,
199
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
200
uint16_t *untiled_z16_map, *tiled_z16_map;
202
int y_flip = (rb->Name == 0) ? -1 : 1;
203
int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0;
204
uint32_t pitch = w * rrb->cpp;
206
rrb->map_pitch = pitch;
208
rrb->map_buffer = malloc(w * h * 2);
209
ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
212
untiled_z16_map = rrb->map_buffer;
213
tiled_z16_map = rrb->bo->ptr;
215
for (uint32_t pix_y = 0; pix_y < h; ++ pix_y) {
216
for (uint32_t pix_x = 0; pix_x < w; ++pix_x) {
217
uint32_t flipped_y = y_flip * (int32_t)(y + pix_y) + y_bias;
218
uint32_t src_offset = get_depth_z16(rrb, x + pix_x, flipped_y);
219
uint32_t dst_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
220
untiled_z16_map[dst_offset/2] = tiled_z16_map[src_offset/2];
224
radeon_bo_unmap(rrb->bo);
226
*out_map = rrb->map_buffer;
227
*out_stride = rrb->map_pitch;
231
radeon_map_renderbuffer(struct gl_context *ctx,
232
struct gl_renderbuffer *rb,
233
GLuint x, GLuint y, GLuint w, GLuint h,
238
struct radeon_context *const rmesa = RADEON_CONTEXT(ctx);
239
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
242
int stride, flip_stride;
246
if (!rrb || !rrb->bo) {
252
rrb->map_mode = mode;
257
rrb->map_pitch = rrb->pitch;
259
ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp);
266
src_y = rrb->base.Base.Height - y - h;
269
/* Make a temporary buffer and blit the current contents of the renderbuffer
270
* out to it. This gives us linear access to the buffer, instead of having
271
* to do detiling in software.
274
rrb->map_pitch = rrb->pitch;
276
assert(!rrb->map_bo);
277
rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0,
278
rrb->map_pitch * h, 4,
279
RADEON_GEM_DOMAIN_GTT, 0);
281
ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset,
282
rb->Format, rrb->pitch / rrb->cpp,
283
rb->Width, rb->Height,
286
rb->Format, rrb->map_pitch / rrb->cpp,
293
ret = radeon_bo_map(rrb->map_bo, !!(mode & GL_MAP_WRITE_BIT));
296
map = rrb->map_bo->ptr;
300
*out_stride = rrb->map_pitch;
302
*out_map = map + (h - 1) * rrb->map_pitch;
303
*out_stride = -rrb->map_pitch;
308
/* sw fallback flush stuff */
309
if (radeon_bo_is_referenced_by_cs(rrb->bo, rmesa->cmdbuf.cs)) {
310
radeon_firevertices(rmesa);
313
if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) {
314
if (rb->Format == MESA_FORMAT_S8_Z24 || rb->Format == MESA_FORMAT_X8_Z24) {
315
radeon_map_renderbuffer_s8z24(ctx, rb, x, y, w, h,
316
mode, out_map, out_stride);
319
if (rb->Format == MESA_FORMAT_Z16) {
320
radeon_map_renderbuffer_z16(ctx, rb, x, y, w, h,
321
mode, out_map, out_stride);
326
ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
330
stride = rrb->map_pitch;
333
y = rb->Height - 1 - y;
334
flip_stride = -stride;
336
flip_stride = stride;
337
map += rrb->draw_offset;
341
map += (int)y * stride;
344
*out_stride = flip_stride;
348
radeon_unmap_renderbuffer_s8z24(struct gl_context *ctx,
349
struct gl_renderbuffer *rb)
351
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
353
if (!rrb->map_buffer)
356
if (rrb->map_mode & GL_MAP_WRITE_BIT) {
357
uint32_t *untiled_s8z24_map = rrb->map_buffer;
358
uint32_t *tiled_s8z24_map;
359
int y_flip = (rb->Name == 0) ? -1 : 1;
360
int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0;
362
radeon_bo_map(rrb->bo, 1);
364
tiled_s8z24_map = rrb->bo->ptr;
366
for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) {
367
for (uint32_t pix_x = 0; pix_x < rrb->map_w; pix_x++) {
368
uint32_t flipped_y = y_flip * (int32_t)(pix_y + rrb->map_y) + y_bias;
369
uint32_t dst_offset = get_depth_z32(rrb, rrb->map_x + pix_x, flipped_y);
370
uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
371
tiled_s8z24_map[dst_offset/4] = untiled_s8z24_map[src_offset/4];
374
radeon_bo_unmap(rrb->bo);
376
free(rrb->map_buffer);
377
rrb->map_buffer = NULL;
381
radeon_unmap_renderbuffer_z16(struct gl_context *ctx,
382
struct gl_renderbuffer *rb)
384
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
386
if (!rrb->map_buffer)
389
if (rrb->map_mode & GL_MAP_WRITE_BIT) {
390
uint16_t *untiled_z16_map = rrb->map_buffer;
391
uint16_t *tiled_z16_map;
392
int y_flip = (rb->Name == 0) ? -1 : 1;
393
int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0;
395
radeon_bo_map(rrb->bo, 1);
397
tiled_z16_map = rrb->bo->ptr;
399
for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) {
400
for (uint32_t pix_x = 0; pix_x < rrb->map_w; pix_x++) {
401
uint32_t flipped_y = y_flip * (int32_t)(pix_y + rrb->map_y) + y_bias;
402
uint32_t dst_offset = get_depth_z16(rrb, rrb->map_x + pix_x, flipped_y);
403
uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
404
tiled_z16_map[dst_offset/2] = untiled_z16_map[src_offset/2];
407
radeon_bo_unmap(rrb->bo);
409
free(rrb->map_buffer);
410
rrb->map_buffer = NULL;
415
radeon_unmap_renderbuffer(struct gl_context *ctx,
416
struct gl_renderbuffer *rb)
418
struct radeon_context *const rmesa = RADEON_CONTEXT(ctx);
419
struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
422
if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) {
423
if (rb->Format == MESA_FORMAT_S8_Z24 || rb->Format == MESA_FORMAT_X8_Z24) {
424
radeon_unmap_renderbuffer_s8z24(ctx, rb);
427
if (rb->Format == MESA_FORMAT_Z16) {
428
radeon_unmap_renderbuffer_z16(ctx, rb);
435
radeon_bo_unmap(rrb->bo);
439
radeon_bo_unmap(rrb->map_bo);
441
if (rrb->map_mode & GL_MAP_WRITE_BIT) {
442
ok = rmesa->vtbl.blit(ctx, rrb->map_bo, 0,
443
rb->Format, rrb->map_pitch / rrb->cpp,
444
rrb->map_w, rrb->map_h,
446
rrb->bo, rrb->draw_offset,
447
rb->Format, rrb->pitch / rrb->cpp,
448
rb->Width, rb->Height,
449
rrb->map_x, rrb->map_y,
450
rrb->map_w, rrb->map_h,
455
radeon_bo_unref(rrb->map_bo);
85
461
* Called via glRenderbufferStorageEXT() to set the format and allocate
327
_mesa_init_renderbuffer(&rrb->base, 0);
328
rrb->base.ClassID = RADEON_RB_CLASS;
330
rrb->base.Format = format;
333
case MESA_FORMAT_RGB565:
334
assert(_mesa_little_endian());
335
rrb->base.DataType = GL_UNSIGNED_BYTE;
336
rrb->base._BaseFormat = GL_RGB;
338
case MESA_FORMAT_RGB565_REV:
339
assert(!_mesa_little_endian());
340
rrb->base.DataType = GL_UNSIGNED_BYTE;
341
rrb->base._BaseFormat = GL_RGB;
343
case MESA_FORMAT_XRGB8888:
344
assert(_mesa_little_endian());
345
rrb->base.DataType = GL_UNSIGNED_BYTE;
346
rrb->base._BaseFormat = GL_RGB;
348
case MESA_FORMAT_XRGB8888_REV:
349
assert(!_mesa_little_endian());
350
rrb->base.DataType = GL_UNSIGNED_BYTE;
351
rrb->base._BaseFormat = GL_RGB;
353
case MESA_FORMAT_ARGB8888:
354
assert(_mesa_little_endian());
355
rrb->base.DataType = GL_UNSIGNED_BYTE;
356
rrb->base._BaseFormat = GL_RGBA;
358
case MESA_FORMAT_ARGB8888_REV:
359
assert(!_mesa_little_endian());
360
rrb->base.DataType = GL_UNSIGNED_BYTE;
361
rrb->base._BaseFormat = GL_RGBA;
364
rrb->base.DataType = GL_UNSIGNED_BYTE;
365
rrb->base._BaseFormat = GL_STENCIL_INDEX;
367
case MESA_FORMAT_Z16:
368
rrb->base.DataType = GL_UNSIGNED_SHORT;
369
rrb->base._BaseFormat = GL_DEPTH_COMPONENT;
371
case MESA_FORMAT_X8_Z24:
372
rrb->base.DataType = GL_UNSIGNED_INT;
373
rrb->base._BaseFormat = GL_DEPTH_COMPONENT;
375
case MESA_FORMAT_S8_Z24:
376
rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
377
rrb->base._BaseFormat = GL_DEPTH_STENCIL;
380
fprintf(stderr, "%s: Unknown format %s\n",
381
__FUNCTION__, _mesa_get_format_name(format));
382
_mesa_delete_renderbuffer(&rrb->base);
687
rb = &rrb->base.Base;
689
_mesa_init_renderbuffer(rb, 0);
690
rb->ClassID = RADEON_RB_CLASS;
692
rb->_BaseFormat = _mesa_get_format_base_format(format);
693
rb->InternalFormat = _mesa_get_format_base_format(format);
386
695
rrb->dPriv = driDrawPriv;
387
rrb->base.InternalFormat = _mesa_get_format_base_format(format);
389
rrb->base.Delete = radeon_delete_renderbuffer;
390
rrb->base.AllocStorage = radeon_alloc_window_storage;
391
rrb->base.GetPointer = radeon_get_pointer;
697
rb->Delete = radeon_delete_renderbuffer;
698
rb->AllocStorage = radeon_alloc_window_storage;
456
765
radeon_update_wrapper(struct gl_context *ctx, struct radeon_renderbuffer *rrb,
457
766
struct gl_texture_image *texImage)
768
struct gl_renderbuffer *rb = &rrb->base.Base;
459
770
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
460
771
"%s(%p, rrb %p, texImage %p, texFormat %s) \n",
461
772
__func__, ctx, rrb, texImage, _mesa_get_format_name(texImage->TexFormat));
463
switch (texImage->TexFormat) {
464
case MESA_FORMAT_RGBA8888:
465
case MESA_FORMAT_RGBA8888_REV:
466
case MESA_FORMAT_ARGB8888:
467
case MESA_FORMAT_ARGB8888_REV:
468
case MESA_FORMAT_XRGB8888:
469
case MESA_FORMAT_XRGB8888_REV:
470
case MESA_FORMAT_RGB565:
471
case MESA_FORMAT_RGB565_REV:
472
case MESA_FORMAT_RGBA5551:
473
case MESA_FORMAT_ARGB1555:
474
case MESA_FORMAT_ARGB1555_REV:
475
case MESA_FORMAT_ARGB4444:
476
case MESA_FORMAT_ARGB4444_REV:
477
rrb->base.DataType = GL_UNSIGNED_BYTE;
479
case MESA_FORMAT_Z16:
480
rrb->base.DataType = GL_UNSIGNED_SHORT;
482
case MESA_FORMAT_X8_Z24:
483
rrb->base.DataType = GL_UNSIGNED_INT;
485
case MESA_FORMAT_S8_Z24:
486
rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
489
_mesa_problem(ctx, "Unexpected texture format in radeon_update_wrapper()");
492
774
rrb->cpp = _mesa_get_format_bytes(texImage->TexFormat);
493
775
rrb->pitch = texImage->Width * rrb->cpp;
494
rrb->base.Format = texImage->TexFormat;
495
rrb->base.InternalFormat = texImage->InternalFormat;
496
rrb->base._BaseFormat = _mesa_base_fbo_format(ctx, rrb->base.InternalFormat);
497
rrb->base.Width = texImage->Width;
498
rrb->base.Height = texImage->Height;
499
rrb->base.Delete = radeon_delete_renderbuffer;
500
rrb->base.AllocStorage = radeon_nop_alloc_storage;
776
rb->Format = texImage->TexFormat;
777
rb->InternalFormat = texImage->InternalFormat;
778
rb->_BaseFormat = _mesa_base_fbo_format(ctx, rb->InternalFormat);
779
rb->Width = texImage->Width;
780
rb->Height = texImage->Height;
781
rb->Delete = radeon_delete_renderbuffer;
782
rb->AllocStorage = radeon_nop_alloc_storage;