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#ifndef COMMON_CMDBUF_H
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#define COMMON_CMDBUF_H
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#include "radeon_bocs_wrapper.h"
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GLboolean rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
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int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
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int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller);
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void rcommonInitCmdBuf(radeonContextPtr rmesa);
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void rcommonDestroyCmdBuf(radeonContextPtr rmesa);
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void rcommonBeginBatch(radeonContextPtr rmesa,
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/* +r6/r7 : code here moved */
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#define CP_PACKET2 (2 << 30)
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#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
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#define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
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#define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
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* Every function writing to the command buffer needs to declare this
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* to get the necessary local variables.
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#define BATCH_LOCALS(rmesa) \
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const radeonContextPtr b_l_rmesa = rmesa
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* Prepare writing n dwords to the command buffer,
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* including producing any necessary state emits on buffer wraparound.
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#define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__)
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* Same as BEGIN_BATCH, but do not cause automatic state emits.
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#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__)
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* Write one dword to the command buffer.
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#define OUT_BATCH(data) \
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radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\
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* Write a relocated dword to the command buffer.
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#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \
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int __offset = (offset); \
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if (0 && __offset) { \
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fprintf(stderr, "(%s:%s:%d) offset : %d\n", \
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__FILE__, __FUNCTION__, __LINE__, __offset); \
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radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset); \
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radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \
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if (!b_l_rmesa->radeonScreen->kernel_mm) \
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b_l_rmesa->cmdbuf.cs->section_cdw += 2; \
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* Write n dwords from ptr to the command buffer.
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#define OUT_BATCH_TABLE(ptr,n) \
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radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\
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* Finish writing dwords to the command buffer.
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* The number of (direct or indirect) OUT_BATCH calls between the previous
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* BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time.
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radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\
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* After the last END_BATCH() of rendering, this indicates that flushing
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* the command buffer now is okay.
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#define COMMIT_BATCH() \
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/** Single register write to command buffer; requires 2 dwords. */
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#define OUT_BATCH_REGVAL(reg, val) \
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OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
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/** Continuous register range write to command buffer; requires 1 dword,
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* expects count dwords afterwards for register contents. */
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#define OUT_BATCH_REGSEQ(reg, count) \
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OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
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/** Write a 32 bit float to the ring; requires 1 dword. */
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#define OUT_BATCH_FLOAT32(f) \
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OUT_BATCH(radeonPackFloat32((f)))
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/* +r6/r7 : code here moved */
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/* Fire the buffered vertices no matter what.
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static INLINE void radeon_firevertices(radeonContextPtr radeon)
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if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
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radeon->glCtx->Driver.Flush(radeon->glCtx); /* +r6/r7 */