24
24
*****************************************************************************/
26
#define insn6510 insn6502
27
#define OP(nn) INLINE void m6510_##nn(m6502_Regs *cpustate)
29
/*****************************************************************************
30
*****************************************************************************
32
* plain vanilla 6502 opcodes
34
*****************************************************************************
35
* op temp cycles rdmem opc wrmem ********************/
37
OP(00) { BRK; } /* 7 BRK */
38
OP(20) { JSR; } /* 6 JSR */
39
OP(40) { RTI; } /* 6 RTI */
40
OP(60) { RTS; } /* 6 RTS */
41
OP(80) { RDOPARG(); NOP; } /* 2 NOP IMM */
42
OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */
43
OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */
44
OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */
46
OP(10) { BPL; } /* 2-4 BPL REL */
47
OP(30) { BMI; } /* 2-4 BMI REL */
48
OP(50) { BVC; } /* 2-4 BVC REL */
49
OP(70) { BVS; } /* 2-4 BVS REL */
50
OP(90) { BCC; } /* 2-4 BCC REL */
51
OP(b0) { BCS; } /* 2-4 BCS REL */
52
OP(d0) { BNE; } /* 2-4 BNE REL */
53
OP(f0) { BEQ; } /* 2-4 BEQ REL */
55
OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */
56
OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */
57
OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */
58
OP(61) { int tmp; RD_IDX; ADC; } /* 6 ADC IDX */
59
OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */
60
OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */
61
OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */
62
OP(e1) { int tmp; RD_IDX; SBC; } /* 6 SBC IDX */
64
OP(11) { int tmp; RD_IDY_P; ORA; } /* 5 ORA IDY page penalty */
65
OP(31) { int tmp; RD_IDY_P; AND; } /* 5 AND IDY page penalty */
66
OP(51) { int tmp; RD_IDY_P; EOR; } /* 5 EOR IDY page penalty */
67
OP(71) { int tmp; RD_IDY_P; ADC; } /* 5 ADC IDY page penalty */
68
OP(91) { int tmp; STA; WR_IDY_NP; } /* 6 STA IDY */
69
OP(b1) { int tmp; RD_IDY_P; LDA; } /* 5 LDA IDY page penalty */
70
OP(d1) { int tmp; RD_IDY_P; CMP; } /* 5 CMP IDY page penalty */
71
OP(f1) { int tmp; RD_IDY_P; SBC; } /* 5 SBC IDY page penalty */
73
OP(02) { KIL; } /* 1 KIL */
74
OP(22) { KIL; } /* 1 KIL */
75
OP(42) { KIL; } /* 1 KIL */
76
OP(62) { KIL; } /* 1 KIL */
77
OP(82) { RDOPARG(); NOP; } /* 2 NOP IMM */
78
OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
79
OP(c2) { RDOPARG(); NOP; } /* 2 NOP IMM */
80
OP(e2) { RDOPARG(); NOP; } /* 2 NOP IMM */
82
OP(12) { KIL; } /* 1 KIL */
83
OP(32) { KIL; } /* 1 KIL */
84
OP(52) { KIL; } /* 1 KIL */
85
OP(72) { KIL; } /* 1 KIL */
86
OP(92) { KIL; } /* 1 KIL */
87
OP(b2) { KIL; } /* 1 KIL */
88
OP(d2) { KIL; } /* 1 KIL */
89
OP(f2) { KIL; } /* 1 KIL */
91
OP(03) { int tmp; RD_IDX; WB_EA; SLO; WB_EA; } /* 7 SLO IDX */
92
OP(23) { int tmp; RD_IDX; WB_EA; RLA; WB_EA; } /* 7 RLA IDX */
93
OP(43) { int tmp; RD_IDX; WB_EA; SRE; WB_EA; } /* 7 SRE IDX */
94
OP(63) { int tmp; RD_IDX; WB_EA; RRA; WB_EA; } /* 7 RRA IDX */
95
OP(83) { int tmp; SAX; WR_IDX; } /* 6 SAX IDX */
96
OP(a3) { int tmp; RD_IDX; LAX; } /* 6 LAX IDX */
97
OP(c3) { int tmp; RD_IDX; WB_EA; DCP; WB_EA; } /* 7 DCP IDX */
98
OP(e3) { int tmp; RD_IDX; WB_EA; ISB; WB_EA; } /* 7 ISB IDX */
100
OP(13) { int tmp; RD_IDY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO IDY */
101
OP(33) { int tmp; RD_IDY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA IDY */
102
OP(53) { int tmp; RD_IDY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE IDY */
103
OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA IDY */
104
OP(93) { int tmp; EA_IDY_NP; SAH; WB_EA; } /* 5 SAH IDY */
105
OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */
106
OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */
107
OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */
109
OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
110
OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */
111
OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
112
OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
113
OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */
114
OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */
115
OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */
116
OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */
118
OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
119
OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
120
OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
121
OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
122
OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */
123
OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */
124
OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
125
OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
127
OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */
128
OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */
129
OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */
130
OP(65) { int tmp; RD_ZPG; ADC; } /* 3 ADC ZPG */
131
OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */
132
OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */
133
OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */
134
OP(e5) { int tmp; RD_ZPG; SBC; } /* 3 SBC ZPG */
136
OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */
137
OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */
138
OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */
139
OP(75) { int tmp; RD_ZPX; ADC; } /* 4 ADC ZPX */
140
OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */
141
OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */
142
OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */
143
OP(f5) { int tmp; RD_ZPX; SBC; } /* 4 SBC ZPX */
145
OP(06) { int tmp; RD_ZPG; WB_EA; ASL; WB_EA; } /* 5 ASL ZPG */
146
OP(26) { int tmp; RD_ZPG; WB_EA; ROL; WB_EA; } /* 5 ROL ZPG */
147
OP(46) { int tmp; RD_ZPG; WB_EA; LSR; WB_EA; } /* 5 LSR ZPG */
148
OP(66) { int tmp; RD_ZPG; WB_EA; ROR; WB_EA; } /* 5 ROR ZPG */
149
OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */
150
OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */
151
OP(c6) { int tmp; RD_ZPG; WB_EA; DEC; WB_EA; } /* 5 DEC ZPG */
152
OP(e6) { int tmp; RD_ZPG; WB_EA; INC; WB_EA; } /* 5 INC ZPG */
154
OP(16) { int tmp; RD_ZPX; WB_EA; ASL; WB_EA; } /* 6 ASL ZPX */
155
OP(36) { int tmp; RD_ZPX; WB_EA; ROL; WB_EA; } /* 6 ROL ZPX */
156
OP(56) { int tmp; RD_ZPX; WB_EA; LSR; WB_EA; } /* 6 LSR ZPX */
157
OP(76) { int tmp; RD_ZPX; WB_EA; ROR; WB_EA; } /* 6 ROR ZPX */
158
OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */
159
OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */
160
OP(d6) { int tmp; RD_ZPX; WB_EA; DEC; WB_EA; } /* 6 DEC ZPX */
161
OP(f6) { int tmp; RD_ZPX; WB_EA; INC; WB_EA; } /* 6 INC ZPX */
163
OP(07) { int tmp; RD_ZPG; WB_EA; SLO; WB_EA; } /* 5 SLO ZPG */
164
OP(27) { int tmp; RD_ZPG; WB_EA; RLA; WB_EA; } /* 5 RLA ZPG */
165
OP(47) { int tmp; RD_ZPG; WB_EA; SRE; WB_EA; } /* 5 SRE ZPG */
166
OP(67) { int tmp; RD_ZPG; WB_EA; RRA; WB_EA; } /* 5 RRA ZPG */
167
OP(87) { int tmp; SAX; WR_ZPG; } /* 3 SAX ZPG */
168
OP(a7) { int tmp; RD_ZPG; LAX; } /* 3 LAX ZPG */
169
OP(c7) { int tmp; RD_ZPG; WB_EA; DCP; WB_EA; } /* 5 DCP ZPG */
170
OP(e7) { int tmp; RD_ZPG; WB_EA; ISB; WB_EA; } /* 5 ISB ZPG */
172
OP(17) { int tmp; RD_ZPX; WB_EA; SLO; WB_EA; } /* 6 SLO ZPX */
173
OP(37) { int tmp; RD_ZPX; WB_EA; RLA; WB_EA; } /* 6 RLA ZPX */
174
OP(57) { int tmp; RD_ZPX; WB_EA; SRE; WB_EA; } /* 6 SRE ZPX */
175
OP(77) { int tmp; RD_ZPX; WB_EA; RRA; WB_EA; } /* 6 RRA ZPX */
176
OP(97) { int tmp; SAX; WR_ZPY; } /* 4 SAX ZPY */
177
OP(b7) { int tmp; RD_ZPY; LAX; } /* 4 LAX ZPY */
178
OP(d7) { int tmp; RD_ZPX; WB_EA; DCP; WB_EA; } /* 6 DCP ZPX */
179
OP(f7) { int tmp; RD_ZPX; WB_EA; ISB; WB_EA; } /* 6 ISB ZPX */
181
OP(08) { RD_DUM; PHP; } /* 3 PHP */
182
OP(28) { RD_DUM; PLP; } /* 4 PLP */
183
OP(48) { RD_DUM; PHA; } /* 3 PHA */
184
OP(68) { RD_DUM; PLA; } /* 4 PLA */
185
OP(88) { RD_DUM; DEY; } /* 2 DEY */
186
OP(a8) { RD_DUM; TAY; } /* 2 TAY */
187
OP(c8) { RD_DUM; INY; } /* 2 INY */
188
OP(e8) { RD_DUM; INX; } /* 2 INX */
190
OP(18) { RD_DUM; CLC; } /* 2 CLC */
191
OP(38) { RD_DUM; SEC; } /* 2 SEC */
192
OP(58) { RD_DUM; CLI; } /* 2 CLI */
193
OP(78) { RD_DUM; SEI; } /* 2 SEI */
194
OP(98) { RD_DUM; TYA; } /* 2 TYA */
195
OP(b8) { RD_DUM; CLV; } /* 2 CLV */
196
OP(d8) { RD_DUM; CLD; } /* 2 CLD */
197
OP(f8) { RD_DUM; SED; } /* 2 SED */
199
OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */
200
OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */
201
OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */
202
OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */
203
OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
204
OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */
205
OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */
206
OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */
208
OP(19) { int tmp; RD_ABY_P; ORA; } /* 4 ORA ABY page penalty */
209
OP(39) { int tmp; RD_ABY_P; AND; } /* 4 AND ABY page penalty */
210
OP(59) { int tmp; RD_ABY_P; EOR; } /* 4 EOR ABY page penalty */
211
OP(79) { int tmp; RD_ABY_P; ADC; } /* 4 ADC ABY page penalty */
212
OP(99) { int tmp; STA; WR_ABY_NP; } /* 5 STA ABY */
213
OP(b9) { int tmp; RD_ABY_P; LDA; } /* 4 LDA ABY page penalty */
214
OP(d9) { int tmp; RD_ABY_P; CMP; } /* 4 CMP ABY page penalty */
215
OP(f9) { int tmp; RD_ABY_P; SBC; } /* 4 SBC ABY page penalty */
217
OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */
218
OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */
219
OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */
220
OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */
221
OP(8a) { RD_DUM; TXA; } /* 2 TXA */
222
OP(aa) { RD_DUM; TAX; } /* 2 TAX */
223
OP(ca) { RD_DUM; DEX; } /* 2 DEX */
224
OP(ea) { RD_DUM; NOP; } /* 2 NOP */
226
OP(1a) { RD_DUM; NOP; } /* 2 NOP */
227
OP(3a) { RD_DUM; NOP; } /* 2 NOP */
228
OP(5a) { RD_DUM; NOP; } /* 2 NOP */
229
OP(7a) { RD_DUM; NOP; } /* 2 NOP */
230
OP(9a) { RD_DUM; TXS; } /* 2 TXS */
231
OP(ba) { RD_DUM; TSX; } /* 2 TSX */
232
OP(da) { RD_DUM; NOP; } /* 2 NOP */
233
OP(fa) { RD_DUM; NOP; } /* 2 NOP */
235
OP(0b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */
236
OP(2b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */
237
OP(4b) { int tmp; RD_IMM; ASR; WB_ACC; } /* 2 ASR IMM */
238
OP(6b) { int tmp; RD_IMM; ARR; WB_ACC; } /* 2 ARR IMM */
239
OP(8b) { int tmp; RD_IMM; AXA; } /* 2 AXA IMM */
240
OP(ab) { int tmp; RD_IMM; OAL_6510; } /* 2 OAL IMM */
241
OP(cb) { int tmp; RD_IMM; ASX; } /* 2 ASX IMM */
242
OP(eb) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */
244
OP(1b) { int tmp; RD_ABY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABY */
245
OP(3b) { int tmp; RD_ABY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABY */
246
OP(5b) { int tmp; RD_ABY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABY */
247
OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABY */
248
OP(9b) { int tmp; EA_ABY_NP; SSH; WB_EA; } /* 5 SSH ABY */
249
OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */
250
OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */
251
OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */
253
OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */
254
OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */
255
OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */
256
OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */
257
OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */
258
OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */
259
OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */
260
OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */
262
OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
263
OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
264
OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
265
OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
266
OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */
267
OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */
268
OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
269
OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
271
OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */
272
OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */
273
OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */
274
OP(6d) { int tmp; RD_ABS; ADC; } /* 4 ADC ABS */
275
OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */
276
OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */
277
OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */
278
OP(ed) { int tmp; RD_ABS; SBC; } /* 4 SBC ABS */
280
OP(1d) { int tmp; RD_ABX_P; ORA; } /* 4 ORA ABX page penalty */
281
OP(3d) { int tmp; RD_ABX_P; AND; } /* 4 AND ABX page penalty */
282
OP(5d) { int tmp; RD_ABX_P; EOR; } /* 4 EOR ABX page penalty */
283
OP(7d) { int tmp; RD_ABX_P; ADC; } /* 4 ADC ABX page penalty */
284
OP(9d) { int tmp; STA; WR_ABX_NP; } /* 5 STA ABX */
285
OP(bd) { int tmp; RD_ABX_P; LDA; } /* 4 LDA ABX page penalty */
286
OP(dd) { int tmp; RD_ABX_P; CMP; } /* 4 CMP ABX page penalty */
287
OP(fd) { int tmp; RD_ABX_P; SBC; } /* 4 SBC ABX page penalty */
289
OP(0e) { int tmp; RD_ABS; WB_EA; ASL; WB_EA; } /* 6 ASL ABS */
290
OP(2e) { int tmp; RD_ABS; WB_EA; ROL; WB_EA; } /* 6 ROL ABS */
291
OP(4e) { int tmp; RD_ABS; WB_EA; LSR; WB_EA; } /* 6 LSR ABS */
292
OP(6e) { int tmp; RD_ABS; WB_EA; ROR; WB_EA; } /* 6 ROR ABS */
293
OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */
294
OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */
295
OP(ce) { int tmp; RD_ABS; WB_EA; DEC; WB_EA; } /* 6 DEC ABS */
296
OP(ee) { int tmp; RD_ABS; WB_EA; INC; WB_EA; } /* 6 INC ABS */
298
OP(1e) { int tmp; RD_ABX_NP; WB_EA; ASL; WB_EA; } /* 7 ASL ABX */
299
OP(3e) { int tmp; RD_ABX_NP; WB_EA; ROL; WB_EA; } /* 7 ROL ABX */
300
OP(5e) { int tmp; RD_ABX_NP; WB_EA; LSR; WB_EA; } /* 7 LSR ABX */
301
OP(7e) { int tmp; RD_ABX_NP; WB_EA; ROR; WB_EA; } /* 7 ROR ABX */
302
OP(9e) { int tmp; EA_ABY_NP; SXH; WB_EA; } /* 5 SXH ABY */
303
OP(be) { int tmp; RD_ABY_P; LDX; } /* 4 LDX ABY page penalty */
304
OP(de) { int tmp; RD_ABX_NP; WB_EA; DEC; WB_EA; } /* 7 DEC ABX */
305
OP(fe) { int tmp; RD_ABX_NP; WB_EA; INC; WB_EA; } /* 7 INC ABX */
307
OP(0f) { int tmp; RD_ABS; WB_EA; SLO; WB_EA; } /* 6 SLO ABS */
308
OP(2f) { int tmp; RD_ABS; WB_EA; RLA; WB_EA; } /* 6 RLA ABS */
309
OP(4f) { int tmp; RD_ABS; WB_EA; SRE; WB_EA; } /* 6 SRE ABS */
310
OP(6f) { int tmp; RD_ABS; WB_EA; RRA; WB_EA; } /* 6 RRA ABS */
311
OP(8f) { int tmp; SAX; WR_ABS; } /* 4 SAX ABS */
312
OP(af) { int tmp; RD_ABS; LAX; } /* 4 LAX ABS */
313
OP(cf) { int tmp; RD_ABS; WB_EA; DCP; WB_EA; } /* 6 DCP ABS */
314
OP(ef) { int tmp; RD_ABS; WB_EA; ISB; WB_EA; } /* 6 ISB ABS */
316
OP(1f) { int tmp; RD_ABX_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABX */
317
OP(3f) { int tmp; RD_ABX_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABX */
318
OP(5f) { int tmp; RD_ABX_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABX */
319
OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABX */
320
OP(9f) { int tmp; EA_ABY_NP; SAH; WB_EA; } /* 5 SAH ABY */
321
OP(bf) { int tmp; RD_ABY_P; LAX; } /* 4 LAX ABY page penalty */
322
OP(df) { int tmp; RD_ABX_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABX */
323
OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */
325
/* and here's the array of function pointers */
327
static void (*const insn6510[0x100])(m6502_Regs *cpustate) = {
328
m6510_00,m6510_01,m6510_02,m6510_03,m6510_04,m6510_05,m6510_06,m6510_07,
329
m6510_08,m6510_09,m6510_0a,m6510_0b,m6510_0c,m6510_0d,m6510_0e,m6510_0f,
330
m6510_10,m6510_11,m6510_12,m6510_13,m6510_14,m6510_15,m6510_16,m6510_17,
331
m6510_18,m6510_19,m6510_1a,m6510_1b,m6510_1c,m6510_1d,m6510_1e,m6510_1f,
332
m6510_20,m6510_21,m6510_22,m6510_23,m6510_24,m6510_25,m6510_26,m6510_27,
333
m6510_28,m6510_29,m6510_2a,m6510_2b,m6510_2c,m6510_2d,m6510_2e,m6510_2f,
334
m6510_30,m6510_31,m6510_32,m6510_33,m6510_34,m6510_35,m6510_36,m6510_37,
335
m6510_38,m6510_39,m6510_3a,m6510_3b,m6510_3c,m6510_3d,m6510_3e,m6510_3f,
336
m6510_40,m6510_41,m6510_42,m6510_43,m6510_44,m6510_45,m6510_46,m6510_47,
337
m6510_48,m6510_49,m6510_4a,m6510_4b,m6510_4c,m6510_4d,m6510_4e,m6510_4f,
338
m6510_50,m6510_51,m6510_52,m6510_53,m6510_54,m6510_55,m6510_56,m6510_57,
339
m6510_58,m6510_59,m6510_5a,m6510_5b,m6510_5c,m6510_5d,m6510_5e,m6510_5f,
340
m6510_60,m6510_61,m6510_62,m6510_63,m6510_64,m6510_65,m6510_66,m6510_67,
341
m6510_68,m6510_69,m6510_6a,m6510_6b,m6510_6c,m6510_6d,m6510_6e,m6510_6f,
342
m6510_70,m6510_71,m6510_72,m6510_73,m6510_74,m6510_75,m6510_76,m6510_77,
343
m6510_78,m6510_79,m6510_7a,m6510_7b,m6510_7c,m6510_7d,m6510_7e,m6510_7f,
344
m6510_80,m6510_81,m6510_82,m6510_83,m6510_84,m6510_85,m6510_86,m6510_87,
345
m6510_88,m6510_89,m6510_8a,m6510_8b,m6510_8c,m6510_8d,m6510_8e,m6510_8f,
346
m6510_90,m6510_91,m6510_92,m6510_93,m6510_94,m6510_95,m6510_96,m6510_97,
347
m6510_98,m6510_99,m6510_9a,m6510_9b,m6510_9c,m6510_9d,m6510_9e,m6510_9f,
348
m6510_a0,m6510_a1,m6510_a2,m6510_a3,m6510_a4,m6510_a5,m6510_a6,m6510_a7,
349
m6510_a8,m6510_a9,m6510_aa,m6510_ab,m6510_ac,m6510_ad,m6510_ae,m6510_af,
350
m6510_b0,m6510_b1,m6510_b2,m6510_b3,m6510_b4,m6510_b5,m6510_b6,m6510_b7,
351
m6510_b8,m6510_b9,m6510_ba,m6510_bb,m6510_bc,m6510_bd,m6510_be,m6510_bf,
352
m6510_c0,m6510_c1,m6510_c2,m6510_c3,m6510_c4,m6510_c5,m6510_c6,m6510_c7,
353
m6510_c8,m6510_c9,m6510_ca,m6510_cb,m6510_cc,m6510_cd,m6510_ce,m6510_cf,
354
m6510_d0,m6510_d1,m6510_d2,m6510_d3,m6510_d4,m6510_d5,m6510_d6,m6510_d7,
355
m6510_d8,m6510_d9,m6510_da,m6510_db,m6510_dc,m6510_dd,m6510_de,m6510_df,
356
m6510_e0,m6510_e1,m6510_e2,m6510_e3,m6510_e4,m6510_e5,m6510_e6,m6510_e7,
357
m6510_e8,m6510_e9,m6510_ea,m6510_eb,m6510_ec,m6510_ed,m6510_ee,m6510_ef,
358
m6510_f0,m6510_f1,m6510_f2,m6510_f3,m6510_f4,m6510_f5,m6510_f6,m6510_f7,
359
m6510_f8,m6510_f9,m6510_fa,m6510_fb,m6510_fc,m6510_fd,m6510_fe,m6510_ff
added
removed
src/emu/cpu/m6502/t6510.c
