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Viewing changes to src/mame/drivers/pcxt.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/pcxt.c
57
57
#include "emu.h"
58
58
#include "cpu/i86/i86.h"
59
59
#include "machine/pit8253.h"
60
 
#include "machine/8255ppi.h"
 
60
#include "machine/i8255.h"
61
61
#include "machine/8237dma.h"
62
62
#include "machine/pic8259.h"
63
63
#include "machine/mc146818.h"
70
70
{
71
71
public:
72
72
        pcxt_state(const machine_config &mconfig, device_type type, const char *tag)
73
 
                : driver_device(mconfig, type, tag) { }
 
73
                : driver_device(mconfig, type, tag),
 
74
                  m_pit8253(*this,"pit8253"),
 
75
                  m_pic8259_1(*this,"pic8259_1"),
 
76
                  m_pic8259_2(*this,"pic8259_2"),
 
77
                  m_dma8237_1(*this,"dma8237_1") { }
74
78
 
75
79
        UINT8 m_bg_bank;
76
80
        int m_bank;
86
90
        UINT8 m_at_pages[0x10];
87
91
        UINT8 m_pc_spkrdata, m_pc_input;
88
92
 
89
 
        device_t        *m_pit8253;
90
 
        device_t        *m_pic8259_1;
91
 
        device_t        *m_pic8259_2;
92
 
        device_t        *m_dma8237_1;
93
 
        device_t        *m_dma8237_2;
 
93
        required_device<device_t> m_pit8253;
 
94
        required_device<device_t> m_pic8259_1;
 
95
        required_device<device_t> m_pic8259_2;
 
96
        required_device<device_t> m_dma8237_1;
 
97
 
 
98
        DECLARE_READ8_MEMBER(disk_iobank_r);
 
99
        DECLARE_WRITE8_MEMBER(disk_iobank_w);
 
100
        DECLARE_READ8_MEMBER(fdc765_status_r);
 
101
        DECLARE_READ8_MEMBER(fdc765_data_r);
 
102
        DECLARE_WRITE8_MEMBER(fdc765_data_w);
 
103
        DECLARE_WRITE8_MEMBER(drive_selection_w);
 
104
        DECLARE_READ8_MEMBER(pc_dma_read_byte);
 
105
        DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
 
106
        DECLARE_READ8_MEMBER(dma_page_select_r);
 
107
        DECLARE_WRITE8_MEMBER(dma_page_select_w);
 
108
        DECLARE_WRITE8_MEMBER(tetriskr_bg_bank_w);
94
109
};
95
110
 
96
111
static SCREEN_UPDATE_RGB32( tetriskr )
98
113
        pcxt_state *state = screen.machine().driver_data<pcxt_state>();
99
114
        int x,y;
100
115
        int yi;
101
 
        const UINT8 *bg_rom = screen.machine().region("gfx2")->base();
 
116
        const UINT8 *bg_rom = state->memregion("gfx2")->base();
102
117
 
103
118
        //popmessage("%04x",m_start_offs);
104
119
 
132
147
}
133
148
 
134
149
 
135
 
static READ8_HANDLER( disk_iobank_r )
 
150
READ8_MEMBER(pcxt_state::disk_iobank_r)
136
151
{
137
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
138
 
        //printf("Read Prototyping card [%02x] @ PC=%05x\n",offset,cpu_get_pc(&space->device()));
139
 
        //if(offset == 0) return input_port_read(space->machine(), "DSW");
140
 
        if(offset == 1) return input_port_read(space->machine(), "IN1");
 
152
        //printf("Read Prototyping card [%02x] @ PC=%05x\n",offset,cpu_get_pc(&space.device()));
 
153
        //if(offset == 0) return ioport("DSW")->read();
 
154
        if(offset == 1) return ioport("IN1")->read();
141
155
 
142
 
        return state->m_disk_data[offset];
 
156
        return m_disk_data[offset];
143
157
}
144
158
 
145
 
static WRITE8_HANDLER( disk_iobank_w )
 
159
WRITE8_MEMBER(pcxt_state::disk_iobank_w)
146
160
{
147
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
148
161
/*
149
162
    BIOS does a single out $0310,$F0 on reset
150
163
 
175
188
        }
176
189
        else
177
190
        {
178
 
                if((state->m_lastvalue == 0xF0) && (data == 0xF2))
 
191
                if((m_lastvalue == 0xF0) && (data == 0xF2))
179
192
                        newbank = 0;
180
 
                else if ((state->m_lastvalue == 0xF1) && (data == 0xF2))
 
193
                else if ((m_lastvalue == 0xF1) && (data == 0xF2))
181
194
                        newbank = 1;
182
 
                else if ((state->m_lastvalue == 0xF0) && (data == 0xF3))
 
195
                else if ((m_lastvalue == 0xF0) && (data == 0xF3))
183
196
                        newbank = 2;
184
 
                else if ((state->m_lastvalue == 0xF1) && (data == 0xF3))
 
197
                else if ((m_lastvalue == 0xF1) && (data == 0xF3))
185
198
                        newbank = 3;
186
199
        }
187
200
 
188
201
//  printf("newbank = %d\n", newbank);
189
202
 
190
 
        if (newbank != state->m_bank)
 
203
        if (newbank != m_bank)
191
204
        {
192
 
                state->m_bank = newbank;
193
 
                memory_set_bankptr(space->machine(),  "bank1",space->machine().region("game_prg")->base() + 0x10000 * state->m_bank );
 
205
                m_bank = newbank;
 
206
                membank("bank1")->set_base(machine().root_device().memregion("game_prg")->base() + 0x10000 * m_bank );
194
207
        }
195
208
 
196
 
        state->m_lastvalue = data;
 
209
        m_lastvalue = data;
197
210
 
198
 
        state->m_disk_data[offset] = data;
 
211
        m_disk_data[offset] = data;
199
212
}
200
213
 
201
214
/*********************************
331
344
        cputag_set_input_line(device->machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
332
345
}
333
346
 
334
 
 
335
 
static const ppi8255_interface filetto_ppi8255_intf[2] =
336
 
{
337
 
        {
338
 
                DEVCB_HANDLER(port_a_r),                /* Port A read */
339
 
                DEVCB_HANDLER(port_b_r),                /* Port B read */
340
 
                DEVCB_HANDLER(port_c_r),                /* Port C read */
341
 
                DEVCB_NULL,                                     /* Port A write */
342
 
                DEVCB_HANDLER(port_b_w),                /* Port B write */
343
 
                DEVCB_NULL                                              /* Port C write */
344
 
        },
345
 
        {
346
 
                DEVCB_NULL,                                             /* Port A read */
347
 
                DEVCB_NULL,                                             /* Port B read */
348
 
                DEVCB_NULL,                                             /* Port C read */
349
 
                DEVCB_HANDLER(wss_1_w),                 /* Port A write */
350
 
                DEVCB_HANDLER(wss_2_w),                 /* Port B write */
351
 
                DEVCB_HANDLER(sys_reset_w)              /* Port C write */
352
 
        }
353
 
};
 
347
static I8255A_INTERFACE( ppi8255_0_intf )
 
348
{
 
349
        DEVCB_HANDLER(port_a_r),                        /* Port A read */
 
350
        DEVCB_NULL,                                                     /* Port A write */
 
351
        DEVCB_HANDLER(port_b_r),                        /* Port B read */
 
352
        DEVCB_HANDLER(port_b_w),                        /* Port B write */
 
353
        DEVCB_HANDLER(port_c_r),                        /* Port C read */
 
354
        DEVCB_NULL                                                      /* Port C write */
 
355
};
 
356
 
 
357
static I8255A_INTERFACE( ppi8255_1_intf )
 
358
{
 
359
        DEVCB_NULL,                                                     /* Port A read */
 
360
        DEVCB_HANDLER(wss_1_w),                         /* Port A write */
 
361
        DEVCB_NULL,                                                     /* Port B read */
 
362
        DEVCB_HANDLER(wss_2_w),                         /* Port B write */
 
363
        DEVCB_NULL,                                                     /* Port C read */
 
364
        DEVCB_HANDLER(sys_reset_w)                      /* Port C write */
 
365
};
 
366
 
354
367
 
355
368
/*Floppy Disk Controller 765 device*/
356
369
/*Currently we only emulate it at a point that the BIOS will pass the checks*/
359
372
#define FDC_WRITE 0x40
360
373
#define FDC_READ 0x00 /*~0x40*/
361
374
 
362
 
static READ8_HANDLER( fdc765_status_r )
 
375
READ8_MEMBER(pcxt_state::fdc765_status_r)
363
376
{
364
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
365
377
        UINT8 tmp;
366
 
//  popmessage("Read FDC status @ PC=%05x",cpu_get_pc(&space->device()));
367
 
        tmp = state->m_status | 0x80;
368
 
        state->m_clr_status++;
369
 
        if(state->m_clr_status == 0x10)
 
378
//  popmessage("Read FDC status @ PC=%05x",cpu_get_pc(&space.device()));
 
379
        tmp = m_status | 0x80;
 
380
        m_clr_status++;
 
381
        if(m_clr_status == 0x10)
370
382
        {
371
 
                state->m_status = 0;
372
 
                state->m_clr_status = 0;
 
383
                m_status = 0;
 
384
                m_clr_status = 0;
373
385
        }
374
386
        return tmp;
375
387
}
376
388
 
377
 
static READ8_HANDLER( fdc765_data_r )
 
389
READ8_MEMBER(pcxt_state::fdc765_data_r)
378
390
{
379
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
380
 
        state->m_status = (FDC_READ);
 
391
        m_status = (FDC_READ);
381
392
        return 0xc0;
382
393
}
383
394
 
384
 
static WRITE8_HANDLER( fdc765_data_w )
 
395
WRITE8_MEMBER(pcxt_state::fdc765_data_w)
385
396
{
386
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
387
 
        state->m_status = (FDC_WRITE);
 
397
        m_status = (FDC_WRITE);
388
398
}
389
399
 
390
400
 
391
 
static WRITE8_HANDLER( drive_selection_w )
 
401
WRITE8_MEMBER(pcxt_state::drive_selection_w)
392
402
{
393
 
//  pcxt_state *state = space->machine().driver_data<pcxt_state>();
394
403
 
395
404
        /* TODO: properly hook-up upd765 FDC there */
396
 
        pic8259_ir6_w(space->machine().device("pic8259_1"), 1);
 
405
        pic8259_ir6_w(machine().device("pic8259_1"), 1);
397
406
}
398
407
 
399
408
/******************
410
419
}
411
420
 
412
421
 
413
 
static READ8_HANDLER( pc_dma_read_byte )
414
 
{
415
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
416
 
        offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
417
 
                & 0xFF0000;
418
 
 
419
 
        return space->read_byte(page_offset + offset);
420
 
}
421
 
 
422
 
 
423
 
static WRITE8_HANDLER( pc_dma_write_byte )
424
 
{
425
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
426
 
        offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
427
 
                & 0xFF0000;
428
 
 
429
 
        space->write_byte(page_offset + offset, data);
430
 
}
431
 
 
432
 
static READ8_HANDLER(dma_page_select_r)
433
 
{
434
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
435
 
        UINT8 data = state->m_at_pages[offset % 0x10];
 
422
READ8_MEMBER(pcxt_state::pc_dma_read_byte)
 
423
{
 
424
        offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
 
425
                & 0xFF0000;
 
426
 
 
427
        return space.read_byte(page_offset + offset);
 
428
}
 
429
 
 
430
 
 
431
WRITE8_MEMBER(pcxt_state::pc_dma_write_byte)
 
432
{
 
433
        offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
 
434
                & 0xFF0000;
 
435
 
 
436
        space.write_byte(page_offset + offset, data);
 
437
}
 
438
 
 
439
READ8_MEMBER(pcxt_state::dma_page_select_r)
 
440
{
 
441
        UINT8 data = m_at_pages[offset % 0x10];
436
442
 
437
443
        switch(offset % 8) {
438
444
        case 1:
439
 
                data = state->m_dma_offset[(offset / 8) & 1][2];
 
445
                data = m_dma_offset[(offset / 8) & 1][2];
440
446
                break;
441
447
        case 2:
442
 
                data = state->m_dma_offset[(offset / 8) & 1][3];
 
448
                data = m_dma_offset[(offset / 8) & 1][3];
443
449
                break;
444
450
        case 3:
445
 
                data = state->m_dma_offset[(offset / 8) & 1][1];
 
451
                data = m_dma_offset[(offset / 8) & 1][1];
446
452
                break;
447
453
        case 7:
448
 
                data = state->m_dma_offset[(offset / 8) & 1][0];
 
454
                data = m_dma_offset[(offset / 8) & 1][0];
449
455
                break;
450
456
        }
451
457
        return data;
452
458
}
453
459
 
454
460
 
455
 
static WRITE8_HANDLER(dma_page_select_w)
 
461
WRITE8_MEMBER(pcxt_state::dma_page_select_w)
456
462
{
457
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
458
 
        state->m_at_pages[offset % 0x10] = data;
 
463
        m_at_pages[offset % 0x10] = data;
459
464
 
460
465
        switch(offset % 8) {
461
466
        case 1:
462
 
                state->m_dma_offset[(offset / 8) & 1][2] = data;
 
467
                m_dma_offset[(offset / 8) & 1][2] = data;
463
468
                break;
464
469
        case 2:
465
 
                state->m_dma_offset[(offset / 8) & 1][3] = data;
 
470
                m_dma_offset[(offset / 8) & 1][3] = data;
466
471
                break;
467
472
        case 3:
468
 
                state->m_dma_offset[(offset / 8) & 1][1] = data;
 
473
                m_dma_offset[(offset / 8) & 1][1] = data;
469
474
                break;
470
475
        case 7:
471
 
                state->m_dma_offset[(offset / 8) & 1][0] = data;
 
476
                m_dma_offset[(offset / 8) & 1][0] = data;
472
477
                break;
473
478
        }
474
479
}
488
493
{
489
494
        DEVCB_LINE(pc_dma_hrq_changed),
490
495
        DEVCB_NULL,
491
 
        DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
492
 
        DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
 
496
        DEVCB_DRIVER_MEMBER(pcxt_state, pc_dma_read_byte),
 
497
        DEVCB_DRIVER_MEMBER(pcxt_state, pc_dma_write_byte),
493
498
        { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
494
499
        { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
495
500
        { DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
533
538
        return pic8259_acknowledge(state->m_pic8259_1);
534
539
}
535
540
 
536
 
static ADDRESS_MAP_START( filetto_map, AS_PROGRAM, 8 )
 
541
static ADDRESS_MAP_START( filetto_map, AS_PROGRAM, 8, pcxt_state )
537
542
        AM_RANGE(0x00000, 0x9ffff) AM_RAM //work RAM 640KB
538
543
        AM_RANGE(0xa0000, 0xbffff) AM_RAM //CGA VRAM
539
544
        AM_RANGE(0xc0000, 0xcffff) AM_ROMBANK("bank1")
541
546
        AM_RANGE(0xf0000, 0xfffff) AM_ROM
542
547
ADDRESS_MAP_END
543
548
 
544
 
static ADDRESS_MAP_START( pcxt_io_common, AS_IO, 8 )
 
549
static ADDRESS_MAP_START( pcxt_io_common, AS_IO, 8, pcxt_state )
545
550
        ADDRESS_MAP_GLOBAL_MASK(0x3ff)
546
 
        AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE("dma8237_1", i8237_r, i8237_w ) //8237 DMA Controller
547
 
        AM_RANGE(0x0020, 0x002f) AM_DEVREADWRITE("pic8259_1", pic8259_r, pic8259_w ) //8259 Interrupt control
548
 
        AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_r, pit8253_w)    //8253 PIT
549
 
        AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255_0", ppi8255_r, ppi8255_w)  //PPI 8255
550
 
        AM_RANGE(0x0064, 0x0066) AM_DEVREADWRITE("ppi8255_1", ppi8255_r, ppi8255_w)  //PPI 8255
551
 
        AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE_MODERN("rtc", mc146818_device, read, write)
 
551
        AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE_LEGACY("dma8237_1", i8237_r, i8237_w ) //8237 DMA Controller
 
552
        AM_RANGE(0x0020, 0x002f) AM_DEVREADWRITE_LEGACY("pic8259_1", pic8259_r, pic8259_w ) //8259 Interrupt control
 
553
        AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)    //8253 PIT
 
554
        AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)  //PPI 8255
 
555
        AM_RANGE(0x0064, 0x0066) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)  //PPI 8255
 
556
        AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE("rtc", mc146818_device, read, write)
552
557
        AM_RANGE(0x0080, 0x0087) AM_READWRITE(dma_page_select_r,dma_page_select_w)
553
 
        AM_RANGE(0x00a0, 0x00af) AM_DEVREADWRITE("pic8259_2", pic8259_r, pic8259_w )
 
558
        AM_RANGE(0x00a0, 0x00af) AM_DEVREADWRITE_LEGACY("pic8259_2", pic8259_r, pic8259_w )
554
559
        AM_RANGE(0x0278, 0x027f) AM_RAM //printer (parallel) port latch
555
560
        AM_RANGE(0x02f8, 0x02ff) AM_RAM //Modem port
556
561
        AM_RANGE(0x0378, 0x037f) AM_RAM //printer (parallel) port
561
566
        AM_RANGE(0x03f8, 0x03ff) AM_RAM //rs232c (serial) port
562
567
ADDRESS_MAP_END
563
568
 
564
 
static ADDRESS_MAP_START( filetto_io, AS_IO, 8 )
 
569
static ADDRESS_MAP_START( filetto_io, AS_IO, 8, pcxt_state )
565
570
        ADDRESS_MAP_GLOBAL_MASK(0x3ff)
566
571
        AM_IMPORT_FROM( pcxt_io_common )
567
572
//  AM_RANGE(0x0200, 0x020f) AM_RAM //game port
570
575
        AM_RANGE(0x0312, 0x0312) AM_READ_PORT("IN0") //Prototyping card,read only
571
576
ADDRESS_MAP_END
572
577
 
573
 
static WRITE8_HANDLER( tetriskr_bg_bank_w )
 
578
WRITE8_MEMBER(pcxt_state::tetriskr_bg_bank_w)
574
579
{
575
 
        pcxt_state *state = space->machine().driver_data<pcxt_state>();
576
580
 
577
 
        state->m_bg_bank = (data & 0x0f) ^ 8;
 
581
        m_bg_bank = (data & 0x0f) ^ 8;
578
582
}
579
583
 
580
 
static ADDRESS_MAP_START( tetriskr_io, AS_IO, 8 )
 
584
static ADDRESS_MAP_START( tetriskr_io, AS_IO, 8, pcxt_state )
581
585
        ADDRESS_MAP_GLOBAL_MASK(0x3ff)
582
586
        AM_IMPORT_FROM( pcxt_io_common )
583
587
        AM_RANGE(0x0200, 0x020f) AM_RAM //game port
706
710
        state->m_bank = -1;
707
711
        state->m_lastvalue = -1;
708
712
        device_set_irq_callback(machine.device("maincpu"), irq_callback);
709
 
        state->m_pit8253 = machine.device( "pit8253" );
710
 
        state->m_pic8259_1 = machine.device( "pic8259_1" );
711
 
        state->m_pic8259_2 = machine.device( "pic8259_2" );
712
 
        state->m_dma8237_1 = machine.device( "dma8237_1" );
713
 
        state->m_dma8237_2 = machine.device( "dma8237_2" );
714
713
 
715
714
        state->m_pc_spkrdata = 0;
716
715
        state->m_pc_input = 0;
727
726
 
728
727
        MCFG_PIT8253_ADD( "pit8253", pc_pit8253_config )
729
728
 
730
 
        MCFG_PPI8255_ADD( "ppi8255_0", filetto_ppi8255_intf[0] )
731
 
        MCFG_PPI8255_ADD( "ppi8255_1", filetto_ppi8255_intf[1] )
 
729
        MCFG_I8255A_ADD( "ppi8255_0", ppi8255_0_intf )
 
730
        MCFG_I8255A_ADD( "ppi8255_1", ppi8255_1_intf )
732
731
 
733
732
        MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
734
733