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Viewing changes to src/mame/drivers/cybertnk.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/cybertnk.c
170
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{
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public:
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        cybertnk_state(const machine_config &mconfig, device_type type, const char *tag)
173
 
                : driver_device(mconfig, type, tag) { }
 
173
                : driver_device(mconfig, type, tag) ,
 
174
                m_spr_ram(*this, "spr_ram"),
 
175
                m_tx_vram(*this, "tx_vram"),
 
176
                m_bg_vram(*this, "bg_vram"),
 
177
                m_fg_vram(*this, "fg_vram"),
 
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                m_io_ram(*this, "io_ram"),
 
179
                m_roadram(*this, "roadram"){ }
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175
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        tilemap_t *m_tx_tilemap;
176
 
        UINT16 *m_tx_vram;
177
 
        UINT16 *m_bg_vram;
178
 
        UINT16 *m_fg_vram;
179
 
        UINT16 *m_spr_ram;
180
 
        UINT16 *m_io_ram;
181
 
        UINT16 *m_roadram;
 
182
        required_shared_ptr<UINT16> m_spr_ram;
 
183
        required_shared_ptr<UINT16> m_tx_vram;
 
184
        required_shared_ptr<UINT16> m_bg_vram;
 
185
        required_shared_ptr<UINT16> m_fg_vram;
 
186
        required_shared_ptr<UINT16> m_io_ram;
 
187
        required_shared_ptr<UINT16> m_roadram;
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        int m_test_x;
183
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        int m_test_y;
184
190
        int m_start_offs;
185
191
        int m_color_pen;
 
192
        DECLARE_WRITE16_MEMBER(tx_vram_w);
 
193
        DECLARE_READ16_MEMBER(io_r);
 
194
        DECLARE_WRITE16_MEMBER(io_w);
 
195
        DECLARE_READ8_MEMBER(soundport_r);
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};
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189
 
#define LOG_UNKNOWN_WRITE logerror("unknown io write CPU '%s':%08x  0x%08x 0x%04x & 0x%04x\n", space->device().tag(), cpu_get_pc(&space->device()), offset*2, data, mem_mask);
 
199
#define LOG_UNKNOWN_WRITE logerror("unknown io write CPU '%s':%08x  0x%08x 0x%04x & 0x%04x\n", space.device().tag(), cpu_get_pc(&space.device()), offset*2, data, mem_mask);
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static TILE_GET_INFO( get_tx_tile_info )
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{
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        /* non-tile based spriteram (BARE-BONES, looks pretty complex) */
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        if(1)
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        {
287
 
                const UINT8 *blit_ram = screen.machine().region("spr_gfx")->base();
 
297
                const UINT8 *blit_ram = screen.machine().root_device().memregion("spr_gfx")->base();
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                int offs,x,y,z,xsize,ysize,yi,xi,col_bank,fx,zoom;
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                UINT32 spr_offs,spr_offs_helper;
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                int xf,yf,xz,yz;
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                if(0) //sprite gfx debug viewer
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                {
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                        int x,y,count;
419
 
                        const UINT8 *blit_ram = screen.machine().region("spr_gfx")->base();
 
429
                        const UINT8 *blit_ram = screen.machine().root_device().memregion("spr_gfx")->base();
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                        if(screen.machine().input().code_pressed(KEYCODE_Z))
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                        state->m_test_x++;
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static SCREEN_UPDATE_IND16( cybertnk_right ) { return update_screen(screen, bitmap, cliprect, -256); }
511
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512
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513
 
static WRITE16_HANDLER( tx_vram_w )
 
523
WRITE16_MEMBER(cybertnk_state::tx_vram_w)
514
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{
515
 
        cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
516
 
        COMBINE_DATA(&state->m_tx_vram[offset]);
517
 
        state->m_tx_tilemap->mark_tile_dirty(offset);
 
525
        COMBINE_DATA(&m_tx_vram[offset]);
 
526
        m_tx_tilemap->mark_tile_dirty(offset);
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}
519
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520
 
static READ16_HANDLER( io_r )
 
529
READ16_MEMBER(cybertnk_state::io_r)
521
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{
522
 
        cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
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        switch( offset )
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        {
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                case 2/2:
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                        return input_port_read(space->machine(), "DSW1");
 
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                        return ioport("DSW1")->read();
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                // 0x00110007 is controller device select
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                // 0x001100D5 is controller data
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                // 0x00110004 low is controller data ready
531
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                case 4/2:
532
 
                        switch( (state->m_io_ram[6/2]) & 0xff )
 
540
                        switch( (m_io_ram[6/2]) & 0xff )
533
541
                        {
534
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                                case 0:
535
 
                                        state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "TRAVERSE");
 
543
                                        m_io_ram[0xd4/2] = ioport("TRAVERSE")->read();
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                                        break;
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                                case 0x20:
539
 
                                        state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "ELEVATE");
 
547
                                        m_io_ram[0xd4/2] = ioport("ELEVATE")->read();
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                                        break;
541
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                                case 0x40:
543
 
                                        state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "ACCEL");
 
551
                                        m_io_ram[0xd4/2] = ioport("ACCEL")->read();
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                                        break;
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                                case 0x42:
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                                        // controller return value is stored in $42(a6)
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                                        // but I don't see it referenced again.
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                                        //popmessage("unknown controller device 0x42");
551
 
                                        state->m_io_ram[0xd4/2] = 0;
 
559
                                        m_io_ram[0xd4/2] = 0;
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                                        break;
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                                case 0x60:
555
 
                                        state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "HANDLE");
 
563
                                        m_io_ram[0xd4/2] = ioport("HANDLE")->read();
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                                        break;
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                                //default:
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                        return 0;
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                case 6/2:
564
 
                        return input_port_read(space->machine(), "IN0"); // high half
 
572
                        return ioport("IN0")->read(); // high half
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                case 8/2:
567
 
                        return input_port_read(space->machine(), "IN0"); // low half
 
575
                        return ioport("IN0")->read(); // low half
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                case 0xa/2:
570
 
                        return input_port_read(space->machine(), "DSW2");
 
578
                        return ioport("DSW2")->read();
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                case 0xd4/2:
573
 
                        return state->m_io_ram[offset]; // controller data
 
581
                        return m_io_ram[offset]; // controller data
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575
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                default:
576
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                {
577
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                        //popmessage("unknown io read 0x%08x", offset);
578
 
                        return state->m_io_ram[offset];
 
586
                        return m_io_ram[offset];
579
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                }
580
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        }
581
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}
582
590
 
583
 
static WRITE16_HANDLER( io_w )
 
591
WRITE16_MEMBER(cybertnk_state::io_w)
584
592
{
585
 
        cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
586
 
        COMBINE_DATA(&state->m_io_ram[offset]);
 
593
        COMBINE_DATA(&m_io_ram[offset]);
587
594
 
588
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        switch( offset )
589
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        {
590
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                case 0/2:
591
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                        // sound data
592
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                        if (ACCESSING_BITS_0_7)
593
 
                                cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
 
600
                                cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
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                        else
595
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                                LOG_UNKNOWN_WRITE
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                        break;
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                case 0x80/2:
645
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                case 0x82/2:
646
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                case 0x84/2:
647
 
                        popmessage("%02x %02x %02x %02x %02x %02x %02x",state->m_io_ram[0x40/2],state->m_io_ram[0x42/2],state->m_io_ram[0x44/2],state->m_io_ram[0x46/2],state->m_io_ram[0x48/2],state->m_io_ram[0x4a/2],state->m_io_ram[0x4c/2]);
 
654
                        popmessage("%02x %02x %02x %02x %02x %02x %02x",m_io_ram[0x40/2],m_io_ram[0x42/2],m_io_ram[0x44/2],m_io_ram[0x46/2],m_io_ram[0x48/2],m_io_ram[0x4a/2],m_io_ram[0x4c/2]);
648
655
                        break;
649
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650
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                default:
653
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        }
654
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}
655
662
 
656
 
static READ8_HANDLER( soundport_r )
 
663
READ8_MEMBER(cybertnk_state::soundport_r)
657
664
{
658
 
        cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
659
 
        return state->m_io_ram[0] & 0xff;
 
665
        return m_io_ram[0] & 0xff;
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}
661
667
 
662
 
static ADDRESS_MAP_START( master_mem, AS_PROGRAM, 16 )
 
668
static ADDRESS_MAP_START( master_mem, AS_PROGRAM, 16, cybertnk_state )
663
669
        AM_RANGE(0x000000, 0x03ffff) AM_ROM
664
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        AM_RANGE(0x080000, 0x087fff) AM_RAM /*Work RAM*/
665
 
        AM_RANGE(0x0a0000, 0x0a0fff) AM_RAM AM_BASE_MEMBER(cybertnk_state, m_spr_ram) // non-tile based sprite ram
666
 
        AM_RANGE(0x0c0000, 0x0c1fff) AM_RAM_WRITE(tx_vram_w) AM_BASE_MEMBER(cybertnk_state, m_tx_vram)
667
 
        AM_RANGE(0x0c4000, 0x0c5fff) AM_RAM AM_BASE_MEMBER(cybertnk_state, m_bg_vram)
668
 
        AM_RANGE(0x0c8000, 0x0c9fff) AM_RAM AM_BASE_MEMBER(cybertnk_state, m_fg_vram)
 
671
        AM_RANGE(0x0a0000, 0x0a0fff) AM_RAM AM_SHARE("spr_ram") // non-tile based sprite ram
 
672
        AM_RANGE(0x0c0000, 0x0c1fff) AM_RAM_WRITE(tx_vram_w) AM_SHARE("tx_vram")
 
673
        AM_RANGE(0x0c4000, 0x0c5fff) AM_RAM AM_SHARE("bg_vram")
 
674
        AM_RANGE(0x0c8000, 0x0c9fff) AM_RAM AM_SHARE("fg_vram")
669
675
        AM_RANGE(0x0e0000, 0x0e0fff) AM_RAM AM_SHARE("sharedram")
670
 
        AM_RANGE(0x100000, 0x107fff) AM_RAM_WRITE(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
671
 
        AM_RANGE(0x110000, 0x1101ff) AM_READWRITE(io_r,io_w) AM_BASE_MEMBER(cybertnk_state, m_io_ram)
 
676
        AM_RANGE(0x100000, 0x107fff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
 
677
        AM_RANGE(0x110000, 0x1101ff) AM_READWRITE(io_r,io_w) AM_SHARE("io_ram")
672
678
ADDRESS_MAP_END
673
679
 
674
 
static ADDRESS_MAP_START( slave_mem, AS_PROGRAM, 16 )
 
680
static ADDRESS_MAP_START( slave_mem, AS_PROGRAM, 16, cybertnk_state )
675
681
        AM_RANGE(0x000000, 0x01ffff) AM_ROM
676
682
        AM_RANGE(0x080000, 0x083fff) AM_RAM /*Work RAM*/
677
 
        AM_RANGE(0x0c0000, 0x0c0fff) AM_RAM AM_BASE_MEMBER(cybertnk_state, m_roadram)
 
683
        AM_RANGE(0x0c0000, 0x0c0fff) AM_RAM AM_SHARE("roadram")
678
684
        AM_RANGE(0x100000, 0x100fff) AM_RAM AM_SHARE("sharedram")
679
685
        AM_RANGE(0x140000, 0x140003) AM_NOP /*Watchdog? Written during loops and interrupts*/
680
686
ADDRESS_MAP_END
681
687
 
682
 
static ADDRESS_MAP_START( sound_mem, AS_PROGRAM, 8 )
 
688
static ADDRESS_MAP_START( sound_mem, AS_PROGRAM, 8, cybertnk_state )
683
689
        AM_RANGE(0x0000, 0x7fff ) AM_ROM
684
690
        AM_RANGE(0x8000, 0x9fff ) AM_RAM
685
691
        AM_RANGE(0xa001, 0xa001 ) AM_READ(soundport_r)
686
692
        AM_RANGE(0xa005, 0xa006 ) AM_NOP
687
 
        AM_RANGE(0xa000, 0xa001 ) AM_DEVREADWRITE("ym1", y8950_r, y8950_w)
688
 
        AM_RANGE(0xc000, 0xc001 ) AM_DEVREADWRITE("ym2", y8950_r, y8950_w)
 
693
        AM_RANGE(0xa000, 0xa001 ) AM_DEVREADWRITE_LEGACY("ym1", y8950_r, y8950_w)
 
694
        AM_RANGE(0xc000, 0xc001 ) AM_DEVREADWRITE_LEGACY("ym2", y8950_r, y8950_w)
689
695
ADDRESS_MAP_END
690
696
 
691
697
static INPUT_PORTS_START( cybertnk )
1008
1014
    UINT8* road_data;
1009
1015
    int i;
1010
1016
 
1011
 
    road_data = machine.region("road_data")->base();
 
1017
    road_data = machine.root_device().memregion("road_data")->base();
1012
1018
    for (i=0;i < 0x40000;i++)
1013
1019
    {
1014
1020
        road_data[i] = BITSWAP8(road_data[i],3,2,1,0,7,6,5,4);