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Viewing changes to src/mame/drivers/crystal.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/crystal.c
129
129
{
130
130
public:
131
131
        crystal_state(const machine_config &mconfig, device_type type, const char *tag)
132
 
                : driver_device(mconfig, type, tag) { }
 
132
                : driver_device(mconfig, type, tag) ,
 
133
                m_sysregs(*this, "sysregs"),
 
134
                m_workram(*this, "workram"),
 
135
                m_vidregs(*this, "vidregs"),
 
136
                m_textureram(*this, "textureram"),
 
137
                m_frameram(*this, "frameram"),
 
138
                m_reset_patch(*this, "reset_patch"){ }
133
139
 
134
140
        /* memory pointers */
135
 
        UINT32 *  m_workram;
136
 
        UINT32 *  m_textureram;
137
 
        UINT32 *  m_frameram;
138
 
        UINT32 *  m_sysregs;
139
 
        UINT32 *  m_vidregs;
 
141
        required_shared_ptr<UINT32> m_sysregs;
 
142
        required_shared_ptr<UINT32> m_workram;
 
143
        required_shared_ptr<UINT32> m_vidregs;
 
144
        required_shared_ptr<UINT32> m_textureram;
 
145
        required_shared_ptr<UINT32> m_frameram;
 
146
        required_shared_ptr<UINT32> m_reset_patch;
140
147
//  UINT32 *  m_nvram;    // currently this uses generic nvram handling
141
148
 
142
149
#ifdef IDLE_LOOP_SPEEDUP
152
159
        UINT32    m_PIO;
153
160
        UINT32    m_DMActrl[2];
154
161
        UINT8     m_OldPort4;
155
 
        UINT32    *m_ResetPatch;
156
162
 
157
163
        device_t *m_maincpu;
158
 
        device_t *m_ds1302;
 
164
        ds1302_device *m_ds1302;
159
165
        device_t *m_vr0video;
 
166
        DECLARE_READ32_MEMBER(FlipCount_r);
 
167
        DECLARE_WRITE32_MEMBER(FlipCount_w);
 
168
        DECLARE_READ32_MEMBER(Input_r);
 
169
        DECLARE_WRITE32_MEMBER(IntAck_w);
 
170
        DECLARE_WRITE32_MEMBER(Banksw_w);
 
171
        DECLARE_WRITE32_MEMBER(Timer0_w);
 
172
        DECLARE_READ32_MEMBER(Timer0_r);
 
173
        DECLARE_WRITE32_MEMBER(Timer1_w);
 
174
        DECLARE_READ32_MEMBER(Timer1_r);
 
175
        DECLARE_WRITE32_MEMBER(Timer2_w);
 
176
        DECLARE_READ32_MEMBER(Timer2_r);
 
177
        DECLARE_WRITE32_MEMBER(Timer3_w);
 
178
        DECLARE_READ32_MEMBER(Timer3_r);
 
179
        DECLARE_READ32_MEMBER(FlashCmd_r);
 
180
        DECLARE_WRITE32_MEMBER(FlashCmd_w);
 
181
        DECLARE_READ32_MEMBER(PIO_r);
 
182
        DECLARE_WRITE32_MEMBER(PIO_w);
 
183
        DECLARE_READ32_MEMBER(DMA0_r);
 
184
        DECLARE_WRITE32_MEMBER(DMA0_w);
 
185
        DECLARE_READ32_MEMBER(DMA1_r);
 
186
        DECLARE_WRITE32_MEMBER(DMA1_w);
160
187
};
161
188
 
162
189
static void IntReq( running_machine &machine, int num )
177
204
#endif
178
205
}
179
206
 
180
 
static READ32_HANDLER( FlipCount_r )
 
207
READ32_MEMBER(crystal_state::FlipCount_r)
181
208
{
182
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
183
209
 
184
210
#ifdef IDLE_LOOP_SPEEDUP
185
 
        UINT32 IntPend = space->read_dword(0x01800c0c);
186
 
        state->m_FlipCntRead++;
187
 
        if (state->m_FlipCntRead >= 16 && !IntPend && state->m_FlipCount != 0)
188
 
                device_suspend(state->m_maincpu, SUSPEND_REASON_SPIN, 1);
 
211
        UINT32 IntPend = space.read_dword(0x01800c0c);
 
212
        m_FlipCntRead++;
 
213
        if (m_FlipCntRead >= 16 && !IntPend && m_FlipCount != 0)
 
214
                device_suspend(m_maincpu, SUSPEND_REASON_SPIN, 1);
189
215
#endif
190
 
        return ((UINT32) state->m_FlipCount) << 16;
 
216
        return ((UINT32) m_FlipCount) << 16;
191
217
}
192
218
 
193
 
static WRITE32_HANDLER( FlipCount_w )
 
219
WRITE32_MEMBER(crystal_state::FlipCount_w)
194
220
{
195
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
196
221
 
197
222
        if (mem_mask & 0x00ff0000)
198
223
        {
199
224
                int fc = (data >> 16) & 0xff;
200
225
                if (fc == 1)
201
 
                        state->m_FlipCount++;
 
226
                        m_FlipCount++;
202
227
                else if (fc == 0)
203
 
                        state->m_FlipCount = 0;
 
228
                        m_FlipCount = 0;
204
229
        }
205
230
}
206
231
 
207
 
static READ32_HANDLER( Input_r )
 
232
READ32_MEMBER(crystal_state::Input_r)
208
233
{
209
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
210
234
 
211
235
        if (offset == 0)
212
 
                return input_port_read(space->machine(), "P1_P2");
 
236
                return ioport("P1_P2")->read();
213
237
        else if (offset == 1)
214
 
                return input_port_read(space->machine(), "P3_P4");
 
238
                return ioport("P3_P4")->read();
215
239
        else if( offset == 2)
216
240
        {
217
 
                UINT8 Port4 = input_port_read(space->machine(), "SYSTEM");
218
 
                if (!(Port4 & 0x10) && ((state->m_OldPort4 ^ Port4) & 0x10))    //coin buttons trigger IRQs
219
 
                        IntReq(space->machine(), 12);
220
 
                if (!(Port4 & 0x20) && ((state->m_OldPort4 ^ Port4) & 0x20))
221
 
                        IntReq(space->machine(), 19);
222
 
                state->m_OldPort4 = Port4;
223
 
                return /*dips*/input_port_read(space->machine(), "DSW") | (Port4 << 16);
 
241
                UINT8 Port4 = ioport("SYSTEM")->read();
 
242
                if (!(Port4 & 0x10) && ((m_OldPort4 ^ Port4) & 0x10))   //coin buttons trigger IRQs
 
243
                        IntReq(machine(), 12);
 
244
                if (!(Port4 & 0x20) && ((m_OldPort4 ^ Port4) & 0x20))
 
245
                        IntReq(machine(), 19);
 
246
                m_OldPort4 = Port4;
 
247
                return /*dips*/ioport("DSW")->read() | (Port4 << 16);
224
248
        }
225
249
        return 0;
226
250
}
227
251
 
228
 
static WRITE32_HANDLER( IntAck_w )
 
252
WRITE32_MEMBER(crystal_state::IntAck_w)
229
253
{
230
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
231
 
        UINT32 IntPend = space->read_dword(0x01800c0c);
 
254
        UINT32 IntPend = space.read_dword(0x01800c0c);
232
255
 
233
256
        if (mem_mask & 0xff)
234
257
        {
235
258
                IntPend &= ~(1 << (data & 0x1f));
236
 
                space->write_dword(0x01800c0c, IntPend);
 
259
                space.write_dword(0x01800c0c, IntPend);
237
260
                if (!IntPend)
238
 
                        device_set_input_line(state->m_maincpu, SE3208_INT, CLEAR_LINE);
 
261
                        device_set_input_line(m_maincpu, SE3208_INT, CLEAR_LINE);
239
262
        }
240
263
        if (mem_mask & 0xff00)
241
 
                state->m_IntHigh = (data >> 8) & 7;
 
264
                m_IntHigh = (data >> 8) & 7;
242
265
}
243
266
 
244
267
static IRQ_CALLBACK( icallback )
258
281
        return 0;               //This should never happen
259
282
}
260
283
 
261
 
static WRITE32_HANDLER( Banksw_w )
 
284
WRITE32_MEMBER(crystal_state::Banksw_w)
262
285
{
263
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
264
286
 
265
 
        state->m_Bank = (data >> 1) & 7;
266
 
        if (state->m_Bank <= 2)
267
 
                memory_set_bankptr(space->machine(), "bank1", space->machine().region("user1")->base() + state->m_Bank * 0x1000000);
 
287
        m_Bank = (data >> 1) & 7;
 
288
        if (m_Bank <= 2)
 
289
                membank("bank1")->set_base(machine().root_device().memregion("user1")->base() + m_Bank * 0x1000000);
268
290
        else
269
 
                memory_set_bankptr(space->machine(), "bank1", space->machine().region("user2")->base());
 
291
                membank("bank1")->set_base(machine().root_device().memregion("user2")->base());
270
292
}
271
293
 
272
294
static TIMER_CALLBACK( Timercb )
299
321
        COMBINE_DATA(&state->m_Timerctrl[which]);
300
322
}
301
323
 
302
 
static WRITE32_HANDLER( Timer0_w )
303
 
{
304
 
        Timer_w(space, 0, data, mem_mask);
305
 
}
306
 
 
307
 
static READ32_HANDLER( Timer0_r )
308
 
{
309
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
310
 
        return state->m_Timerctrl[0];
311
 
}
312
 
 
313
 
static WRITE32_HANDLER( Timer1_w )
314
 
{
315
 
        Timer_w(space, 1, data, mem_mask);
316
 
}
317
 
 
318
 
static READ32_HANDLER( Timer1_r )
319
 
{
320
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
321
 
        return state->m_Timerctrl[1];
322
 
}
323
 
 
324
 
static WRITE32_HANDLER( Timer2_w )
325
 
{
326
 
        Timer_w(space, 2, data, mem_mask);
327
 
}
328
 
 
329
 
static READ32_HANDLER( Timer2_r )
330
 
{
331
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
332
 
        return state->m_Timerctrl[2];
333
 
}
334
 
 
335
 
static WRITE32_HANDLER( Timer3_w )
336
 
{
337
 
        Timer_w(space, 3, data, mem_mask);
338
 
}
339
 
 
340
 
static READ32_HANDLER( Timer3_r )
341
 
{
342
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
343
 
        return state->m_Timerctrl[3];
344
 
}
345
 
 
346
 
static READ32_HANDLER( FlashCmd_r )
347
 
{
348
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
349
 
 
350
 
        if ((state->m_FlashCmd & 0xff) == 0xff)
 
324
WRITE32_MEMBER(crystal_state::Timer0_w)
 
325
{
 
326
        Timer_w(&space, 0, data, mem_mask);
 
327
}
 
328
 
 
329
READ32_MEMBER(crystal_state::Timer0_r)
 
330
{
 
331
        return m_Timerctrl[0];
 
332
}
 
333
 
 
334
WRITE32_MEMBER(crystal_state::Timer1_w)
 
335
{
 
336
        Timer_w(&space, 1, data, mem_mask);
 
337
}
 
338
 
 
339
READ32_MEMBER(crystal_state::Timer1_r)
 
340
{
 
341
        return m_Timerctrl[1];
 
342
}
 
343
 
 
344
WRITE32_MEMBER(crystal_state::Timer2_w)
 
345
{
 
346
        Timer_w(&space, 2, data, mem_mask);
 
347
}
 
348
 
 
349
READ32_MEMBER(crystal_state::Timer2_r)
 
350
{
 
351
        return m_Timerctrl[2];
 
352
}
 
353
 
 
354
WRITE32_MEMBER(crystal_state::Timer3_w)
 
355
{
 
356
        Timer_w(&space, 3, data, mem_mask);
 
357
}
 
358
 
 
359
READ32_MEMBER(crystal_state::Timer3_r)
 
360
{
 
361
        return m_Timerctrl[3];
 
362
}
 
363
 
 
364
READ32_MEMBER(crystal_state::FlashCmd_r)
 
365
{
 
366
 
 
367
        if ((m_FlashCmd & 0xff) == 0xff)
351
368
        {
352
 
                if (state->m_Bank <= 2)
 
369
                if (m_Bank <= 2)
353
370
                {
354
 
                        UINT32 *ptr = (UINT32*)(space->machine().region("user1")->base() + state->m_Bank * 0x1000000);
 
371
                        UINT32 *ptr = (UINT32*)(machine().root_device().memregion("user1")->base() + m_Bank * 0x1000000);
355
372
                        return ptr[0];
356
373
                }
357
374
                else
358
375
                        return 0xffffffff;
359
376
        }
360
 
        if ((state->m_FlashCmd & 0xff) == 0x90)
 
377
        if ((m_FlashCmd & 0xff) == 0x90)
361
378
        {
362
 
                if (state->m_Bank <= 2)
 
379
                if (m_Bank <= 2)
363
380
            return 0x00180089;  //Intel 128MBit
364
381
                else
365
382
                        return 0xffffffff;
367
384
        return 0;
368
385
}
369
386
 
370
 
static WRITE32_HANDLER( FlashCmd_w )
371
 
{
372
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
373
 
        state->m_FlashCmd = data;
374
 
}
375
 
 
376
 
static READ32_HANDLER( PIO_r )
377
 
{
378
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
379
 
        return state->m_PIO;
380
 
}
381
 
 
382
 
static WRITE32_HANDLER( PIO_w )
383
 
{
384
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
 
387
WRITE32_MEMBER(crystal_state::FlashCmd_w)
 
388
{
 
389
        m_FlashCmd = data;
 
390
}
 
391
 
 
392
READ32_MEMBER(crystal_state::PIO_r)
 
393
{
 
394
        return m_PIO;
 
395
}
 
396
 
 
397
WRITE32_MEMBER(crystal_state::PIO_w)
 
398
{
385
399
        UINT32 RST = data & 0x01000000;
386
400
        UINT32 CLK = data & 0x02000000;
387
401
        UINT32 DAT = data & 0x10000000;
388
402
 
389
 
        if (!RST)
390
 
                state->m_ds1302->reset();
391
 
 
392
 
        ds1302_dat_w(state->m_ds1302, 0, DAT ? 1 : 0);
393
 
        ds1302_clk_w(state->m_ds1302, 0, CLK ? 1 : 0);
394
 
 
395
 
        if (ds1302_read(state->m_ds1302, 0))
396
 
                space->write_dword(0x01802008, space->read_dword(0x01802008) | 0x10000000);
 
403
        m_ds1302->ce_w(RST ? 1 : 0);
 
404
        m_ds1302->io_w(DAT ? 1 : 0);
 
405
        m_ds1302->sclk_w(CLK ? 1 : 0);
 
406
 
 
407
        if (m_ds1302->io_r())
 
408
                space.write_dword(0x01802008, space.read_dword(0x01802008) | 0x10000000);
397
409
        else
398
 
                space->write_dword(0x01802008, space->read_dword(0x01802008) & (~0x10000000));
 
410
                space.write_dword(0x01802008, space.read_dword(0x01802008) & (~0x10000000));
399
411
 
400
 
        COMBINE_DATA(&state->m_PIO);
 
412
        COMBINE_DATA(&m_PIO);
401
413
}
402
414
 
403
415
INLINE void DMA_w( address_space *space, int which, UINT32 data, UINT32 mem_mask )
443
455
        COMBINE_DATA(&state->m_DMActrl[which]);
444
456
}
445
457
 
446
 
static READ32_HANDLER( DMA0_r )
447
 
{
448
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
449
 
        return state->m_DMActrl[0];
450
 
}
451
 
 
452
 
static WRITE32_HANDLER( DMA0_w )
453
 
{
454
 
        DMA_w(space, 0, data, mem_mask);
455
 
}
456
 
 
457
 
static READ32_HANDLER( DMA1_r )
458
 
{
459
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
460
 
        return state->m_DMActrl[1];
461
 
}
462
 
 
463
 
static WRITE32_HANDLER( DMA1_w )
464
 
{
465
 
        DMA_w(space, 1, data, mem_mask);
466
 
}
467
 
 
468
 
 
469
 
static ADDRESS_MAP_START( crystal_mem, AS_PROGRAM, 32 )
 
458
READ32_MEMBER(crystal_state::DMA0_r)
 
459
{
 
460
        return m_DMActrl[0];
 
461
}
 
462
 
 
463
WRITE32_MEMBER(crystal_state::DMA0_w)
 
464
{
 
465
        DMA_w(&space, 0, data, mem_mask);
 
466
}
 
467
 
 
468
READ32_MEMBER(crystal_state::DMA1_r)
 
469
{
 
470
        return m_DMActrl[1];
 
471
}
 
472
 
 
473
WRITE32_MEMBER(crystal_state::DMA1_w)
 
474
{
 
475
        DMA_w(&space, 1, data, mem_mask);
 
476
}
 
477
 
 
478
 
 
479
static ADDRESS_MAP_START( crystal_mem, AS_PROGRAM, 32, crystal_state )
470
480
        AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_WRITENOP
471
481
 
472
482
        AM_RANGE(0x01200000, 0x0120000f) AM_READ(Input_r)
483
493
        AM_RANGE(0x01800810, 0x01800813) AM_READWRITE(DMA1_r, DMA1_w)
484
494
 
485
495
        AM_RANGE(0x01800c04, 0x01800c07) AM_WRITE(IntAck_w)
486
 
        AM_RANGE(0x01800000, 0x0180ffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_sysregs)
487
 
        AM_RANGE(0x02000000, 0x027fffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_workram)
 
496
        AM_RANGE(0x01800000, 0x0180ffff) AM_RAM AM_SHARE("sysregs")
 
497
        AM_RANGE(0x02000000, 0x027fffff) AM_RAM AM_SHARE("workram")
488
498
 
489
499
        AM_RANGE(0x030000a4, 0x030000a7) AM_READWRITE(FlipCount_r, FlipCount_w)
490
500
 
491
 
        AM_RANGE(0x03000000, 0x0300ffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_vidregs)
492
 
        AM_RANGE(0x03800000, 0x03ffffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_textureram)
493
 
        AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_frameram)
494
 
        AM_RANGE(0x04800000, 0x04800fff) AM_DEVREADWRITE("vrender", vr0_snd_read, vr0_snd_write)
 
501
        AM_RANGE(0x03000000, 0x0300ffff) AM_RAM AM_SHARE("vidregs")
 
502
        AM_RANGE(0x03800000, 0x03ffffff) AM_RAM AM_SHARE("textureram")
 
503
        AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_SHARE("frameram")
 
504
        AM_RANGE(0x04800000, 0x04800fff) AM_DEVREADWRITE_LEGACY("vrender", vr0_snd_read, vr0_snd_write)
495
505
 
496
506
        AM_RANGE(0x05000000, 0x05000003) AM_READWRITE(FlashCmd_r, FlashCmd_w)
497
507
        AM_RANGE(0x05000000, 0x05ffffff) AM_ROMBANK("bank1")
498
508
 
499
 
        AM_RANGE(0x44414F4C, 0x44414F7F) AM_RAM AM_BASE_MEMBER(crystal_state, m_ResetPatch)
 
509
        AM_RANGE(0x44414F4C, 0x44414F7F) AM_RAM AM_SHARE("reset_patch")
500
510
 
501
511
ADDRESS_MAP_END
502
512
 
537
547
                0xdef4d4fa
538
548
        };
539
549
 
540
 
        memcpy(state->m_ResetPatch, Patch, sizeof(Patch));
 
550
        memcpy(state->m_reset_patch, Patch, sizeof(Patch));
541
551
#else
542
552
        static const UINT8 Patch[] =
543
553
        {
546
556
                0x20,0x3A,0xD0,0xA1,0xFA,0xD4,0xF4,0xDE
547
557
        };
548
558
 
549
 
        memcpy(state->m_ResetPatch, Patch, sizeof(Patch));
 
559
        memcpy(state->m_reset_patch, Patch, sizeof(Patch));
550
560
#endif
551
561
}
552
562
 
555
565
        crystal_state *state = machine.driver_data<crystal_state>();
556
566
 
557
567
        if (state->m_Bank <= 2)
558
 
                memory_set_bankptr(machine, "bank1", machine.region("user1")->base() + state->m_Bank * 0x1000000);
 
568
                state->membank("bank1")->set_base(state->memregion("user1")->base() + state->m_Bank * 0x1000000);
559
569
        else
560
 
                memory_set_bankptr(machine, "bank1", machine.region("user2")->base());
 
570
                state->membank("bank1")->set_base(state->memregion("user2")->base());
561
571
}
562
572
 
563
573
static MACHINE_START( crystal )
566
576
        int i;
567
577
 
568
578
        state->m_maincpu = machine.device("maincpu");
569
 
        state->m_ds1302 = machine.device("rtc");
 
579
        state->m_ds1302 = machine.device<ds1302_device>("rtc");
570
580
        state->m_vr0video = machine.device("vr0");
571
581
 
572
582
        device_set_irq_callback(machine.device("maincpu"), icallback);
601
611
        state->m_IntHigh = 0;
602
612
        device_set_irq_callback(machine.device("maincpu"), icallback);
603
613
        state->m_Bank = 0;
604
 
        memory_set_bankptr(machine, "bank1", machine.region("user1")->base() + 0);
 
614
        state->membank("bank1")->set_base(state->memregion("user1")->base() + 0);
605
615
        state->m_FlashCmd = 0xff;
606
616
        state->m_OldPort4 = 0;
607
617
 
660
670
        }
661
671
 
662
672
        Visible  = (UINT16*) Front;
663
 
        DrawDest = (UINT16 *) state->m_frameram;
 
673
        // ERROR: This cast is NOT endian-safe without the use of BYTE/WORD/DWORD_XOR_* macros!
 
674
        DrawDest = reinterpret_cast<UINT16 *>(state->m_frameram.target());
664
675
 
665
676
 
666
677
        if (GetVidReg(space, 0x8c) & 0x80)
677
688
        tail = GetVidReg(space, 0x80);
678
689
        while ((head & 0x7ff) != (tail & 0x7ff))
679
690
        {
680
 
                DoFlip = vrender0_ProcessPacket(state->m_vr0video, 0x03800000 + head * 64, DrawDest, (UINT8*)state->m_textureram);
 
691
                // ERROR: This cast is NOT endian-safe without the use of BYTE/WORD/DWORD_XOR_* macros!
 
692
                DoFlip = vrender0_ProcessPacket(state->m_vr0video, 0x03800000 + head * 64, DrawDest, reinterpret_cast<UINT8*>(state->m_textureram.target()));
681
693
                head++;
682
694
                head &= 0x7ff;
683
695
                if (DoFlip)
845
857
        MCFG_PALETTE_INIT(RRRRR_GGGGGG_BBBBB)
846
858
        MCFG_PALETTE_LENGTH(65536)
847
859
 
848
 
        MCFG_DS1302_ADD("rtc")
 
860
        MCFG_DS1302_ADD("rtc", XTAL_32_768kHz)
849
861
 
850
862
        MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
851
863
 
946
958
 
947
959
static DRIVER_INIT(crysking)
948
960
{
949
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
 
961
        UINT16 *Rom = (UINT16*) machine.root_device().memregion("user1")->base();
950
962
 
951
963
        //patch the data feed by the protection
952
964
 
965
977
 
966
978
static DRIVER_INIT(evosocc)
967
979
{
968
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
 
980
        UINT16 *Rom = (UINT16*) machine.root_device().memregion("user1")->base();
969
981
        Rom += 0x1000000 * 2 / 2;
970
982
 
971
983
        Rom[WORD_XOR_LE(0x97388E/2)] = 0x90FC;  //PUSH R2..R7
983
995
 
984
996
static DRIVER_INIT(topbladv)
985
997
{
986
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
 
998
        UINT16 *Rom = (UINT16*) machine.root_device().memregion("user1")->base();
987
999
 
988
1000
        Rom[WORD_XOR_LE(0x12d7a/2)] = 0x90FC;   //PUSH R7-R6-R5-R4-R3-R2
989
1001
        Rom[WORD_XOR_LE(0x12d7c/2)] = 0x9001;   //PUSH R0
1001
1013
 
1002
1014
static DRIVER_INIT(officeye)
1003
1015
{
1004
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
 
1016
        UINT16 *Rom = (UINT16*) machine.root_device().memregion("user1")->base();
1005
1017
 
1006
1018
        Rom[WORD_XOR_LE(0x9c9e/2)] = 0x901C;    //PUSH R4-R3-R2
1007
1019
        Rom[WORD_XOR_LE(0x9ca0/2)] = 0x9001;    //PUSH R0