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Viewing changes to src/mame/drivers/ddribble.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/ddribble.c
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}
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static WRITE8_HANDLER( ddribble_bankswitch_w )
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{
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        memory_set_bank(space->machine(), "bank1", data & 0x0f);
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}
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static READ8_HANDLER( ddribble_sharedram_r )
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{
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        ddribble_state *state = space->machine().driver_data<ddribble_state>();
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        return state->m_sharedram[offset];
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}
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static WRITE8_HANDLER( ddribble_sharedram_w )
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{
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        ddribble_state *state = space->machine().driver_data<ddribble_state>();
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        state->m_sharedram[offset] = data;
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}
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static READ8_HANDLER( ddribble_snd_sharedram_r )
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{
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        ddribble_state *state = space->machine().driver_data<ddribble_state>();
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        return state->m_snd_sharedram[offset];
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}
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static WRITE8_HANDLER( ddribble_snd_sharedram_w )
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{
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        ddribble_state *state = space->machine().driver_data<ddribble_state>();
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        state->m_snd_sharedram[offset] = data;
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}
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static WRITE8_HANDLER( ddribble_coin_counter_w )
 
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WRITE8_MEMBER(ddribble_state::ddribble_bankswitch_w)
 
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{
 
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        membank("bank1")->set_entry(data & 0x0f);
 
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}
 
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READ8_MEMBER(ddribble_state::ddribble_sharedram_r)
 
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{
 
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        return m_sharedram[offset];
 
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}
 
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WRITE8_MEMBER(ddribble_state::ddribble_sharedram_w)
 
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{
 
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        m_sharedram[offset] = data;
 
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}
 
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READ8_MEMBER(ddribble_state::ddribble_snd_sharedram_r)
 
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{
 
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        return m_snd_sharedram[offset];
 
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}
 
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WRITE8_MEMBER(ddribble_state::ddribble_snd_sharedram_w)
 
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{
 
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        m_snd_sharedram[offset] = data;
 
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}
 
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WRITE8_MEMBER(ddribble_state::ddribble_coin_counter_w)
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{
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        /* b4-b7: unused */
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        /* b2-b3: unknown */
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        /* b1: coin counter 2 */
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        /* b0: coin counter 1 */
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        coin_counter_w(space->machine(), 0,(data) & 0x01);
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        coin_counter_w(space->machine(), 1,(data >> 1) & 0x01);
 
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        coin_counter_w(machine(), 0,(data) & 0x01);
 
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        coin_counter_w(machine(), 1,(data >> 1) & 0x01);
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}
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static READ8_DEVICE_HANDLER( ddribble_vlm5030_busy_r )
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static WRITE8_DEVICE_HANDLER( ddribble_vlm5030_ctrl_w )
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{
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        ddribble_state *state = device->machine().driver_data<ddribble_state>();
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        UINT8 *SPEECH_ROM = device->machine().region("vlm")->base();
 
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        UINT8 *SPEECH_ROM = state->memregion("vlm")->base();
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        /* b7 : vlm data bus OE   */
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}
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static ADDRESS_MAP_START( cpu0_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpu0_map, AS_PROGRAM, 8, ddribble_state )
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        AM_RANGE(0x0000, 0x0004) AM_WRITE(K005885_0_w)                                                                                          /* video registers (005885 #1) */
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        AM_RANGE(0x0800, 0x0804) AM_WRITE(K005885_1_w)                                                                                          /* video registers (005885 #2) */
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        AM_RANGE(0x1800, 0x187f) AM_RAM AM_BASE_MEMBER(ddribble_state, m_paletteram)                                                                            /* palette */
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        AM_RANGE(0x2000, 0x2fff) AM_RAM_WRITE(ddribble_fg_videoram_w) AM_BASE_MEMBER(ddribble_state, m_fg_videoram)     /* Video RAM 1 */
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        AM_RANGE(0x3000, 0x3fff) AM_RAM AM_BASE_MEMBER(ddribble_state, m_spriteram_1)                                                           /* Object RAM 1 */
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        AM_RANGE(0x4000, 0x5fff) AM_RAM AM_BASE_MEMBER(ddribble_state, m_sharedram)                                                                     /* shared RAM with CPU #1 */
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        AM_RANGE(0x6000, 0x6fff) AM_RAM_WRITE(ddribble_bg_videoram_w) AM_BASE_MEMBER(ddribble_state, m_bg_videoram)     /* Video RAM 2 */
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        AM_RANGE(0x7000, 0x7fff) AM_RAM AM_BASE_MEMBER(ddribble_state, m_spriteram_2)                                                           /* Object RAM 2 */
 
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        AM_RANGE(0x1800, 0x187f) AM_RAM AM_SHARE("paletteram")                                                                          /* palette */
 
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        AM_RANGE(0x2000, 0x2fff) AM_RAM_WRITE(ddribble_fg_videoram_w) AM_SHARE("fg_videoram")   /* Video RAM 1 */
 
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        AM_RANGE(0x3000, 0x3fff) AM_RAM AM_SHARE("spriteram_1")                                                         /* Object RAM 1 */
 
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        AM_RANGE(0x4000, 0x5fff) AM_RAM AM_SHARE("sharedram")                                                                   /* shared RAM with CPU #1 */
 
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        AM_RANGE(0x6000, 0x6fff) AM_RAM_WRITE(ddribble_bg_videoram_w) AM_SHARE("bg_videoram")   /* Video RAM 2 */
 
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        AM_RANGE(0x7000, 0x7fff) AM_RAM AM_SHARE("spriteram_2")                                                         /* Object RAM 2 */
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        AM_RANGE(0x8000, 0x8000) AM_WRITE(ddribble_bankswitch_w)                                                                                /* bankswitch control */
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        AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank1")                                                                                                            /* banked ROM */
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        AM_RANGE(0xa000, 0xffff) AM_ROM                                                                                                                         /* ROM */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( cpu1_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpu1_map, AS_PROGRAM, 8, ddribble_state )
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        AM_RANGE(0x0000, 0x1fff) AM_READWRITE(ddribble_sharedram_r, ddribble_sharedram_w)                       /* shared RAM with CPU #0 */
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        AM_RANGE(0x2000, 0x27ff) AM_READWRITE(ddribble_snd_sharedram_r, ddribble_snd_sharedram_w)       /* shared RAM with CPU #2 */
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        AM_RANGE(0x2800, 0x2800) AM_READ_PORT("DSW1")
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        AM_RANGE(0x8000, 0xffff) AM_ROM                                                                                                                 /* ROM */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( cpu2_map, AS_PROGRAM, 8 )
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        AM_RANGE(0x0000, 0x07ff) AM_RAM AM_BASE_MEMBER(ddribble_state, m_snd_sharedram)         /* shared RAM with CPU #1 */
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        AM_RANGE(0x1000, 0x1001) AM_DEVREADWRITE("ymsnd", ym2203_r, ym2203_w)   /* YM2203 */
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        AM_RANGE(0x3000, 0x3000) AM_DEVWRITE("vlm", vlm5030_data_w)                     /* Speech data */
 
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static ADDRESS_MAP_START( cpu2_map, AS_PROGRAM, 8, ddribble_state )
 
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        AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("snd_sharedram")               /* shared RAM with CPU #1 */
 
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        AM_RANGE(0x1000, 0x1001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)    /* YM2203 */
 
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        AM_RANGE(0x3000, 0x3000) AM_DEVWRITE_LEGACY("vlm", vlm5030_data_w)                      /* Speech data */
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        AM_RANGE(0x8000, 0xffff) AM_ROM                                                                         /* ROM */
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ADDRESS_MAP_END
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static MACHINE_START( ddribble )
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{
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        ddribble_state *state = machine.driver_data<ddribble_state>();
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        UINT8 *ROM = machine.region("maincpu")->base();
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        memory_configure_bank(machine, "bank1", 0, 5, &ROM[0x10000], 0x2000);
 
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        UINT8 *ROM = state->memregion("maincpu")->base();
 
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        state->membank("bank1")->configure_entries(0, 5, &ROM[0x10000], 0x2000);
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        state->m_filter1 = machine.device("filter1");
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        state->m_filter2 = machine.device("filter2");