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Viewing changes to src/mame/drivers/suna8.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/suna8.c
60
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static DRIVER_INIT( hardhead )
62
62
{
63
 
        UINT8 *rom = machine.region("maincpu")->base();
 
63
        UINT8 *rom = machine.root_device().memregion("maincpu")->base();
64
64
        int i;
65
65
 
66
66
        for (i = 0; i < 0x8000; i++)
75
75
                        rom[i] = BITSWAP8(rom[i], 7,6,5,3,4,2,1,0) ^ 0x58;
76
76
        }
77
77
 
78
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
 
78
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
79
79
}
80
80
 
81
81
/* Non encrypted bootleg */
82
82
static DRIVER_INIT( hardhedb )
83
83
{
84
84
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
85
 
        space->set_decrypted_region(0x0000, 0x7fff, machine.region("maincpu")->base() + 0x48000);
86
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
 
85
        space->set_decrypted_region(0x0000, 0x7fff, machine.root_device().memregion("maincpu")->base() + 0x48000);
 
86
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
87
87
}
88
88
 
89
89
/***************************************************************************
95
95
static UINT8 *brickzn_decrypt(running_machine &machine)
96
96
{
97
97
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
98
 
        UINT8   *RAM    =       machine.region("maincpu")->base();
99
 
        size_t  size    =       machine.region("maincpu")->bytes();
 
98
        UINT8   *RAM    =       machine.root_device().memregion("maincpu")->base();
 
99
        size_t  size    =       machine.root_device().memregion("maincpu")->bytes();
100
100
        UINT8   *decrypt = auto_alloc_array(machine, UINT8, size);
101
101
        int i;
102
102
 
137
137
 
138
138
static DRIVER_INIT( brickzn )
139
139
{
140
 
        UINT8   *RAM    =       machine.region("maincpu")->base();
 
140
        UINT8   *RAM    =       machine.root_device().memregion("maincpu")->base();
141
141
        UINT8   *decrypt = brickzn_decrypt(machine);
142
142
        int i;
143
143
 
162
162
        decrypt[0x24b5] = 0x00; // HALT -> NOP
163
163
        decrypt[0x2583] = 0x00; // HALT -> NOP
164
164
 
165
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
166
 
        memory_configure_bank_decrypted(machine, "bank1", 0, 16, decrypt + 0x10000, 0x4000);
 
165
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
 
166
        machine.root_device().membank("bank1")->configure_decrypted_entries(0, 16, decrypt + 0x10000, 0x4000);
167
167
}
168
168
 
169
169
static DRIVER_INIT( brickzn3 )
170
170
{
171
 
        UINT8   *RAM    =       machine.region("maincpu")->base();
 
171
        UINT8   *RAM    =       machine.root_device().memregion("maincpu")->base();
172
172
        UINT8   *decrypt = brickzn_decrypt(machine);
173
173
        int i;
174
174
 
193
193
        decrypt[0x2487] = 0x00; // HALT -> NOP
194
194
        decrypt[0x256c] = 0x00; // HALT -> NOP
195
195
 
196
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
197
 
        memory_configure_bank_decrypted(machine, "bank1", 0, 16, decrypt + 0x10000, 0x4000);
 
196
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
 
197
        machine.root_device().membank("bank1")->configure_decrypted_entries(0, 16, decrypt + 0x10000, 0x4000);
198
198
}
199
199
 
200
200
 
205
205
static DRIVER_INIT( hardhea2 )
206
206
{
207
207
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
208
 
        UINT8   *RAM    =       machine.region("maincpu")->base();
209
 
        size_t  size    =       machine.region("maincpu")->bytes();
 
208
        UINT8   *RAM    =       machine.root_device().memregion("maincpu")->base();
 
209
        size_t  size    =       machine.root_device().memregion("maincpu")->bytes();
210
210
        UINT8   *decrypt =      auto_alloc_array(machine, UINT8, size);
211
211
        UINT8 x;
212
212
        int i;
280
280
                        RAM[i] = BITSWAP8(RAM[i], 5,6,7,4,3,2,1,0) ^ 0x41;
281
281
        }
282
282
 
283
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
284
 
        memory_configure_bank(machine, "bank2", 0, 2, auto_alloc_array(machine, UINT8, 0x2000 * 2), 0x2000);
 
283
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
 
284
        machine.root_device().membank("bank2")->configure_entries(0, 2, auto_alloc_array(machine, UINT8, 0x2000 * 2), 0x2000);
285
285
}
286
286
 
287
287
 
292
292
static DRIVER_INIT( starfigh )
293
293
{
294
294
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
295
 
        UINT8   *RAM    =       machine.region("maincpu")->base();
296
 
        size_t  size    =       machine.region("maincpu")->bytes();
 
295
        UINT8   *RAM    =       machine.root_device().memregion("maincpu")->base();
 
296
        size_t  size    =       machine.root_device().memregion("maincpu")->bytes();
297
297
        UINT8   *decrypt =      auto_alloc_array(machine, UINT8, size);
298
298
        UINT8 x;
299
299
        int i;
349
349
                        RAM[i] = BITSWAP8(RAM[i], 5,6,7,4,3,2,1,0) ^ 0x45;
350
350
        }
351
351
 
352
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
 
352
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
353
353
}
354
354
 
355
355
 
360
360
static DRIVER_INIT( sparkman )
361
361
{
362
362
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
363
 
        UINT8   *RAM    =       machine.region("maincpu")->base();
364
 
        size_t  size    =       machine.region("maincpu")->bytes();
 
363
        UINT8   *RAM    =       machine.root_device().memregion("maincpu")->base();
 
364
        size_t  size    =       machine.root_device().memregion("maincpu")->bytes();
365
365
        UINT8   *decrypt =      auto_alloc_array(machine, UINT8, size);
366
366
        UINT8 x;
367
367
        int i;
417
417
                        RAM[i] = BITSWAP8(RAM[i], 5,6,7,4,3,2,1,0) ^ 0x44;
418
418
        }
419
419
 
420
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
 
420
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
421
421
}
422
422
 
423
423
/***************************************************************************
432
432
                                Hard Head
433
433
***************************************************************************/
434
434
 
435
 
static READ8_HANDLER( hardhead_protection_r )
 
435
READ8_MEMBER(suna8_state::hardhead_protection_r)
436
436
{
437
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
438
 
        UINT8 protection_val = state->m_protection_val;
 
437
        UINT8 protection_val = m_protection_val;
439
438
 
440
439
        if (protection_val & 0x80)
441
440
                return  ((~offset & 0x20)                       ?       0x20 : 0) |
446
445
                                (((offset ^ protection_val) & 0x01)     ?       0x84 : 0);
447
446
}
448
447
 
449
 
static WRITE8_HANDLER( hardhead_protection_w )
 
448
WRITE8_MEMBER(suna8_state::hardhead_protection_w)
450
449
{
451
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
452
450
 
453
 
        if (data & 0x80)        state->m_protection_val = data;
454
 
        else                            state->m_protection_val = offset & 1;
 
451
        if (data & 0x80)        m_protection_val = data;
 
452
        else                            m_protection_val = offset & 1;
455
453
}
456
454
 
457
455
 
467
465
                                Hard Head
468
466
***************************************************************************/
469
467
 
470
 
static READ8_HANDLER( hardhead_ip_r )
 
468
READ8_MEMBER(suna8_state::hardhead_ip_r)
471
469
{
472
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
473
470
 
474
 
        switch (*state->m_hardhead_ip)
 
471
        switch (*m_hardhead_ip)
475
472
        {
476
 
                case 0: return input_port_read(space->machine(), "P1");
477
 
                case 1: return input_port_read(space->machine(), "P2");
478
 
                case 2: return input_port_read(space->machine(), "DSW1");
479
 
                case 3: return input_port_read(space->machine(), "DSW2");
 
473
                case 0: return ioport("P1")->read();
 
474
                case 1: return ioport("P2")->read();
 
475
                case 2: return ioport("DSW1")->read();
 
476
                case 3: return ioport("DSW2")->read();
480
477
                default:
481
 
                        logerror("CPU #0 - PC %04X: Unknown IP read: %02X\n", cpu_get_pc(&space->device()), *state->m_hardhead_ip);
 
478
                        logerror("CPU #0 - PC %04X: Unknown IP read: %02X\n", cpu_get_pc(&space.device()), *m_hardhead_ip);
482
479
                        return 0xff;
483
480
        }
484
481
}
488
485
    ---4 ----
489
486
    ---- 3210   ROM Bank
490
487
*/
491
 
static WRITE8_HANDLER( hardhead_bankswitch_w )
 
488
WRITE8_MEMBER(suna8_state::hardhead_bankswitch_w)
492
489
{
493
490
        int bank = data & 0x0f;
494
491
 
495
 
        if (data & ~0xef)       logerror("CPU #0 - PC %04X: unknown bank bits: %02X\n",cpu_get_pc(&space->device()),data);
496
 
        memory_set_bank(space->machine(), "bank1", bank);
 
492
        if (data & ~0xef)       logerror("CPU #0 - PC %04X: unknown bank bits: %02X\n",cpu_get_pc(&space.device()),data);
 
493
        membank("bank1")->set_entry(bank);
497
494
}
498
495
 
499
496
 
503
500
    ---- -2--   Flip Screen
504
501
    ---- --10
505
502
*/
506
 
static WRITE8_HANDLER( hardhead_flipscreen_w )
 
503
WRITE8_MEMBER(suna8_state::hardhead_flipscreen_w)
507
504
{
508
 
        flip_screen_set(space->machine(),     data & 0x04);
509
 
        coin_lockout_w ( space->machine(), 0,   data & 0x08);
510
 
        coin_lockout_w ( space->machine(), 1,   data & 0x10);
 
505
        flip_screen_set(data & 0x04);
 
506
        coin_lockout_w ( machine(), 0,  data & 0x08);
 
507
        coin_lockout_w ( machine(), 1,  data & 0x10);
511
508
}
512
509
 
513
 
static ADDRESS_MAP_START( hardhead_map, AS_PROGRAM, 8 )
 
510
static ADDRESS_MAP_START( hardhead_map, AS_PROGRAM, 8, suna8_state )
514
511
        AM_RANGE(0x0000, 0x7fff) AM_ROM                                                         // ROM
515
512
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")                                            // Banked ROM
516
513
        AM_RANGE(0xc000, 0xd7ff) AM_RAM                                                         // RAM
517
 
        AM_RANGE(0xd800, 0xd9ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE_GENERIC(paletteram)     // Palette
518
 
        AM_RANGE(0xda00, 0xda00) AM_RAM_READ(hardhead_ip_r) AM_BASE_MEMBER(suna8_state, m_hardhead_ip)  // Input Port Select
519
 
        AM_RANGE(0xda80, 0xda80) AM_READWRITE(soundlatch2_r, hardhead_bankswitch_w      )       // ROM Banking
520
 
        AM_RANGE(0xdb00, 0xdb00) AM_WRITE(soundlatch_w                  )       // To Sound CPU
 
514
        AM_RANGE(0xd800, 0xd9ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_byte_be_w) AM_SHARE("paletteram")     // Palette
 
515
        AM_RANGE(0xda00, 0xda00) AM_RAM_READ(hardhead_ip_r) AM_SHARE("hardhead_ip")     // Input Port Select
 
516
        AM_RANGE(0xda80, 0xda80) AM_READ(soundlatch2_byte_r) AM_WRITE(hardhead_bankswitch_w     )       // ROM Banking
 
517
        AM_RANGE(0xdb00, 0xdb00) AM_WRITE(soundlatch_byte_w                     )       // To Sound CPU
521
518
        AM_RANGE(0xdb80, 0xdb80) AM_WRITE(hardhead_flipscreen_w )       // Flip Screen + Coin Lockout
522
519
        AM_RANGE(0xdc00, 0xdc00) AM_NOP                                                         // <- R (after bank select)
523
520
        AM_RANGE(0xdc80, 0xdc80) AM_NOP                                                         // <- R (after bank select)
524
521
        AM_RANGE(0xdd00, 0xdd00) AM_NOP                                                         // <- R (after ip select)
525
522
        AM_RANGE(0xdd80, 0xddff) AM_READWRITE(hardhead_protection_r, hardhead_protection_w      )       // Protection
526
 
        AM_RANGE(0xe000, 0xffff) AM_RAM_WRITE(suna8_spriteram_w) AM_BASE_MEMBER(suna8_state, m_spriteram)       // Sprites
 
523
        AM_RANGE(0xe000, 0xffff) AM_RAM_WRITE(suna8_spriteram_w) AM_SHARE("spriteram")  // Sprites
527
524
ADDRESS_MAP_END
528
525
 
529
526
 
530
 
static ADDRESS_MAP_START( hardhead_io_map, AS_IO, 8 )
 
527
static ADDRESS_MAP_START( hardhead_io_map, AS_IO, 8, suna8_state )
531
528
        ADDRESS_MAP_GLOBAL_MASK(0xff)
532
529
        AM_RANGE(0x00, 0x00) AM_READNOP // ? IRQ Ack
533
530
ADDRESS_MAP_END
543
540
    ---- 3---
544
541
    ---- -210   ROM Bank
545
542
*/
546
 
static WRITE8_HANDLER( rranger_bankswitch_w )
 
543
WRITE8_MEMBER(suna8_state::rranger_bankswitch_w)
547
544
{
548
545
        int bank = data & 0x07;
549
546
        if ((~data & 0x10) && (bank >= 4))      bank += 4;
550
547
 
551
 
        if (data & ~0xf7)       logerror("CPU #0 - PC %04X: unknown bank bits: %02X\n",cpu_get_pc(&space->device()),data);
552
 
 
553
 
        memory_set_bank(space->machine(), "bank1", bank);
554
 
 
555
 
        flip_screen_set(space->machine(),     data & 0x20);
556
 
        coin_lockout_w ( space->machine(), 0,   data & 0x40);
557
 
        coin_lockout_w ( space->machine(), 1,   data & 0x80);
 
548
        if (data & ~0xf7)       logerror("CPU #0 - PC %04X: unknown bank bits: %02X\n",cpu_get_pc(&space.device()),data);
 
549
 
 
550
        membank("bank1")->set_entry(bank);
 
551
 
 
552
        flip_screen_set(data & 0x20);
 
553
        coin_lockout_w ( machine(), 0,  data & 0x40);
 
554
        coin_lockout_w ( machine(), 1,  data & 0x80);
558
555
}
559
556
 
560
557
/*
565
562
    ---- --1-   1 -> Interlude screens
566
563
    ---- ---0
567
564
*/
568
 
static READ8_HANDLER( rranger_soundstatus_r )
 
565
READ8_MEMBER(suna8_state::rranger_soundstatus_r)
569
566
{
570
 
        soundlatch2_r(space, offset);
 
567
        soundlatch2_byte_r(space, offset);
571
568
        return 0x02;
572
569
}
573
570
 
574
 
static WRITE8_HANDLER( sranger_prot_w )
 
571
WRITE8_MEMBER(suna8_state::sranger_prot_w)
575
572
{
576
573
        /* check code at 0x2ce2 (in sranger), protection is so dire that I can't even exactly
577
574
       estabilish if what I'm doing can be considered or not a kludge... -AS */
578
 
        space->write_byte(0xcd99,0xff);
 
575
        space.write_byte(0xcd99,0xff);
579
576
}
580
577
 
581
 
static ADDRESS_MAP_START( rranger_map, AS_PROGRAM, 8 )
 
578
static ADDRESS_MAP_START( rranger_map, AS_PROGRAM, 8, suna8_state )
582
579
        AM_RANGE(0x0000, 0x7fff) AM_ROM                                                         // ROM
583
580
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")                                            // Banked ROM
584
 
        AM_RANGE(0xc000, 0xc000) AM_READWRITE(watchdog_reset_r, soundlatch_w)   // To Sound CPU
 
581
        AM_RANGE(0xc000, 0xc000) AM_READWRITE(watchdog_reset_r, soundlatch_byte_w)      // To Sound CPU
585
582
        AM_RANGE(0xc002, 0xc002) AM_WRITE(rranger_bankswitch_w  )       // ROM Banking
586
583
        AM_RANGE(0xc002, 0xc002) AM_READ_PORT("P1")                                     // P1 (Inputs)
587
584
        AM_RANGE(0xc003, 0xc003) AM_READ_PORT("P2")                                     // P2
590
587
        AM_RANGE(0xc280, 0xc280) AM_WRITENOP    // ? NMI Ack
591
588
        AM_RANGE(0xc280, 0xc280) AM_READ_PORT("DSW1")                           // DSW 1
592
589
        AM_RANGE(0xc2c0, 0xc2c0) AM_READ_PORT("DSW2")                           // DSW 2
593
 
        AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE_GENERIC(paletteram)     // Palette
 
590
        AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_byte_be_w) AM_SHARE("paletteram")     // Palette
594
591
        AM_RANGE(0xc800, 0xdfff) AM_RAM                                                         // RAM
595
 
        AM_RANGE(0xe000, 0xffff) AM_RAM_WRITE(suna8_spriteram_w) AM_BASE_MEMBER(suna8_state, m_spriteram)       // Sprites
 
592
        AM_RANGE(0xe000, 0xffff) AM_RAM_WRITE(suna8_spriteram_w) AM_SHARE("spriteram")  // Sprites
596
593
ADDRESS_MAP_END
597
594
 
598
595
 
599
 
static ADDRESS_MAP_START( rranger_io_map, AS_IO, 8 )
 
596
static ADDRESS_MAP_START( rranger_io_map, AS_IO, 8, suna8_state )
600
597
        ADDRESS_MAP_GLOBAL_MASK(0xff)
601
598
        AM_RANGE(0x00, 0x00) AM_READNOP // ? IRQ Ack
602
599
ADDRESS_MAP_END
608
605
/*
609
606
?
610
607
*/
611
 
static READ8_HANDLER( brickzn_c140_r )
 
608
READ8_MEMBER(suna8_state::brickzn_c140_r)
612
609
{
613
610
        return 0xff;
614
611
}
615
612
 
616
613
/*
617
614
*/
618
 
static WRITE8_HANDLER( brickzn_palettebank_w )
 
615
WRITE8_MEMBER(suna8_state::brickzn_palettebank_w)
619
616
{
620
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
621
617
 
622
 
        state->m_palettebank = (data >> 1) & 1;
623
 
        if (data & ~0x02)       logerror("CPU #0 - PC %04X: unknown palettebank bits: %02X\n",cpu_get_pc(&space->device()),data);
 
618
        m_palettebank = (data >> 1) & 1;
 
619
        if (data & ~0x02)       logerror("CPU #0 - PC %04X: unknown palettebank bits: %02X\n",cpu_get_pc(&space.device()),data);
624
620
 
625
621
        /* Also used as soundlatch - depending on c0c0? */
626
 
        soundlatch_w(space,0,data);
 
622
        soundlatch_byte_w(space,0,data);
627
623
}
628
624
 
629
625
/*
631
627
    ---- --1-   Ram Bank
632
628
    ---- ---0   Flip Screen
633
629
*/
634
 
static WRITE8_HANDLER( brickzn_spritebank_w )
 
630
WRITE8_MEMBER(suna8_state::brickzn_spritebank_w)
635
631
{
636
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
637
632
 
638
 
        state->m_spritebank = (data >> 1) & 1;
639
 
        if (data & ~0x03)       logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space->device()),data);
640
 
        flip_screen_set(space->machine(),  data & 0x01 );
 
633
        m_spritebank = (data >> 1) & 1;
 
634
        if (data & ~0x03)       logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space.device()),data);
 
635
        flip_screen_set(data & 0x01 );
641
636
}
642
637
 
643
 
static WRITE8_HANDLER( brickzn_unknown_w )
 
638
WRITE8_MEMBER(suna8_state::brickzn_unknown_w)
644
639
{
645
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
646
640
 
647
 
        state->m_unknown = data;
 
641
        m_unknown = data;
648
642
}
649
643
 
650
644
/*
651
645
    7654 ----
652
646
    ---- 3210   ROM Bank
653
647
*/
654
 
static WRITE8_HANDLER( brickzn_rombank_w )
 
648
WRITE8_MEMBER(suna8_state::brickzn_rombank_w)
655
649
{
656
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
657
650
        int bank = data & 0x0f;
658
651
 
659
 
        if (data & ~0x0f)       logerror("CPU #0 - PC %04X: unknown rom bank bits: %02X\n",cpu_get_pc(&space->device()),data);
 
652
        if (data & ~0x0f)       logerror("CPU #0 - PC %04X: unknown rom bank bits: %02X\n",cpu_get_pc(&space.device()),data);
660
653
 
661
 
        memory_set_bank(space->machine(), "bank1", bank);
662
 
        state->m_rombank = data;
 
654
        membank("bank1")->set_entry(bank);
 
655
        m_rombank = data;
663
656
}
664
657
 
665
 
static ADDRESS_MAP_START( brickzn_map, AS_PROGRAM, 8 )
 
658
static ADDRESS_MAP_START( brickzn_map, AS_PROGRAM, 8, suna8_state )
666
659
        AM_RANGE(0x0000, 0x7fff) AM_ROM                                                                         // ROM
667
660
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")                                                            // Banked ROM
668
661
        AM_RANGE(0xc040, 0xc040) AM_WRITE(brickzn_rombank_w                             )       // ROM Bank
676
669
        AM_RANGE(0xc108, 0xc108) AM_READ_PORT("TRACK1")                                 // P1 (Analog)
677
670
        AM_RANGE(0xc10c, 0xc10c) AM_READ_PORT("TRACK2")                                 // P2
678
671
        AM_RANGE(0xc140, 0xc140) AM_READ(brickzn_c140_r)                                // ???
679
 
        AM_RANGE(0xc600, 0xc7ff) AM_READWRITE(suna8_banked_paletteram_r, brickzn_banked_paletteram_w)   // Palette (Banked)
 
672
        AM_RANGE(0xc600, 0xc7ff) AM_READWRITE(banked_paletteram_r, brickzn_banked_paletteram_w) // Palette (Banked)
680
673
        AM_RANGE(0xc800, 0xdfff) AM_RAM                                                                 // RAM
681
674
        AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w)       // Sprites (Banked)
682
675
ADDRESS_MAP_END
687
680
***************************************************************************/
688
681
 
689
682
/* Probably wrong: */
690
 
static WRITE8_HANDLER( hardhea2_nmi_w )
 
683
WRITE8_MEMBER(suna8_state::hardhea2_nmi_w)
691
684
{
692
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
693
685
 
694
 
        state->m_nmi_enable = data & 0x01;
695
 
//  if (data & ~0x01)   logerror("CPU #0 - PC %04X: unknown nmi bits: %02X\n",cpu_get_pc(&space->device()),data);
 
686
        m_nmi_enable = data & 0x01;
 
687
//  if (data & ~0x01)   logerror("CPU #0 - PC %04X: unknown nmi bits: %02X\n",cpu_get_pc(&space.device()),data);
696
688
}
697
689
 
698
690
/*
699
691
    7654 321-
700
692
    ---- ---0   Flip Screen
701
693
*/
702
 
static WRITE8_HANDLER( hardhea2_flipscreen_w )
 
694
WRITE8_MEMBER(suna8_state::hardhea2_flipscreen_w)
703
695
{
704
 
        flip_screen_set(space->machine(), data & 0x01);
705
 
        if (data & ~0x01)       logerror("CPU #0 - PC %04X: unknown flipscreen bits: %02X\n",cpu_get_pc(&space->device()),data);
 
696
        flip_screen_set(data & 0x01);
 
697
        if (data & ~0x01)       logerror("CPU #0 - PC %04X: unknown flipscreen bits: %02X\n",cpu_get_pc(&space.device()),data);
706
698
}
707
699
 
708
 
static WRITE8_HANDLER( hardhea2_leds_w )
 
700
WRITE8_MEMBER(suna8_state::hardhea2_leds_w)
709
701
{
710
 
        set_led_status(space->machine(), 0, data & 0x01);
711
 
        set_led_status(space->machine(), 1, data & 0x02);
712
 
        coin_counter_w(space->machine(), 0, data & 0x04);
713
 
        if (data & ~0x07)       logerror("CPU#0  - PC %06X: unknown leds bits: %02X\n",cpu_get_pc(&space->device()),data);
 
702
        set_led_status(machine(), 0, data & 0x01);
 
703
        set_led_status(machine(), 1, data & 0x02);
 
704
        coin_counter_w(machine(), 0, data & 0x04);
 
705
        if (data & ~0x07)       logerror("CPU#0  - PC %06X: unknown leds bits: %02X\n",cpu_get_pc(&space.device()),data);
714
706
}
715
707
 
716
708
/*
718
710
    ---- --1-   Ram Bank
719
711
    ---- ---0   Ram Bank?
720
712
*/
721
 
static WRITE8_HANDLER( hardhea2_spritebank_w )
 
713
WRITE8_MEMBER(suna8_state::hardhea2_spritebank_w)
722
714
{
723
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
724
715
 
725
 
        state->m_spritebank = (data >> 1) & 1;
726
 
        if (data & ~0x02)       logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space->device()),data);
 
716
        m_spritebank = (data >> 1) & 1;
 
717
        if (data & ~0x02)       logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space.device()),data);
727
718
}
728
719
 
729
720
/*
730
721
    7654 ----
731
722
    ---- 3210   ROM Bank
732
723
*/
733
 
static WRITE8_HANDLER( hardhea2_rombank_w )
 
724
WRITE8_MEMBER(suna8_state::hardhea2_rombank_w)
734
725
{
735
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
736
726
        int bank = data & 0x0f;
737
727
 
738
 
        if (data & ~0x0f)       logerror("CPU #0 - PC %04X: unknown rom bank bits: %02X\n",cpu_get_pc(&space->device()),data);
739
 
 
740
 
        memory_set_bank(space->machine(), "bank1", bank);
741
 
 
742
 
        state->m_rombank = data;
743
 
}
744
 
 
745
 
static WRITE8_HANDLER( hardhea2_spritebank_0_w )
746
 
{
747
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
748
 
 
749
 
        state->m_spritebank = 0;
750
 
}
751
 
static WRITE8_HANDLER( hardhea2_spritebank_1_w )
752
 
{
753
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
754
 
 
755
 
        state->m_spritebank = 1;
756
 
}
757
 
 
758
 
static WRITE8_HANDLER( hardhea2_rambank_0_w )
759
 
{
760
 
        memory_set_bank(space->machine(), "bank2", 0);
761
 
}
762
 
 
763
 
static WRITE8_HANDLER( hardhea2_rambank_1_w )
764
 
{
765
 
        memory_set_bank(space->machine(), "bank2", 1);
766
 
}
767
 
 
768
 
 
769
 
static ADDRESS_MAP_START( hardhea2_map, AS_PROGRAM, 8 )
 
728
        if (data & ~0x0f)       logerror("CPU #0 - PC %04X: unknown rom bank bits: %02X\n",cpu_get_pc(&space.device()),data);
 
729
 
 
730
        membank("bank1")->set_entry(bank);
 
731
 
 
732
        m_rombank = data;
 
733
}
 
734
 
 
735
WRITE8_MEMBER(suna8_state::hardhea2_spritebank_0_w)
 
736
{
 
737
 
 
738
        m_spritebank = 0;
 
739
}
 
740
WRITE8_MEMBER(suna8_state::hardhea2_spritebank_1_w)
 
741
{
 
742
 
 
743
        m_spritebank = 1;
 
744
}
 
745
 
 
746
WRITE8_MEMBER(suna8_state::hardhea2_rambank_0_w)
 
747
{
 
748
        membank("bank2")->set_entry(0);
 
749
}
 
750
 
 
751
WRITE8_MEMBER(suna8_state::hardhea2_rambank_1_w)
 
752
{
 
753
        membank("bank2")->set_entry(1);
 
754
}
 
755
 
 
756
 
 
757
static ADDRESS_MAP_START( hardhea2_map, AS_PROGRAM, 8, suna8_state )
770
758
        AM_RANGE(0x0000, 0x7fff) AM_ROM                                                                 // ROM
771
759
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")                                                    // Banked ROM
772
760
        AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1")                                             // P1 (Inputs)
785
773
        AM_RANGE(0xc380, 0xc380) AM_WRITE(hardhea2_nmi_w                                )       // ? NMI related ?
786
774
        AM_RANGE(0xc400, 0xc400) AM_WRITE(hardhea2_leds_w                               )       // Leds + Coin Counter
787
775
        AM_RANGE(0xc480, 0xc480) AM_WRITENOP    // ~ROM Bank
788
 
        AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w                          )       // To Sound CPU
 
776
        AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_byte_w                             )       // To Sound CPU
789
777
 
790
778
        // *** Protection
791
779
        AM_RANGE(0xc50f, 0xc50f) AM_WRITE(hardhea2_spritebank_1_w )
801
789
        AM_RANGE(0xc533, 0xc533) AM_WRITE(hardhea2_rambank_0_w )
802
790
        // Protection ***
803
791
 
804
 
        AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE_GENERIC(paletteram      )       // Palette (Banked??)
 
792
        AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_byte_be_w) AM_SHARE("paletteram"      )       // Palette (Banked??)
805
793
        AM_RANGE(0xc800, 0xdfff) AM_RAMBANK("bank2")                                                    // RAM (Banked?)
806
794
        AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w)       // Sprites (Banked)
807
795
ADDRESS_MAP_END
811
799
                                Star Fighter
812
800
***************************************************************************/
813
801
 
814
 
static WRITE8_HANDLER( starfigh_spritebank_latch_w )
815
 
{
816
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
817
 
 
818
 
        state->m_spritebank_latch = (data >> 2) & 1;
819
 
        if (data & ~0x04)       logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space->device()),data);
820
 
}
821
 
 
822
 
static WRITE8_HANDLER( starfigh_spritebank_w )
823
 
{
824
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
825
 
 
826
 
        state->m_spritebank = state->m_spritebank_latch;
827
 
}
828
 
 
829
 
static ADDRESS_MAP_START( starfigh_map, AS_PROGRAM, 8 )
 
802
WRITE8_MEMBER(suna8_state::starfigh_spritebank_latch_w)
 
803
{
 
804
 
 
805
        m_spritebank_latch = (data >> 2) & 1;
 
806
        if (data & ~0x04)       logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space.device()),data);
 
807
}
 
808
 
 
809
WRITE8_MEMBER(suna8_state::starfigh_spritebank_w)
 
810
{
 
811
 
 
812
        m_spritebank = m_spritebank_latch;
 
813
}
 
814
 
 
815
static ADDRESS_MAP_START( starfigh_map, AS_PROGRAM, 8, suna8_state )
830
816
        AM_RANGE(0x0000, 0x7fff) AM_ROM                                                                         // ROM
831
817
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")                                                            // Banked ROM
832
818
        AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1")                                             // P1 (Inputs)
838
824
        AM_RANGE(0xc280, 0xc280) AM_WRITE(hardhea2_rombank_w                    )       // ROM Bank (?mirrored up to c2ff?)
839
825
        AM_RANGE(0xc300, 0xc300) AM_WRITE(hardhea2_flipscreen_w                 )       // Flip Screen
840
826
        AM_RANGE(0xc400, 0xc400) AM_WRITE(hardhea2_leds_w                               )       // Leds + Coin Counter
841
 
        AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w                                  )       // To Sound CPU
842
 
        AM_RANGE(0xc600, 0xc7ff) AM_READWRITE(suna8_banked_paletteram_r, paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE_GENERIC(paletteram   )       // Palette (Banked??)
 
827
        AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_byte_w                                     )       // To Sound CPU
 
828
        AM_RANGE(0xc600, 0xc7ff) AM_READWRITE(banked_paletteram_r, paletteram_RRRRGGGGBBBBxxxx_byte_be_w) AM_SHARE("paletteram" )       // Palette (Banked??)
843
829
        AM_RANGE(0xc800, 0xdfff) AM_RAM                                                                 // RAM
844
830
        AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w)       // Sprites (Banked)
845
831
ADDRESS_MAP_END
869
855
*/
870
856
 
871
857
/* This is a command-based protection. */
872
 
static WRITE8_HANDLER( sparkman_cmd_prot_w )
 
858
WRITE8_MEMBER(suna8_state::sparkman_cmd_prot_w)
873
859
{
874
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
875
860
 
876
861
        switch(data)
877
862
        {
878
 
                case 0xa6: state->m_nmi_enable = 1; break;
879
 
                case 0x00: state->m_nmi_enable = 0; break;
880
 
                case 0x18: state->m_trash_prot = 0; break;
881
 
                case 0xce: state->m_trash_prot = 0; break;
882
 
                case 0x81: state->m_trash_prot = 1; break;
883
 
                case 0x99: state->m_trash_prot = 1; break;
884
 
                case 0x54: state->m_spritebank = 1; break;
885
 
                default: logerror("CPU #0 - PC %04X: unknown protection command: %02X\n",cpu_get_pc(&space->device()),data);
 
863
                case 0xa6: m_nmi_enable = 1; break;
 
864
                case 0x00: m_nmi_enable = 0; break;
 
865
                case 0x18: m_trash_prot = 0; break;
 
866
                case 0xce: m_trash_prot = 0; break;
 
867
                case 0x81: m_trash_prot = 1; break;
 
868
                case 0x99: m_trash_prot = 1; break;
 
869
                case 0x54: m_spritebank = 1; break;
 
870
                default: logerror("CPU #0 - PC %04X: unknown protection command: %02X\n",cpu_get_pc(&space.device()),data);
886
871
        }
887
872
}
888
873
 
889
 
static WRITE8_HANDLER( suna8_wram_w )
 
874
WRITE8_MEMBER(suna8_state::suna8_wram_w)
890
875
{
891
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
892
876
 
893
 
        if (!state->m_trash_prot)
894
 
                state->m_wram[offset] = data;
 
877
        if (!m_trash_prot)
 
878
                m_wram[offset] = data;
895
879
}
896
880
 
897
881
/*
898
882
    7654 321-
899
883
    ---- ---0   Flip Screen
900
884
*/
901
 
static WRITE8_HANDLER( sparkman_flipscreen_w )
902
 
{
903
 
        flip_screen_set(space->machine(), data & 0x01);
904
 
        //if (data & ~0x01)     logerror("CPU #0 - PC %04X: unknown flipscreen bits: %02X\n",cpu_get_pc(&space->device()),data);
905
 
}
906
 
 
907
 
static WRITE8_HANDLER( sparkman_leds_w )
908
 
{
909
 
        set_led_status(space->machine(), 0, data & 0x01);
910
 
        set_led_status(space->machine(), 1, data & 0x02);
911
 
        //if (data & ~0x03) logerror("CPU#0  - PC %06X: unknown leds bits: %02X\n",cpu_get_pc(&space->device()),data);
912
 
}
913
 
 
914
 
static WRITE8_HANDLER( sparkman_coin_counter_w )
915
 
{
916
 
        coin_counter_w(space->machine(), 0, data & 0x01);
 
885
WRITE8_MEMBER(suna8_state::sparkman_flipscreen_w)
 
886
{
 
887
        flip_screen_set(data & 0x01);
 
888
        //if (data & ~0x01)     logerror("CPU #0 - PC %04X: unknown flipscreen bits: %02X\n",cpu_get_pc(&space.device()),data);
 
889
}
 
890
 
 
891
WRITE8_MEMBER(suna8_state::sparkman_leds_w)
 
892
{
 
893
        set_led_status(machine(), 0, data & 0x01);
 
894
        set_led_status(machine(), 1, data & 0x02);
 
895
        //if (data & ~0x03) logerror("CPU#0  - PC %06X: unknown leds bits: %02X\n",cpu_get_pc(&space.device()),data);
 
896
}
 
897
 
 
898
WRITE8_MEMBER(suna8_state::sparkman_coin_counter_w)
 
899
{
 
900
        coin_counter_w(machine(), 0, data & 0x01);
917
901
}
918
902
 
919
903
/*
921
905
    ---- --1-   Ram Bank
922
906
    ---- ---0   Ram Bank?
923
907
*/
924
 
static WRITE8_HANDLER( sparkman_spritebank_w )
 
908
WRITE8_MEMBER(suna8_state::sparkman_spritebank_w)
925
909
{
926
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
927
910
 
928
911
        if(data == 0xf7) //???
929
 
                state->m_spritebank = 0;
 
912
                m_spritebank = 0;
930
913
        else
931
 
                state->m_spritebank = (data) & 1;
932
 
        //if (data & ~0x02)     logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space->device()),data);
 
914
                m_spritebank = (data) & 1;
 
915
        //if (data & ~0x02)     logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",cpu_get_pc(&space.device()),data);
933
916
}
934
917
 
935
918
/*
936
919
    7654 ----
937
920
    ---- 3210   ROM Bank
938
921
*/
939
 
static WRITE8_HANDLER( sparkman_rombank_w )
 
922
WRITE8_MEMBER(suna8_state::sparkman_rombank_w)
940
923
{
941
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
942
924
        int bank = data & 0x0f;
943
925
 
944
 
        //if (data & ~0x0f)     logerror("CPU #0 - PC %04X: unknown rom bank bits: %02X\n",cpu_get_pc(&space->device()),data);
 
926
        //if (data & ~0x0f)     logerror("CPU #0 - PC %04X: unknown rom bank bits: %02X\n",cpu_get_pc(&space.device()),data);
945
927
 
946
 
        memory_set_bank(space->machine(), "bank1", bank);
947
 
        state->m_rombank = data;
 
928
        membank("bank1")->set_entry(bank);
 
929
        m_rombank = data;
948
930
}
949
931
 
950
 
static READ8_HANDLER( sparkman_c0a3_r )
 
932
READ8_MEMBER(suna8_state::sparkman_c0a3_r)
951
933
{
952
 
        return (space->machine().primary_screen->frame_number() & 1) ? 0x80 : 0;
 
934
        return (machine().primary_screen->frame_number() & 1) ? 0x80 : 0;
953
935
}
954
936
 
955
937
#if 0
956
 
static WRITE8_HANDLER( sparkman_en_trash_w )
 
938
WRITE8_MEMBER(suna8_state::sparkman_en_trash_w)
957
939
{
958
 
        suna8_state *state = space->machine().driver_data<suna8_state>();
959
940
 
960
 
        state->m_trash_prot = 1;
 
941
        m_trash_prot = 1;
961
942
}
962
943
#endif
963
944
 
964
 
static ADDRESS_MAP_START( sparkman_map, AS_PROGRAM, 8 )
 
945
static ADDRESS_MAP_START( sparkman_map, AS_PROGRAM, 8, suna8_state )
965
946
        AM_RANGE(0x0000, 0x7fff) AM_ROM                                                                 // ROM
966
947
        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")                                                    // Banked ROM
967
948
        AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1")                                             // P1 (Inputs)
976
957
        AM_RANGE(0xc380, 0xc3ff) AM_WRITE(sparkman_cmd_prot_w           )       // Protection
977
958
        AM_RANGE(0xc400, 0xc400) AM_WRITE(sparkman_leds_w                       )       // Leds
978
959
        AM_RANGE(0xc480, 0xc480) AM_WRITE(sparkman_coin_counter_w   )   // Coin Counter
979
 
        AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w                          )       // To Sound CPU
980
 
        AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE_GENERIC(paletteram      )       // Palette (Banked??)
981
 
        AM_RANGE(0xc800, 0xdfff) AM_RAM_WRITE(suna8_wram_w) AM_BASE_MEMBER(suna8_state, m_wram)                                                         // RAM
 
960
        AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_byte_w                             )       // To Sound CPU
 
961
        AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_byte_be_w) AM_SHARE("paletteram"      )       // Palette (Banked??)
 
962
        AM_RANGE(0xc800, 0xdfff) AM_RAM_WRITE(suna8_wram_w) AM_SHARE("wram")                                                            // RAM
982
963
        AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w)       // Sprites (Banked)
983
964
ADDRESS_MAP_END
984
965
 
995
976
                                Hard Head
996
977
***************************************************************************/
997
978
 
998
 
static ADDRESS_MAP_START( hardhead_sound_map, AS_PROGRAM, 8 )
 
979
static ADDRESS_MAP_START( hardhead_sound_map, AS_PROGRAM, 8, suna8_state )
999
980
        AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
1000
 
        AM_RANGE(0xa000, 0xa001) AM_DEVREADWRITE("ymsnd", ym3812_r, ym3812_w)
1001
 
        AM_RANGE(0xa002, 0xa003) AM_DEVWRITE("aysnd", ay8910_address_data_w             )
 
981
        AM_RANGE(0xa000, 0xa001) AM_DEVREADWRITE_LEGACY("ymsnd", ym3812_r, ym3812_w)
 
982
        AM_RANGE(0xa002, 0xa003) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w              )
1002
983
        AM_RANGE(0xc000, 0xc7ff) AM_RAM // RAM
1003
 
        AM_RANGE(0xc800, 0xc800) AM_DEVREAD("ymsnd", ym3812_status_port_r)      // ? unsure
1004
 
        AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_w                         )       //
1005
 
        AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_r                           )       // From Main CPU
 
984
        AM_RANGE(0xc800, 0xc800) AM_DEVREAD_LEGACY("ymsnd", ym3812_status_port_r)       // ? unsure
 
985
        AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_byte_w                            )       //
 
986
        AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_byte_r                              )       // From Main CPU
1006
987
ADDRESS_MAP_END
1007
988
 
1008
989
 
1009
 
static ADDRESS_MAP_START( hardhead_sound_io_map, AS_IO, 8 )
 
990
static ADDRESS_MAP_START( hardhead_sound_io_map, AS_IO, 8, suna8_state )
1010
991
        ADDRESS_MAP_GLOBAL_MASK(0xff)
1011
992
        AM_RANGE(0x01, 0x01) AM_READNOP // ? IRQ Ack
1012
993
ADDRESS_MAP_END
1016
997
                                Rough Ranger
1017
998
***************************************************************************/
1018
999
 
1019
 
static ADDRESS_MAP_START( rranger_sound_map, AS_PROGRAM, 8 )
 
1000
static ADDRESS_MAP_START( rranger_sound_map, AS_PROGRAM, 8, suna8_state )
1020
1001
        AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
1021
 
        AM_RANGE(0xa000, 0xa001) AM_DEVWRITE("ym1", ym2203_w                    )       // Samples + Music
1022
 
        AM_RANGE(0xa002, 0xa003) AM_DEVWRITE("ym2", ym2203_w                    )       // Music + FX
 
1002
        AM_RANGE(0xa000, 0xa001) AM_DEVWRITE_LEGACY("ym1", ym2203_w                     )       // Samples + Music
 
1003
        AM_RANGE(0xa002, 0xa003) AM_DEVWRITE_LEGACY("ym2", ym2203_w                     )       // Music + FX
1023
1004
        AM_RANGE(0xc000, 0xc7ff) AM_RAM // RAM
1024
 
        AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_w                         )       // To Sound CPU
1025
 
        AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_r                           )       // From Main CPU
 
1005
        AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_byte_w                            )       // To Sound CPU
 
1006
        AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_byte_r                              )       // From Main CPU
1026
1007
ADDRESS_MAP_END
1027
1008
 
1028
1009
 
1030
1011
                                Brick Zone
1031
1012
***************************************************************************/
1032
1013
 
1033
 
static ADDRESS_MAP_START( brickzn_sound_map, AS_PROGRAM, 8 )
 
1014
static ADDRESS_MAP_START( brickzn_sound_map, AS_PROGRAM, 8, suna8_state )
1034
1015
        AM_RANGE(0x0000, 0xbfff) AM_ROM // ROM
1035
 
        AM_RANGE(0xc000, 0xc001) AM_DEVWRITE("ymsnd", ym3812_w  )
1036
 
        AM_RANGE(0xc002, 0xc003) AM_DEVWRITE("aysnd", ay8910_address_data_w             )
 
1016
        AM_RANGE(0xc000, 0xc001) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w   )
 
1017
        AM_RANGE(0xc002, 0xc003) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w              )
1037
1018
        AM_RANGE(0xe000, 0xe7ff) AM_RAM // RAM
1038
 
        AM_RANGE(0xf000, 0xf000) AM_WRITE(soundlatch2_w                         )       // To PCM CPU
1039
 
        AM_RANGE(0xf800, 0xf800) AM_READ(soundlatch_r                           )       // From Main CPU
 
1019
        AM_RANGE(0xf000, 0xf000) AM_WRITE(soundlatch2_byte_w                            )       // To PCM CPU
 
1020
        AM_RANGE(0xf800, 0xf800) AM_READ(soundlatch_byte_r                              )       // From Main CPU
1040
1021
ADDRESS_MAP_END
1041
1022
 
1042
1023
 
1043
1024
/* PCM Z80 , 4 DACs (4 bits per sample), NO RAM !! */
1044
1025
 
1045
 
static ADDRESS_MAP_START( brickzn_pcm_map, AS_PROGRAM, 8 )
 
1026
static ADDRESS_MAP_START( brickzn_pcm_map, AS_PROGRAM, 8, suna8_state )
1046
1027
        AM_RANGE(0x0000, 0xffff) AM_ROM // ROM
1047
1028
ADDRESS_MAP_END
1048
1029
 
1049
1030
 
1050
 
static WRITE8_HANDLER( brickzn_pcm_w )
 
1031
WRITE8_MEMBER(suna8_state::brickzn_pcm_w)
1051
1032
{
1052
1033
        static const char *const dacs[] = { "dac1", "dac2", "dac3", "dac4" };
1053
 
        dac_signed_data_w( space->machine().device(dacs[offset & 3]), (data & 0xf) * 0x11 );
 
1034
        dac_signed_data_w( machine().device(dacs[offset & 3]), (data & 0xf) * 0x11 );
1054
1035
}
1055
1036
 
1056
1037
 
1057
 
static ADDRESS_MAP_START( brickzn_pcm_io_map, AS_IO, 8 )
 
1038
static ADDRESS_MAP_START( brickzn_pcm_io_map, AS_IO, 8, suna8_state )
1058
1039
        ADDRESS_MAP_GLOBAL_MASK(0xff)
1059
 
        AM_RANGE(0x00, 0x00) AM_READ(soundlatch2_r              )       // From Sound CPU
 
1040
        AM_RANGE(0x00, 0x00) AM_READ(soundlatch2_byte_r         )       // From Sound CPU
1060
1041
        AM_RANGE(0x00, 0x03) AM_WRITE(brickzn_pcm_w             )       // 4 x DAC
1061
1042
ADDRESS_MAP_END
1062
1043
 
1348
1329
        PORT_BIT(  0x08, IP_ACTIVE_LOW,  IPT_UNKNOWN )
1349
1330
        PORT_BIT(  0x10, IP_ACTIVE_LOW,  IPT_UNKNOWN )
1350
1331
        PORT_BIT(  0x20, IP_ACTIVE_LOW,  IPT_UNKNOWN )
1351
 
        PORT_BIT(  0x40, IP_ACTIVE_HIGH, IPT_VBLANK )
 
1332
        PORT_BIT(  0x40, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
1352
1333
        PORT_BIT(  0x80, IP_ACTIVE_LOW,  IPT_UNKNOWN )
1353
1334
 
1354
1335
INPUT_PORTS_END
1531
1512
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.30)
1532
1513
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.30)
1533
1514
 
1534
 
        MCFG_SOUND_ADD("samples", SAMPLES, 0)
1535
 
        MCFG_SOUND_CONFIG(suna8_samples_interface)
 
1515
        MCFG_SAMPLES_ADD("samples", suna8_samples_interface)
1536
1516
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
1537
1517
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
1538
1518
MACHINE_CONFIG_END
1595
1575
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.90)
1596
1576
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.90)
1597
1577
 
1598
 
        MCFG_SOUND_ADD("samples", SAMPLES, 0)
1599
 
        MCFG_SOUND_CONFIG(suna8_samples_interface)
 
1578
        MCFG_SAMPLES_ADD("samples", suna8_samples_interface)
1600
1579
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
1601
1580
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
1602
1581
MACHINE_CONFIG_END
1644
1623
        /* video hardware */
1645
1624
        MCFG_SCREEN_ADD("screen", RASTER)
1646
1625
        MCFG_SCREEN_REFRESH_RATE(60)
1647
 
        MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)   // we're using IPT_VBLANK
 
1626
        MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)   // we're using PORT_VBLANK
1648
1627
        MCFG_SCREEN_SIZE(256, 256)
1649
1628
        MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0+16, 256-16-1)
1650
1629
        MCFG_SCREEN_UPDATE_STATIC(suna8)
1699
1678
 
1700
1679
static MACHINE_RESET( hardhea2 )
1701
1680
{
 
1681
        suna8_state *state = machine.driver_data<suna8_state>();
1702
1682
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
1703
 
        hardhea2_rambank_0_w(space,0,0);
 
1683
        state->hardhea2_rambank_0_w(*space,0,0);
1704
1684
}
1705
1685
 
1706
1686
static MACHINE_CONFIG_DERIVED( hardhea2, brickzn )
1767
1747
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
1768
1748
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
1769
1749
 
1770
 
        MCFG_SOUND_ADD("samples", SAMPLES, 0)
1771
 
        MCFG_SOUND_CONFIG(suna8_samples_interface)
 
1750
        MCFG_SAMPLES_ADD("samples", suna8_samples_interface)
1772
1751
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
1773
1752
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
1774
1753
MACHINE_CONFIG_END
1815
1794
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.30)
1816
1795
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.30)
1817
1796
 
1818
 
        MCFG_SOUND_ADD("samples", SAMPLES, 0)
1819
 
        MCFG_SOUND_CONFIG(suna8_samples_interface)
 
1797
        MCFG_SAMPLES_ADD("samples", suna8_samples_interface)
1820
1798
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
1821
1799
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
1822
1800
MACHINE_CONFIG_END
2377
2355
 
2378
2356
static DRIVER_INIT( suna8 )
2379
2357
{
2380
 
        memory_configure_bank(machine, "bank1", 0, 16, machine.region("maincpu")->base() + 0x10000, 0x4000);
 
2358
        machine.root_device().membank("bank1")->configure_entries(0, 16, machine.root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
2381
2359
}
2382
2360
 
2383
2361
/* Working Games */