23
23
/* allocate second bank of videoram */
24
24
state->m_videoram = auto_alloc_array(machine, UINT8, 0x8000);
25
memory_set_bankptr(machine, "bank1", state->m_videoram);
25
state->membank("bank1")->set_base(state->m_videoram);
27
27
/* get pointers to our PROMs */
28
state->m_syncprom = machine.region("proms")->base() + 0x000;
29
state->m_wpprom = machine.region("proms")->base() + 0x200;
30
state->m_priprom = machine.region("proms")->base() + 0x300;
28
state->m_syncprom = machine.root_device().memregion("proms")->base() + 0x000;
29
state->m_wpprom = machine.root_device().memregion("proms")->base() + 0x200;
30
state->m_priprom = machine.root_device().memregion("proms")->base() + 0x300;
32
32
/* compute the color output resistor weights at startup */
33
33
compute_resistor_weights(0, 255, -1.0,
53
53
*************************************/
55
WRITE8_HANDLER( cloud9_video_control_w )
55
WRITE8_MEMBER(cloud9_state::cloud9_video_control_w)
57
cloud9_state *state = space->machine().driver_data<cloud9_state>();
59
58
/* only D7 matters */
60
state->m_video_control[offset] = (data >> 7) & 1;
59
m_video_control[offset] = (data >> 7) & 1;
83
81
bit0 = (~r >> 0) & 0x01;
84
82
bit1 = (~r >> 1) & 0x01;
85
83
bit2 = (~r >> 2) & 0x01;
86
r = combine_3_weights(state->m_rweights, bit0, bit1, bit2);
84
r = combine_3_weights(m_rweights, bit0, bit1, bit2);
88
86
/* green component (inverted) */
89
87
bit0 = (~g >> 0) & 0x01;
90
88
bit1 = (~g >> 1) & 0x01;
91
89
bit2 = (~g >> 2) & 0x01;
92
g = combine_3_weights(state->m_gweights, bit0, bit1, bit2);
90
g = combine_3_weights(m_gweights, bit0, bit1, bit2);
94
92
/* blue component (inverted) */
95
93
bit0 = (~b >> 0) & 0x01;
96
94
bit1 = (~b >> 1) & 0x01;
97
95
bit2 = (~b >> 2) & 0x01;
98
b = combine_3_weights(state->m_bweights, bit0, bit1, bit2);
96
b = combine_3_weights(m_bweights, bit0, bit1, bit2);
100
palette_set_color(space->machine(), offset & 0x3f, MAKE_RGB(r, g, b));
98
palette_set_color(machine(), offset & 0x3f, MAKE_RGB(r, g, b));
181
179
*************************************/
183
WRITE8_HANDLER( cloud9_videoram_w )
181
WRITE8_MEMBER(cloud9_state::cloud9_videoram_w)
185
183
/* direct writes to VRAM go through the write protect PROM as well */
186
cloud9_write_vram(space->machine(), offset, data, 0, 0);
184
cloud9_write_vram(machine(), offset, data, 0, 0);
195
193
*************************************/
197
READ8_HANDLER( cloud9_bitmode_r )
195
READ8_MEMBER(cloud9_state::cloud9_bitmode_r)
199
cloud9_state *state = space->machine().driver_data<cloud9_state>();
201
198
/* in bitmode, the address comes from the autoincrement latches */
202
UINT16 addr = (state->m_bitmode_addr[1] << 6) | (state->m_bitmode_addr[0] >> 2);
199
UINT16 addr = (m_bitmode_addr[1] << 6) | (m_bitmode_addr[0] >> 2);
204
201
/* the appropriate pixel is selected into the upper 4 bits */
205
UINT8 result = state->m_videoram[((~state->m_bitmode_addr[0] & 2) << 13) | addr] << ((state->m_bitmode_addr[0] & 1) * 4);
202
UINT8 result = m_videoram[((~m_bitmode_addr[0] & 2) << 13) | addr] << ((m_bitmode_addr[0] & 1) * 4);
207
204
/* autoincrement because /BITMD was selected */
208
bitmode_autoinc(space->machine());
205
bitmode_autoinc(machine());
210
207
/* the upper 4 bits of the data lines are not driven so make them all 1's */
211
208
return (result >> 4) | 0xf0;
215
WRITE8_HANDLER( cloud9_bitmode_w )
212
WRITE8_MEMBER(cloud9_state::cloud9_bitmode_w)
217
cloud9_state *state = space->machine().driver_data<cloud9_state>();
219
215
/* in bitmode, the address comes from the autoincrement latches */
220
UINT16 addr = (state->m_bitmode_addr[1] << 6) | (state->m_bitmode_addr[0] >> 2);
216
UINT16 addr = (m_bitmode_addr[1] << 6) | (m_bitmode_addr[0] >> 2);
222
218
/* the lower 4 bits of data are replicated to the upper 4 bits */
223
219
data = (data & 0x0f) | (data << 4);
225
221
/* write through the generic VRAM routine, passing the low 2 X bits as PIXB/PIXA */
226
cloud9_write_vram(space->machine(), addr, data, 1, state->m_bitmode_addr[0] & 3);
222
cloud9_write_vram(machine(), addr, data, 1, m_bitmode_addr[0] & 3);
228
224
/* autoincrement because /BITMD was selected */
229
bitmode_autoinc(space->machine());
225
bitmode_autoinc(machine());
233
WRITE8_HANDLER( cloud9_bitmode_addr_w )
229
WRITE8_MEMBER(cloud9_state::cloud9_bitmode_addr_w)
235
cloud9_state *state = space->machine().driver_data<cloud9_state>();
237
232
/* write through to video RAM and also to the addressing latches */
238
cloud9_write_vram(space->machine(), offset, data, 0, 0);
239
state->m_bitmode_addr[offset] = data;
233
cloud9_write_vram(machine(), offset, data, 0, 0);
234
m_bitmode_addr[offset] = data;