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Viewing changes to src/mame/video/qix.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/video/qix.c
46
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        qix_state *state = machine.driver_data<qix_state>();
47
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48
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        /* allocate memory for the full video RAM */
49
 
        state->m_videoram = auto_alloc_array(machine, UINT8, 256 * 256);
 
49
        state->m_videoram.allocate(256 * 256);
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        /* set up save states */
52
 
        state->save_pointer(NAME(state->m_videoram), 256 * 256);
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        state->save_item(NAME(state->m_flip));
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        state->save_item(NAME(state->m_palette_bank));
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        state->save_item(NAME(state->m_leds));
110
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 *
111
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 *************************************/
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static READ8_HANDLER( qix_videoram_r )
 
112
READ8_MEMBER(qix_state::qix_videoram_r)
114
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{
115
 
        qix_state *state = space->machine().driver_data<qix_state>();
116
114
 
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        /* add in the upper bit of the address latch */
118
 
        offset += (state->m_videoram_address[0] & 0x80) << 8;
119
 
        return state->m_videoram[offset];
 
116
        offset += (m_videoram_address[0] & 0x80) << 8;
 
117
        return m_videoram[offset];
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}
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static WRITE8_HANDLER( qix_videoram_w )
 
121
WRITE8_MEMBER(qix_state::qix_videoram_w)
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{
125
 
        qix_state *state = space->machine().driver_data<qix_state>();
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        /* update the screen in case the game is writing "behind" the beam -
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       Zookeeper likes to do this */
129
 
        space->machine().primary_screen->update_now();
 
126
        machine().primary_screen->update_now();
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        /* add in the upper bit of the address latch */
132
 
        offset += (state->m_videoram_address[0] & 0x80) << 8;
 
129
        offset += (m_videoram_address[0] & 0x80) << 8;
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        /* write the data */
135
 
        state->m_videoram[offset] = data;
 
132
        m_videoram[offset] = data;
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}
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static WRITE8_HANDLER( slither_videoram_w )
 
136
WRITE8_MEMBER(qix_state::slither_videoram_w)
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{
141
 
        qix_state *state = space->machine().driver_data<qix_state>();
142
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143
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        /* update the screen in case the game is writing "behind" the beam -
144
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       Zookeeper likes to do this */
145
 
        space->machine().primary_screen->update_now();
 
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        machine().primary_screen->update_now();
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        /* add in the upper bit of the address latch */
148
 
        offset += (state->m_videoram_address[0] & 0x80) << 8;
 
144
        offset += (m_videoram_address[0] & 0x80) << 8;
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        /* blend the data */
151
 
        state->m_videoram[offset] = (state->m_videoram[offset] & ~*state->m_videoram_mask) | (data & *state->m_videoram_mask);
 
147
        m_videoram[offset] = (m_videoram[offset] & ~*m_videoram_mask) | (data & *m_videoram_mask);
152
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}
153
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154
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168
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 *
169
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 *************************************/
170
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171
 
static READ8_HANDLER( qix_addresslatch_r )
 
167
READ8_MEMBER(qix_state::qix_addresslatch_r)
172
168
{
173
 
        qix_state *state = space->machine().driver_data<qix_state>();
174
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175
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        /* compute the value at the address latch */
176
 
        offset = (state->m_videoram_address[0] << 8) | state->m_videoram_address[1];
177
 
        return state->m_videoram[offset];
 
171
        offset = (m_videoram_address[0] << 8) | m_videoram_address[1];
 
172
        return m_videoram[offset];
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}
179
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181
 
static WRITE8_HANDLER( qix_addresslatch_w )
 
176
WRITE8_MEMBER(qix_state::qix_addresslatch_w)
182
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{
183
 
        qix_state *state = space->machine().driver_data<qix_state>();
184
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185
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        /* update the screen in case the game is writing "behind" the beam */
186
 
        space->machine().primary_screen->update_now();
 
180
        machine().primary_screen->update_now();
187
181
 
188
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        /* compute the value at the address latch */
189
 
        offset = (state->m_videoram_address[0] << 8) | state->m_videoram_address[1];
 
183
        offset = (m_videoram_address[0] << 8) | m_videoram_address[1];
190
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        /* write the data */
192
 
        state->m_videoram[offset] = data;
 
186
        m_videoram[offset] = data;
193
187
}
194
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195
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196
 
static WRITE8_HANDLER( slither_addresslatch_w )
 
190
WRITE8_MEMBER(qix_state::slither_addresslatch_w)
197
191
{
198
 
        qix_state *state = space->machine().driver_data<qix_state>();
199
192
 
200
193
        /* update the screen in case the game is writing "behind" the beam */
201
 
        space->machine().primary_screen->update_now();
 
194
        machine().primary_screen->update_now();
202
195
 
203
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        /* compute the value at the address latch */
204
 
        offset = (state->m_videoram_address[0] << 8) | state->m_videoram_address[1];
 
197
        offset = (m_videoram_address[0] << 8) | m_videoram_address[1];
205
198
 
206
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        /* blend the data */
207
 
        state->m_videoram[offset] = (state->m_videoram[offset] & ~*state->m_videoram_mask) | (data & *state->m_videoram_mask);
 
200
        m_videoram[offset] = (m_videoram[offset] & ~*m_videoram_mask) | (data & *m_videoram_mask);
208
201
}
209
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210
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 *************************************/
217
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218
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219
 
static WRITE8_HANDLER( qix_paletteram_w )
 
212
WRITE8_MEMBER(qix_state::qix_paletteram_w)
220
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{
221
 
        qix_state *state = space->machine().driver_data<qix_state>();
222
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223
 
        UINT8 old_data = state->m_paletteram[offset];
 
215
        UINT8 old_data = m_paletteram[offset];
224
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225
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        /* set the palette RAM value */
226
 
        state->m_paletteram[offset] = data;
 
218
        m_paletteram[offset] = data;
227
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228
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        /* trigger an update if a currently visible pen has changed */
229
 
        if (((offset >> 8) == state->m_palette_bank) &&
 
221
        if (((offset >> 8) == m_palette_bank) &&
230
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            (old_data != data))
231
 
                space->machine().primary_screen->update_now();
 
223
                machine().primary_screen->update_now();
232
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}
233
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234
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235
 
WRITE8_HANDLER( qix_palettebank_w )
 
227
WRITE8_MEMBER(qix_state::qix_palettebank_w)
236
228
{
237
 
        qix_state *state = space->machine().driver_data<qix_state>();
238
229
 
239
230
        /* set the bank value */
240
 
        if (state->m_palette_bank != (data & 3))
 
231
        if (m_palette_bank != (data & 3))
241
232
        {
242
 
                space->machine().primary_screen->update_now();
243
 
                state->m_palette_bank = data & 3;
 
233
                machine().primary_screen->update_now();
 
234
                m_palette_bank = data & 3;
244
235
        }
245
236
 
246
237
        /* LEDs are in the upper 6 bits */
247
 
        state->m_leds = ~data & 0xfc;
 
238
        m_leds = ~data & 0xfc;
248
239
}
249
240
 
250
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344
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 *
345
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 *************************************/
346
337
 
347
 
static ADDRESS_MAP_START( qix_video_map, AS_PROGRAM, 8 )
 
338
static ADDRESS_MAP_START( qix_video_map, AS_PROGRAM, 8, qix_state )
348
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        AM_RANGE(0x0000, 0x7fff) AM_READWRITE(qix_videoram_r, qix_videoram_w)
349
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        AM_RANGE(0x8000, 0x83ff) AM_RAM AM_SHARE("share1")
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        AM_RANGE(0x8400, 0x87ff) AM_RAM AM_SHARE("nvram")
351
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        AM_RANGE(0x8800, 0x8800) AM_MIRROR(0x03ff) AM_WRITE(qix_palettebank_w)
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        AM_RANGE(0x8c00, 0x8c00) AM_MIRROR(0x03fe) AM_READWRITE(qix_data_firq_r, qix_data_firq_w)
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        AM_RANGE(0x8c01, 0x8c01) AM_MIRROR(0x03fe) AM_READWRITE(qix_video_firq_ack_r, qix_video_firq_ack_w)
354
 
        AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(qix_paletteram_w) AM_BASE_MEMBER(qix_state, m_paletteram)
 
345
        AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(qix_paletteram_w) AM_SHARE("paletteram")
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        AM_RANGE(0x9400, 0x9400) AM_MIRROR(0x03fc) AM_READWRITE(qix_addresslatch_r, qix_addresslatch_w)
356
 
        AM_RANGE(0x9402, 0x9403) AM_MIRROR(0x03fc) AM_WRITEONLY AM_BASE_MEMBER(qix_state, m_videoram_address)
357
 
        AM_RANGE(0x9800, 0x9800) AM_MIRROR(0x03ff) AM_READONLY AM_BASE_MEMBER(qix_state, m_scanline_latch)
358
 
        AM_RANGE(0x9c00, 0x9c00) AM_MIRROR(0x03fe) AM_DEVWRITE_MODERN("vid_u18", mc6845_device, address_w)
359
 
        AM_RANGE(0x9c01, 0x9c01) AM_MIRROR(0x03fe) AM_DEVREADWRITE_MODERN("vid_u18", mc6845_device, register_r, register_w)
 
347
        AM_RANGE(0x9402, 0x9403) AM_MIRROR(0x03fc) AM_WRITEONLY AM_SHARE("videoram_addr")
 
348
        AM_RANGE(0x9800, 0x9800) AM_MIRROR(0x03ff) AM_READONLY AM_SHARE("scanline_latch")
 
349
        AM_RANGE(0x9c00, 0x9c00) AM_MIRROR(0x03fe) AM_DEVWRITE("vid_u18", mc6845_device, address_w)
 
350
        AM_RANGE(0x9c01, 0x9c01) AM_MIRROR(0x03fe) AM_DEVREADWRITE("vid_u18", mc6845_device, register_r, register_w)
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        AM_RANGE(0xa000, 0xffff) AM_ROM
361
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ADDRESS_MAP_END
362
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363
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364
 
static ADDRESS_MAP_START( zookeep_video_map, AS_PROGRAM, 8 )
 
355
static ADDRESS_MAP_START( zookeep_video_map, AS_PROGRAM, 8, qix_state )
365
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        AM_RANGE(0x0000, 0x7fff) AM_READWRITE(qix_videoram_r, qix_videoram_w)
366
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        AM_RANGE(0x8000, 0x83ff) AM_RAM AM_SHARE("share1")
367
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        AM_RANGE(0x8400, 0x87ff) AM_RAM AM_SHARE("nvram")
369
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        AM_RANGE(0x8801, 0x8801) AM_MIRROR(0x03fe) AM_WRITE(zookeep_bankswitch_w)
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        AM_RANGE(0x8c00, 0x8c00) AM_MIRROR(0x03fe) AM_READWRITE(qix_data_firq_r, qix_data_firq_w)
371
362
        AM_RANGE(0x8c01, 0x8c01) AM_MIRROR(0x03fe) AM_READWRITE(qix_video_firq_ack_r, qix_video_firq_ack_w)
372
 
        AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(qix_paletteram_w) AM_BASE_MEMBER(qix_state, m_paletteram)
 
363
        AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(qix_paletteram_w) AM_SHARE("paletteram")
373
364
        AM_RANGE(0x9400, 0x9400) AM_MIRROR(0x03fc) AM_READWRITE(qix_addresslatch_r, qix_addresslatch_w)
374
 
        AM_RANGE(0x9402, 0x9403) AM_MIRROR(0x03fc) AM_WRITEONLY AM_BASE_MEMBER(qix_state, m_videoram_address)
375
 
        AM_RANGE(0x9800, 0x9800) AM_MIRROR(0x03ff) AM_READONLY AM_BASE_MEMBER(qix_state, m_scanline_latch)
376
 
        AM_RANGE(0x9c00, 0x9c00) AM_MIRROR(0x03fe) AM_DEVWRITE_MODERN("vid_u18", mc6845_device, address_w)
377
 
        AM_RANGE(0x9c01, 0x9c01) AM_MIRROR(0x03fe) AM_DEVREADWRITE_MODERN("vid_u18", mc6845_device, register_r, register_w)
 
365
        AM_RANGE(0x9402, 0x9403) AM_MIRROR(0x03fc) AM_WRITEONLY AM_SHARE("videoram_addr")
 
366
        AM_RANGE(0x9800, 0x9800) AM_MIRROR(0x03ff) AM_READONLY AM_SHARE("scanline_latch")
 
367
        AM_RANGE(0x9c00, 0x9c00) AM_MIRROR(0x03fe) AM_DEVWRITE("vid_u18", mc6845_device, address_w)
 
368
        AM_RANGE(0x9c01, 0x9c01) AM_MIRROR(0x03fe) AM_DEVREADWRITE("vid_u18", mc6845_device, register_r, register_w)
378
369
        AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank1")
379
370
        AM_RANGE(0xc000, 0xffff) AM_ROM
380
371
ADDRESS_MAP_END
381
372
 
382
373
 
383
 
static ADDRESS_MAP_START( slither_video_map, AS_PROGRAM, 8 )
 
374
static ADDRESS_MAP_START( slither_video_map, AS_PROGRAM, 8, qix_state )
384
375
        AM_RANGE(0x0000, 0x7fff) AM_READWRITE(qix_videoram_r, slither_videoram_w)
385
376
        AM_RANGE(0x8000, 0x83ff) AM_RAM AM_SHARE("share1")
386
377
        AM_RANGE(0x8400, 0x87ff) AM_RAM AM_SHARE("nvram")
387
378
        AM_RANGE(0x8800, 0x8800) AM_MIRROR(0x03ff) AM_WRITE(qix_palettebank_w)
388
379
        AM_RANGE(0x8c00, 0x8c00) AM_MIRROR(0x03fe) AM_READWRITE(qix_data_firq_r, qix_data_firq_w)
389
380
        AM_RANGE(0x8c01, 0x8c01) AM_MIRROR(0x03fe) AM_READWRITE(qix_video_firq_ack_r, qix_video_firq_ack_w)
390
 
        AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(qix_paletteram_w) AM_BASE_MEMBER(qix_state, m_paletteram)
 
381
        AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(qix_paletteram_w) AM_SHARE("paletteram")
391
382
        AM_RANGE(0x9400, 0x9400) AM_MIRROR(0x03fc) AM_READWRITE(qix_addresslatch_r, slither_addresslatch_w)
392
 
        AM_RANGE(0x9401, 0x9401) AM_MIRROR(0x03fc) AM_WRITEONLY AM_BASE_MEMBER(qix_state, m_videoram_mask)
393
 
        AM_RANGE(0x9402, 0x9403) AM_MIRROR(0x03fc) AM_WRITEONLY AM_BASE_MEMBER(qix_state, m_videoram_address)
394
 
        AM_RANGE(0x9800, 0x9800) AM_MIRROR(0x03ff) AM_READONLY AM_BASE_MEMBER(qix_state, m_scanline_latch)
395
 
        AM_RANGE(0x9c00, 0x9c00) AM_MIRROR(0x03fe) AM_DEVWRITE_MODERN("vid_u18", mc6845_device, address_w)
396
 
        AM_RANGE(0x9c01, 0x9c01) AM_MIRROR(0x03fe) AM_DEVREADWRITE_MODERN("vid_u18", mc6845_device, register_r, register_w)
 
383
        AM_RANGE(0x9401, 0x9401) AM_MIRROR(0x03fc) AM_WRITEONLY AM_SHARE("videoram_mask")
 
384
        AM_RANGE(0x9402, 0x9403) AM_MIRROR(0x03fc) AM_WRITEONLY AM_SHARE("videoram_addr")
 
385
        AM_RANGE(0x9800, 0x9800) AM_MIRROR(0x03ff) AM_READONLY AM_SHARE("scanline_latch")
 
386
        AM_RANGE(0x9c00, 0x9c00) AM_MIRROR(0x03fe) AM_DEVWRITE("vid_u18", mc6845_device, address_w)
 
387
        AM_RANGE(0x9c01, 0x9c01) AM_MIRROR(0x03fe) AM_DEVREADWRITE("vid_u18", mc6845_device, register_r, register_w)
397
388
        AM_RANGE(0xa000, 0xffff) AM_ROM
398
389
ADDRESS_MAP_END
399
390