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Viewing changes to src/mame/drivers/fromanc2.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/fromanc2.c
37
37
}
38
38
 
39
39
 
40
 
static WRITE16_HANDLER( fromanc2_sndcmd_w )
41
 
{
42
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
43
 
 
44
 
        soundlatch_w(space, offset, (data >> 8) & 0xff);        // 1P (LEFT)
45
 
        soundlatch2_w(space, offset, data & 0xff);                      // 2P (RIGHT)
46
 
 
47
 
        device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
48
 
        state->m_sndcpu_nmi_flag = 0;
49
 
}
50
 
 
51
 
static WRITE16_HANDLER( fromanc2_portselect_w )
52
 
{
53
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
54
 
        state->m_portselect = data;
55
 
}
56
 
 
57
 
static READ16_HANDLER( fromanc2_keymatrix_r )
58
 
{
59
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
 
40
WRITE16_MEMBER(fromanc2_state::fromanc2_sndcmd_w)
 
41
{
 
42
 
 
43
        soundlatch_byte_w(space, offset, (data >> 8) & 0xff);   // 1P (LEFT)
 
44
        soundlatch2_byte_w(space, offset, data & 0xff);                 // 2P (RIGHT)
 
45
 
 
46
        device_set_input_line(m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
 
47
        m_sndcpu_nmi_flag = 0;
 
48
}
 
49
 
 
50
WRITE16_MEMBER(fromanc2_state::fromanc2_portselect_w)
 
51
{
 
52
        m_portselect = data;
 
53
}
 
54
 
 
55
READ16_MEMBER(fromanc2_state::fromanc2_keymatrix_r)
 
56
{
60
57
        UINT16 ret;
61
58
 
62
 
        switch (state->m_portselect)
 
59
        switch (m_portselect)
63
60
        {
64
 
        case 0x01:      ret = input_port_read(space->machine(), "KEY0"); break;
65
 
        case 0x02:      ret = input_port_read(space->machine(), "KEY1"); break;
66
 
        case 0x04:      ret = input_port_read(space->machine(), "KEY2"); break;
67
 
        case 0x08:      ret = input_port_read(space->machine(), "KEY3"); break;
 
61
        case 0x01:      ret = ioport("KEY0")->read(); break;
 
62
        case 0x02:      ret = ioport("KEY1")->read(); break;
 
63
        case 0x04:      ret = ioport("KEY2")->read(); break;
 
64
        case 0x08:      ret = ioport("KEY3")->read(); break;
68
65
        default:        ret = 0xffff;
69
 
                        logerror("PC:%08X unknown %02X\n", cpu_get_pc(&space->device()), state->m_portselect);
 
66
                        logerror("PC:%08X unknown %02X\n", cpu_get_pc(&space.device()), m_portselect);
70
67
                        break;
71
68
        }
72
69
 
73
70
        return ret;
74
71
}
75
72
 
76
 
static CUSTOM_INPUT( subcpu_int_r )
77
 
{
78
 
        fromanc2_state *state = field.machine().driver_data<fromanc2_state>();
79
 
        return state->m_subcpu_int_flag & 0x01;
80
 
}
81
 
 
82
 
static CUSTOM_INPUT( sndcpu_nmi_r )
83
 
{
84
 
        fromanc2_state *state = field.machine().driver_data<fromanc2_state>();
85
 
        return state->m_sndcpu_nmi_flag & 0x01;
86
 
}
87
 
 
88
 
static CUSTOM_INPUT( subcpu_nmi_r )
89
 
{
90
 
        fromanc2_state *state = field.machine().driver_data<fromanc2_state>();
91
 
        return state->m_subcpu_nmi_flag & 0x01;
92
 
}
93
 
 
94
 
static WRITE16_HANDLER( fromanc2_eeprom_w )
 
73
CUSTOM_INPUT_MEMBER(fromanc2_state::subcpu_int_r)
 
74
{
 
75
        return m_subcpu_int_flag & 0x01;
 
76
}
 
77
 
 
78
CUSTOM_INPUT_MEMBER(fromanc2_state::sndcpu_nmi_r)
 
79
{
 
80
        return m_sndcpu_nmi_flag & 0x01;
 
81
}
 
82
 
 
83
CUSTOM_INPUT_MEMBER(fromanc2_state::subcpu_nmi_r)
 
84
{
 
85
        return m_subcpu_nmi_flag & 0x01;
 
86
}
 
87
 
 
88
WRITE16_MEMBER(fromanc2_state::fromanc2_eeprom_w)
95
89
{
96
90
        if (ACCESSING_BITS_8_15)
97
 
                input_port_write(space->machine(), "EEPROMOUT", data, 0xffff);
 
91
                ioport("EEPROMOUT")->write(data, 0xffff);
98
92
}
99
93
 
100
 
static WRITE16_HANDLER( fromancr_eeprom_w )
 
94
WRITE16_MEMBER(fromanc2_state::fromancr_eeprom_w)
101
95
{
102
96
        if (ACCESSING_BITS_0_7)
103
97
        {
104
 
                fromancr_gfxbank_w(space->machine(), data & 0xfff8);
105
 
                input_port_write(space->machine(), "EEPROMOUT", data, 0xff);
 
98
                fromancr_gfxbank_w(machine(), data & 0xfff8);
 
99
                ioport("EEPROMOUT")->write(data, 0xff);
106
100
        }
107
101
}
108
102
 
109
 
static WRITE16_HANDLER( fromanc4_eeprom_w )
 
103
WRITE16_MEMBER(fromanc2_state::fromanc4_eeprom_w)
110
104
{
111
105
        if (ACCESSING_BITS_0_7)
112
 
                input_port_write(space->machine(), "EEPROMOUT", data, 0xff);
113
 
}
114
 
 
115
 
static WRITE16_HANDLER( fromanc2_subcpu_w )
116
 
{
117
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
118
 
        state->m_datalatch1 = data;
119
 
 
120
 
        device_set_input_line(state->m_subcpu, 0, HOLD_LINE);
121
 
        state->m_subcpu_int_flag = 0;
122
 
}
123
 
 
124
 
static READ16_HANDLER( fromanc2_subcpu_r )
125
 
{
126
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
127
 
        device_set_input_line(state->m_subcpu, INPUT_LINE_NMI, PULSE_LINE);
128
 
        state->m_subcpu_nmi_flag = 0;
129
 
 
130
 
        return (state->m_datalatch_2h << 8) | state->m_datalatch_2l;
131
 
}
132
 
 
133
 
static READ8_HANDLER( fromanc2_maincpu_r_l )
134
 
{
135
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
136
 
        return state->m_datalatch1 & 0x00ff;
137
 
}
138
 
 
139
 
static READ8_HANDLER( fromanc2_maincpu_r_h )
140
 
{
141
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
142
 
        state->m_subcpu_int_flag = 1;
143
 
 
144
 
        return (state->m_datalatch1 & 0xff00) >> 8;
145
 
}
146
 
 
147
 
static WRITE8_HANDLER( fromanc2_maincpu_w_l )
148
 
{
149
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
150
 
        state->m_datalatch_2l = data;
151
 
}
152
 
 
153
 
static WRITE8_HANDLER( fromanc2_maincpu_w_h )
154
 
{
155
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
156
 
        state->m_datalatch_2h = data;
157
 
}
158
 
 
159
 
static WRITE8_HANDLER( fromanc2_subcpu_nmi_clr )
160
 
{
161
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
162
 
        state->m_subcpu_nmi_flag = 1;
163
 
}
164
 
 
165
 
static READ8_HANDLER( fromanc2_sndcpu_nmi_clr )
166
 
{
167
 
        fromanc2_state *state = space->machine().driver_data<fromanc2_state>();
168
 
        state->m_sndcpu_nmi_flag = 1;
 
106
                ioport("EEPROMOUT")->write(data, 0xff);
 
107
}
 
108
 
 
109
WRITE16_MEMBER(fromanc2_state::fromanc2_subcpu_w)
 
110
{
 
111
        m_datalatch1 = data;
 
112
 
 
113
        device_set_input_line(m_subcpu, 0, HOLD_LINE);
 
114
        m_subcpu_int_flag = 0;
 
115
}
 
116
 
 
117
READ16_MEMBER(fromanc2_state::fromanc2_subcpu_r)
 
118
{
 
119
        device_set_input_line(m_subcpu, INPUT_LINE_NMI, PULSE_LINE);
 
120
        m_subcpu_nmi_flag = 0;
 
121
 
 
122
        return (m_datalatch_2h << 8) | m_datalatch_2l;
 
123
}
 
124
 
 
125
READ8_MEMBER(fromanc2_state::fromanc2_maincpu_r_l)
 
126
{
 
127
        return m_datalatch1 & 0x00ff;
 
128
}
 
129
 
 
130
READ8_MEMBER(fromanc2_state::fromanc2_maincpu_r_h)
 
131
{
 
132
        m_subcpu_int_flag = 1;
 
133
 
 
134
        return (m_datalatch1 & 0xff00) >> 8;
 
135
}
 
136
 
 
137
WRITE8_MEMBER(fromanc2_state::fromanc2_maincpu_w_l)
 
138
{
 
139
        m_datalatch_2l = data;
 
140
}
 
141
 
 
142
WRITE8_MEMBER(fromanc2_state::fromanc2_maincpu_w_h)
 
143
{
 
144
        m_datalatch_2h = data;
 
145
}
 
146
 
 
147
WRITE8_MEMBER(fromanc2_state::fromanc2_subcpu_nmi_clr)
 
148
{
 
149
        m_subcpu_nmi_flag = 1;
 
150
}
 
151
 
 
152
READ8_MEMBER(fromanc2_state::fromanc2_sndcpu_nmi_clr)
 
153
{
 
154
        m_sndcpu_nmi_flag = 1;
169
155
 
170
156
        return 0xff;
171
157
}
172
158
 
173
 
static WRITE8_HANDLER( fromanc2_subcpu_rombank_w )
 
159
WRITE8_MEMBER(fromanc2_state::fromanc2_subcpu_rombank_w)
174
160
{
175
161
        // Change ROM BANK
176
 
        memory_set_bank(space->machine(), "bank1", data & 0x03);
 
162
        membank("bank1")->set_entry(data & 0x03);
177
163
 
178
164
        // Change RAM BANK
179
 
        memory_set_bank(space->machine(), "bank2", (data & 0x0c) >> 2);
 
165
        membank("bank2")->set_entry((data & 0x0c) >> 2);
180
166
}
181
167
 
182
168
 
186
172
 *
187
173
 *************************************/
188
174
 
189
 
static ADDRESS_MAP_START( fromanc2_main_map, AS_PROGRAM, 16 )
 
175
static ADDRESS_MAP_START( fromanc2_main_map, AS_PROGRAM, 16, fromanc2_state )
190
176
        AM_RANGE(0x000000, 0x07ffff) AM_ROM                                                                     // MAIN ROM
191
177
 
192
178
        AM_RANGE(0x802000, 0x802fff) AM_READNOP                                                         // ???
219
205
        AM_RANGE(0xd80000, 0xd8ffff) AM_RAM                                                                     // WORK RAM
220
206
ADDRESS_MAP_END
221
207
 
222
 
static ADDRESS_MAP_START( fromancr_main_map, AS_PROGRAM, 16 )
 
208
static ADDRESS_MAP_START( fromancr_main_map, AS_PROGRAM, 16, fromanc2_state )
223
209
        AM_RANGE(0x000000, 0x07ffff) AM_ROM                                                                     // MAIN ROM
224
210
 
225
211
        AM_RANGE(0x800000, 0x803fff) AM_WRITE(fromancr_videoram_0_w)            // VRAM BG (1P/2P)
247
233
        AM_RANGE(0xd80000, 0xd8ffff) AM_RAM                                                                     // WORK RAM
248
234
ADDRESS_MAP_END
249
235
 
250
 
static ADDRESS_MAP_START( fromanc4_main_map, AS_PROGRAM, 16 )
 
236
static ADDRESS_MAP_START( fromanc4_main_map, AS_PROGRAM, 16, fromanc2_state )
251
237
        AM_RANGE(0x000000, 0x07ffff) AM_ROM                                                             // MAIN ROM
252
238
        AM_RANGE(0x400000, 0x7fffff) AM_ROM                                                             // DATA ROM
253
239
 
283
269
ADDRESS_MAP_END
284
270
 
285
271
 
286
 
static ADDRESS_MAP_START( fromanc2_sub_map, AS_PROGRAM, 8 )
 
272
static ADDRESS_MAP_START( fromanc2_sub_map, AS_PROGRAM, 8, fromanc2_state )
287
273
        AM_RANGE(0x0000, 0x3fff) AM_ROM                                                         // ROM
288
274
        AM_RANGE(0x4000, 0x7fff) AM_RAMBANK("bank1")                                            // ROM(BANK) (is this comment correct?  It was in the split address maps in a RAM configuration...
289
275
        AM_RANGE(0x8000, 0xbfff) AM_RAM                                                         // RAM(WORK)
290
276
        AM_RANGE(0xc000, 0xffff) AM_RAMBANK("bank2")                                            // RAM(BANK)
291
277
ADDRESS_MAP_END
292
278
 
293
 
static ADDRESS_MAP_START( fromanc2_sub_io_map, AS_IO, 8 )
 
279
static ADDRESS_MAP_START( fromanc2_sub_io_map, AS_IO, 8, fromanc2_state )
294
280
        ADDRESS_MAP_GLOBAL_MASK(0xff)
295
281
        AM_RANGE(0x00, 0x00) AM_WRITE(fromanc2_subcpu_rombank_w)
296
282
        AM_RANGE(0x02, 0x02) AM_READWRITE(fromanc2_maincpu_r_l, fromanc2_maincpu_w_l)   // to/from MAIN CPU
299
285
ADDRESS_MAP_END
300
286
 
301
287
 
302
 
static ADDRESS_MAP_START( fromanc2_sound_map, AS_PROGRAM, 8 )
 
288
static ADDRESS_MAP_START( fromanc2_sound_map, AS_PROGRAM, 8, fromanc2_state )
303
289
        AM_RANGE(0x0000, 0xdfff) AM_ROM
304
290
        AM_RANGE(0xe000, 0xffff) AM_RAM
305
291
ADDRESS_MAP_END
306
292
 
307
 
static ADDRESS_MAP_START( fromanc2_sound_io_map, AS_IO, 8 )
 
293
static ADDRESS_MAP_START( fromanc2_sound_io_map, AS_IO, 8, fromanc2_state )
308
294
        ADDRESS_MAP_GLOBAL_MASK(0xff)
309
 
        AM_RANGE(0x00, 0x00) AM_READ(soundlatch_r) AM_WRITENOP                  // snd cmd (1P) / ?
310
 
        AM_RANGE(0x04, 0x04) AM_READ(soundlatch2_r)                                                     // snd cmd (2P)
311
 
        AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ymsnd", ym2610_r, ym2610_w)
 
295
        AM_RANGE(0x00, 0x00) AM_READ(soundlatch_byte_r) AM_WRITENOP                     // snd cmd (1P) / ?
 
296
        AM_RANGE(0x04, 0x04) AM_READ(soundlatch2_byte_r)                                                        // snd cmd (2P)
 
297
        AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
312
298
        AM_RANGE(0x0c, 0x0c) AM_READ(fromanc2_sndcpu_nmi_clr)
313
299
ADDRESS_MAP_END
314
300
 
325
311
        PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
326
312
        PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN3 )
327
313
        PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN4 )
328
 
        PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(subcpu_int_r, NULL)         // SUBCPU INT FLAG
329
 
        PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(sndcpu_nmi_r, NULL)         // SNDCPU NMI FLAG
330
 
        PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(subcpu_nmi_r, NULL)         // SUBCPU NMI FLAG
 
314
        PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, fromanc2_state,subcpu_int_r, NULL)              // SUBCPU INT FLAG
 
315
        PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, fromanc2_state,sndcpu_nmi_r, NULL)              // SNDCPU NMI FLAG
 
316
        PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, fromanc2_state,subcpu_nmi_r, NULL)              // SUBCPU NMI FLAG
331
317
        PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_device, read_bit)
332
318
        PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME( "Service Mode (1P)" ) PORT_CODE(KEYCODE_F2)   // TEST (1P)
333
319
        PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME( "Service Mode (2P)" ) PORT_CODE(KEYCODE_F2)   // TEST (2P)
436
422
        PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN2 )
437
423
        PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN3 )
438
424
        PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_COIN4 )
439
 
        PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(sndcpu_nmi_r, NULL)         // SNDCPU NMI FLAG
 
425
        PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, fromanc2_state,sndcpu_nmi_r, NULL)              // SNDCPU NMI FLAG
440
426
        PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNUSED )
441
427
        PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_device, read_bit)
442
428
        PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNUSED )
538
524
{
539
525
        fromanc2_state *state = machine.driver_data<fromanc2_state>();
540
526
 
541
 
        memory_configure_bank(machine, "bank1", 0, 4, machine.region("sub")->base(), 0x4000);
542
 
        memory_configure_bank(machine, "bank2", 0, 1, machine.region("sub")->base() + 0x08000, 0x4000);
543
 
        memory_configure_bank(machine, "bank2", 1, 3, machine.region("sub")->base() + 0x14000, 0x4000);
 
527
        state->membank("bank1")->configure_entries(0, 4, state->memregion("sub")->base(), 0x4000);
 
528
        state->membank("bank2")->configure_entry(0, state->memregion("sub")->base() + 0x08000);
 
529
        state->membank("bank2")->configure_entries(1, 3, state->memregion("sub")->base() + 0x14000, 0x4000);
544
530
 
545
531
        MACHINE_START_CALL(fromanc4);
546
532