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Viewing changes to src/mame/drivers/ddragon.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/ddragon.c
150
150
        ddragon_state *state = machine.driver_data<ddragon_state>();
151
151
 
152
152
        /* configure banks */
153
 
        memory_configure_bank(machine, "bank1", 0, 8, machine.region("maincpu")->base() + 0x10000, 0x4000);
 
153
        state->membank("bank1")->configure_entries(0, 8, state->memregion("maincpu")->base() + 0x10000, 0x4000);
154
154
 
155
155
        state->m_maincpu = machine.device("maincpu");
156
156
        state->m_sub_cpu = machine.device("sub");
190
190
 *
191
191
 *************************************/
192
192
 
193
 
static WRITE8_HANDLER( ddragon_bankswitch_w )
 
193
WRITE8_MEMBER(ddragon_state::ddragon_bankswitch_w)
194
194
{
195
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
196
 
        state->m_scrollx_hi = (data & 0x01);
197
 
        state->m_scrolly_hi = ((data & 0x02) >> 1);
198
 
        flip_screen_set(space->machine(), ~data & 0x04);
 
195
        m_scrollx_hi = (data & 0x01);
 
196
        m_scrolly_hi = ((data & 0x02) >> 1);
 
197
        flip_screen_set(~data & 0x04);
199
198
 
200
199
        /* bit 3 unknown */
201
200
 
202
201
        if (data & 0x10)
203
 
                state->m_dd_sub_cpu_busy = 0;
204
 
        else if (state->m_dd_sub_cpu_busy == 0)
205
 
                device_set_input_line(state->m_sub_cpu, state->m_sprite_irq, (state->m_sprite_irq == INPUT_LINE_NMI) ? PULSE_LINE : HOLD_LINE);
 
202
                m_dd_sub_cpu_busy = 0;
 
203
        else if (m_dd_sub_cpu_busy == 0)
 
204
                device_set_input_line(m_sub_cpu, m_sprite_irq, (m_sprite_irq == INPUT_LINE_NMI) ? PULSE_LINE : HOLD_LINE);
206
205
 
207
 
        memory_set_bank(space->machine(), "bank1", (data & 0xe0) >> 5);
 
206
        membank("bank1")->set_entry((data & 0xe0) >> 5);
208
207
}
209
208
 
210
209
 
211
 
static WRITE8_HANDLER( toffy_bankswitch_w )
 
210
WRITE8_MEMBER(ddragon_state::toffy_bankswitch_w)
212
211
{
213
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
214
 
        state->m_scrollx_hi = (data & 0x01);
215
 
        state->m_scrolly_hi = ((data & 0x02) >> 1);
 
212
        m_scrollx_hi = (data & 0x01);
 
213
        m_scrolly_hi = ((data & 0x02) >> 1);
216
214
 
217
 
//  flip_screen_set(space->machine(), ~data & 0x04);
 
215
//  flip_screen_set(machine(), ~data & 0x04);
218
216
 
219
217
        /* bit 3 unknown */
220
218
 
221
219
        /* I don't know ... */
222
 
        memory_set_bank(space->machine(), "bank1", (data & 0x20) >> 5);
 
220
        membank("bank1")->set_entry((data & 0x20) >> 5);
223
221
}
224
222
 
225
223
 
226
 
static READ8_HANDLER( darktowr_mcu_bank_r )
 
224
READ8_MEMBER(ddragon_state::darktowr_mcu_bank_r)
227
225
{
228
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
229
 
        // logerror("BankRead %05x %08x\n",cpu_get_pc(&space->device()),offset);
 
226
        // logerror("BankRead %05x %08x\n",cpu_get_pc(&space.device()),offset);
230
227
 
231
228
        /* Horrible hack - the alternate TStrike set is mismatched against the MCU,
232
229
   so just hack around the protection here.  (The hacks are 'right' as I have
233
230
   the original source code & notes to this version of TStrike to examine).
234
231
   */
235
 
        if (!strcmp(space->machine().system().name, "tstrike"))
 
232
        if (!strcmp(machine().system().name, "tstrike"))
236
233
        {
237
234
                /* Static protection checks at boot-up */
238
 
                if (cpu_get_pc(&space->device()) == 0x9ace)
 
235
                if (cpu_get_pc(&space.device()) == 0x9ace)
239
236
                        return 0;
240
 
                if (cpu_get_pc(&space->device()) == 0x9ae4)
 
237
                if (cpu_get_pc(&space.device()) == 0x9ae4)
241
238
                        return 0x63;
242
239
 
243
240
                /* Just return whatever the code is expecting */
244
 
                return state->m_rambase[0xbe1];
 
241
                return m_rambase[0xbe1];
245
242
        }
246
243
 
247
244
        if (offset == 0x1401 || offset == 1)
248
 
                return state->m_darktowr_mcu_ports[0];
 
245
                return m_darktowr_mcu_ports[0];
249
246
 
250
247
        logerror("Unmapped mcu bank read %04x\n",offset);
251
248
        return 0xff;
252
249
}
253
250
 
254
251
 
255
 
static WRITE8_HANDLER( darktowr_mcu_bank_w )
 
252
WRITE8_MEMBER(ddragon_state::darktowr_mcu_bank_w)
256
253
{
257
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
258
 
        logerror("BankWrite %05x %08x %08x\n", cpu_get_pc(&space->device()), offset, data);
 
254
        logerror("BankWrite %05x %08x %08x\n", cpu_get_pc(&space.device()), offset, data);
259
255
 
260
256
        if (offset == 0x1400 || offset == 0)
261
257
        {
262
 
                state->m_darktowr_mcu_ports[1] = BITSWAP8(data,0,1,2,3,4,5,6,7);
 
258
                m_darktowr_mcu_ports[1] = BITSWAP8(data,0,1,2,3,4,5,6,7);
263
259
                logerror("MCU PORT 1 -> %04x (from %04x)\n", BITSWAP8(data,0,1,2,3,4,5,6,7), data);
264
260
        }
265
261
}
266
262
 
267
263
 
268
 
static WRITE8_HANDLER( darktowr_bankswitch_w )
 
264
WRITE8_MEMBER(ddragon_state::darktowr_bankswitch_w)
269
265
{
270
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
271
 
        int oldbank = memory_get_bank(space->machine(), "bank1");
 
266
        int oldbank = membank("bank1")->entry();
272
267
        int newbank = (data & 0xe0) >> 5;
273
268
 
274
 
        state->m_scrollx_hi = (data & 0x01);
275
 
        state->m_scrolly_hi = ((data & 0x02) >> 1);
 
269
        m_scrollx_hi = (data & 0x01);
 
270
        m_scrolly_hi = ((data & 0x02) >> 1);
276
271
 
277
 
//  flip_screen_set(space->machine(), ~data & 0x04);
 
272
//  flip_screen_set(machine(), ~data & 0x04);
278
273
 
279
274
        /* bit 3 unknown */
280
275
 
281
276
        if (data & 0x10)
282
 
                state->m_dd_sub_cpu_busy = 0;
283
 
        else if (state->m_dd_sub_cpu_busy == 0)
284
 
                device_set_input_line(state->m_sub_cpu, state->m_sprite_irq, (state->m_sprite_irq == INPUT_LINE_NMI) ? PULSE_LINE : HOLD_LINE);
 
277
                m_dd_sub_cpu_busy = 0;
 
278
        else if (m_dd_sub_cpu_busy == 0)
 
279
                device_set_input_line(m_sub_cpu, m_sprite_irq, (m_sprite_irq == INPUT_LINE_NMI) ? PULSE_LINE : HOLD_LINE);
285
280
 
286
 
        memory_set_bank(space->machine(), "bank1", newbank);
 
281
        membank("bank1")->set_entry(newbank);
287
282
        if (newbank == 4 && oldbank != 4)
288
 
                space->install_legacy_readwrite_handler(0x4000, 0x7fff, FUNC(darktowr_mcu_bank_r), FUNC(darktowr_mcu_bank_w));
 
283
                space.install_readwrite_handler(0x4000, 0x7fff, read8_delegate(FUNC(ddragon_state::darktowr_mcu_bank_r),this), write8_delegate(FUNC(ddragon_state::darktowr_mcu_bank_w),this));
289
284
        else if (newbank != 4 && oldbank == 4)
290
 
                space->install_readwrite_bank(0x4000, 0x7fff, "bank1");
 
285
                space.install_readwrite_bank(0x4000, 0x7fff, "bank1");
291
286
}
292
287
 
293
288
 
298
293
 *
299
294
 *************************************/
300
295
 
301
 
static WRITE8_HANDLER( ddragon_interrupt_w )
 
296
WRITE8_MEMBER(ddragon_state::ddragon_interrupt_w)
302
297
{
303
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
304
298
        switch (offset)
305
299
        {
306
300
                case 0: /* 380b - NMI ack */
307
 
                        device_set_input_line(state->m_maincpu, INPUT_LINE_NMI, CLEAR_LINE);
 
301
                        device_set_input_line(m_maincpu, INPUT_LINE_NMI, CLEAR_LINE);
308
302
                        break;
309
303
 
310
304
                case 1: /* 380c - FIRQ ack */
311
 
                        device_set_input_line(state->m_maincpu, M6809_FIRQ_LINE, CLEAR_LINE);
 
305
                        device_set_input_line(m_maincpu, M6809_FIRQ_LINE, CLEAR_LINE);
312
306
                        break;
313
307
 
314
308
                case 2: /* 380d - IRQ ack */
315
 
                        device_set_input_line(state->m_maincpu, M6809_IRQ_LINE, CLEAR_LINE);
 
309
                        device_set_input_line(m_maincpu, M6809_IRQ_LINE, CLEAR_LINE);
316
310
                        break;
317
311
 
318
312
                case 3: /* 380e - SND irq */
319
 
                        soundlatch_w(space, 0, data);
320
 
                        device_set_input_line(state->m_snd_cpu, state->m_sound_irq, (state->m_sound_irq == INPUT_LINE_NMI) ? PULSE_LINE : HOLD_LINE);
 
313
                        soundlatch_byte_w(space, 0, data);
 
314
                        device_set_input_line(m_snd_cpu, m_sound_irq, (m_sound_irq == INPUT_LINE_NMI) ? PULSE_LINE : HOLD_LINE);
321
315
                        break;
322
316
 
323
317
                case 4: /* 380f - ? */
327
321
}
328
322
 
329
323
 
330
 
static WRITE8_HANDLER( ddragon2_sub_irq_ack_w )
 
324
WRITE8_MEMBER(ddragon_state::ddragon2_sub_irq_ack_w)
331
325
{
332
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
333
 
        device_set_input_line(state->m_sub_cpu, state->m_sprite_irq, CLEAR_LINE );
 
326
        device_set_input_line(m_sub_cpu, m_sprite_irq, CLEAR_LINE );
334
327
}
335
328
 
336
329
 
337
 
static WRITE8_HANDLER( ddragon2_sub_irq_w )
 
330
WRITE8_MEMBER(ddragon_state::ddragon2_sub_irq_w)
338
331
{
339
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
340
 
        device_set_input_line(state->m_maincpu, M6809_IRQ_LINE, ASSERT_LINE);
 
332
        device_set_input_line(m_maincpu, M6809_IRQ_LINE, ASSERT_LINE);
341
333
}
342
334
 
343
335
 
355
347
 *
356
348
 *************************************/
357
349
 
358
 
static CUSTOM_INPUT( sub_cpu_busy )
359
 
{
360
 
        ddragon_state *state = field.machine().driver_data<ddragon_state>();
361
 
        return state->m_dd_sub_cpu_busy;
362
 
}
363
 
 
364
 
 
365
 
static WRITE8_HANDLER( darktowr_mcu_w )
366
 
{
367
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
368
 
        logerror("McuWrite %05x %08x %08x\n",cpu_get_pc(&space->device()), offset, data);
369
 
        state->m_darktowr_mcu_ports[offset] = data;
370
 
}
371
 
 
372
 
 
373
 
static READ8_HANDLER( ddragon_hd63701_internal_registers_r )
374
 
{
375
 
        logerror("%04x: read %d\n", cpu_get_pc(&space->device()), offset);
 
350
CUSTOM_INPUT_MEMBER(ddragon_state::sub_cpu_busy)
 
351
{
 
352
        return m_dd_sub_cpu_busy;
 
353
}
 
354
 
 
355
 
 
356
WRITE8_MEMBER(ddragon_state::darktowr_mcu_w)
 
357
{
 
358
        logerror("McuWrite %05x %08x %08x\n",cpu_get_pc(&space.device()), offset, data);
 
359
        m_darktowr_mcu_ports[offset] = data;
 
360
}
 
361
 
 
362
 
 
363
READ8_MEMBER(ddragon_state::ddragon_hd63701_internal_registers_r)
 
364
{
 
365
        logerror("%04x: read %d\n", cpu_get_pc(&space.device()), offset);
376
366
        return 0;
377
367
}
378
368
 
379
369
 
380
 
static WRITE8_HANDLER( ddragon_hd63701_internal_registers_w )
 
370
WRITE8_MEMBER(ddragon_state::ddragon_hd63701_internal_registers_w)
381
371
{
382
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
383
372
 
384
373
        /* I don't know why port 0x17 is used..  Doesn't seem to be a standard MCU port */
385
374
        if (offset == 0x17)
389
378
        it's quite obvious from the Double Dragon 2 code, below). */
390
379
                if (data & 3)
391
380
                {
392
 
                        device_set_input_line(state->m_maincpu, M6809_IRQ_LINE, ASSERT_LINE);
393
 
                        device_set_input_line(state->m_sub_cpu, state->m_sprite_irq, CLEAR_LINE);
 
381
                        device_set_input_line(m_maincpu, M6809_IRQ_LINE, ASSERT_LINE);
 
382
                        device_set_input_line(m_sub_cpu, m_sprite_irq, CLEAR_LINE);
394
383
                }
395
384
        }
396
385
}
403
392
 *
404
393
 *************************************/
405
394
 
406
 
static READ8_HANDLER( ddragon_spriteram_r )
 
395
READ8_MEMBER(ddragon_state::ddragon_spriteram_r)
407
396
{
408
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
409
397
 
410
398
        /* Double Dragon crash fix - see notes above */
411
 
        if (offset == 0x49 && cpu_get_pc(&space->device()) == 0x6261 && state->m_spriteram[offset] == 0x1f)
 
399
        if (offset == 0x49 && cpu_get_pc(&space.device()) == 0x6261 && m_spriteram[offset] == 0x1f)
412
400
                return 0x1;
413
401
 
414
 
        return state->m_spriteram[offset];
 
402
        return m_spriteram[offset];
415
403
}
416
404
 
417
405
 
418
 
static WRITE8_HANDLER( ddragon_spriteram_w )
 
406
WRITE8_MEMBER(ddragon_state::ddragon_spriteram_w)
419
407
{
420
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
421
 
 
422
 
        if (&space->device() == state->m_sub_cpu && offset == 0)
423
 
                state->m_dd_sub_cpu_busy = 1;
424
 
 
425
 
        state->m_spriteram[offset] = data;
 
408
 
 
409
        if (&space.device() == m_sub_cpu && offset == 0)
 
410
                m_dd_sub_cpu_busy = 1;
 
411
 
 
412
        m_spriteram[offset] = data;
426
413
}
427
414
 
428
415
 
433
420
 *
434
421
 *************************************/
435
422
 
436
 
static WRITE8_HANDLER( dd_adpcm_w )
 
423
WRITE8_MEMBER(ddragon_state::dd_adpcm_w)
437
424
{
438
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
439
 
        device_t *adpcm = (offset & 1) ? state->m_adpcm_2 : state->m_adpcm_1;
440
 
        int chip = (adpcm == state->m_adpcm_1) ? 0 : 1;
 
425
        device_t *adpcm = (offset & 1) ? m_adpcm_2 : m_adpcm_1;
 
426
        int chip = (adpcm == m_adpcm_1) ? 0 : 1;
441
427
 
442
428
        switch (offset / 2)
443
429
        {
444
430
                case 3:
445
 
                        state->m_adpcm_idle[chip] = 1;
 
431
                        m_adpcm_idle[chip] = 1;
446
432
                        msm5205_reset_w(adpcm, 1);
447
433
                        break;
448
434
 
449
435
                case 2:
450
 
                        state->m_adpcm_pos[chip] = (data & 0x7f) * 0x200;
 
436
                        m_adpcm_pos[chip] = (data & 0x7f) * 0x200;
451
437
                        break;
452
438
 
453
439
                case 1:
454
 
                        state->m_adpcm_end[chip] = (data & 0x7f) * 0x200;
 
440
                        m_adpcm_end[chip] = (data & 0x7f) * 0x200;
455
441
                        break;
456
442
 
457
443
                case 0:
458
 
                        state->m_adpcm_idle[chip] = 0;
 
444
                        m_adpcm_idle[chip] = 0;
459
445
                        msm5205_reset_w(adpcm, 0);
460
446
                        break;
461
447
        }
479
465
        }
480
466
        else
481
467
        {
482
 
                UINT8 *ROM = device->machine().region("adpcm")->base() + 0x10000 * chip;
 
468
                UINT8 *ROM = device->machine().root_device().memregion("adpcm")->base() + 0x10000 * chip;
483
469
 
484
470
                state->m_adpcm_data[chip] = ROM[state->m_adpcm_pos[chip]++];
485
471
                msm5205_data_w(device, state->m_adpcm_data[chip] >> 4);
487
473
}
488
474
 
489
475
 
490
 
static READ8_HANDLER( dd_adpcm_status_r )
 
476
READ8_MEMBER(ddragon_state::dd_adpcm_status_r)
491
477
{
492
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
493
 
        return state->m_adpcm_idle[0] + (state->m_adpcm_idle[1] << 1);
 
478
        return m_adpcm_idle[0] + (m_adpcm_idle[1] << 1);
494
479
}
495
480
 
496
481
 
501
486
 *
502
487
 *************************************/
503
488
 
504
 
static ADDRESS_MAP_START( ddragon_map, AS_PROGRAM, 8 )
505
 
        AM_RANGE(0x0000, 0x0fff) AM_RAM AM_BASE_MEMBER(ddragon_state, m_rambase)
506
 
        AM_RANGE(0x1000, 0x11ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_split1_w) AM_BASE_GENERIC(paletteram)
507
 
        AM_RANGE(0x1200, 0x13ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_split2_w) AM_BASE_GENERIC(paletteram2)
 
489
static ADDRESS_MAP_START( ddragon_map, AS_PROGRAM, 8, ddragon_state )
 
490
        AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("rambase")
 
491
        AM_RANGE(0x1000, 0x11ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_byte_split_lo_w) AM_SHARE("paletteram")
 
492
        AM_RANGE(0x1200, 0x13ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_byte_split_hi_w) AM_SHARE("paletteram2")
508
493
        AM_RANGE(0x1400, 0x17ff) AM_RAM
509
 
        AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE(ddragon_fgvideoram_w) AM_BASE_MEMBER(ddragon_state, m_fgvideoram)
510
 
        AM_RANGE(0x2000, 0x2fff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w) AM_BASE_MEMBER(ddragon_state, m_spriteram)
511
 
        AM_RANGE(0x3000, 0x37ff) AM_RAM_WRITE(ddragon_bgvideoram_w) AM_BASE_MEMBER(ddragon_state, m_bgvideoram)
 
494
        AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE(ddragon_fgvideoram_w) AM_SHARE("fgvideoram")
 
495
        AM_RANGE(0x2000, 0x2fff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w) AM_SHARE("spriteram")
 
496
        AM_RANGE(0x3000, 0x37ff) AM_RAM_WRITE(ddragon_bgvideoram_w) AM_SHARE("bgvideoram")
512
497
        AM_RANGE(0x3800, 0x3800) AM_READ_PORT("P1")
513
498
        AM_RANGE(0x3801, 0x3801) AM_READ_PORT("P2")
514
499
        AM_RANGE(0x3802, 0x3802) AM_READ_PORT("EXTRA")
515
500
        AM_RANGE(0x3803, 0x3803) AM_READ_PORT("DSW0")
516
501
        AM_RANGE(0x3804, 0x3804) AM_READ_PORT("DSW1")
517
502
        AM_RANGE(0x3808, 0x3808) AM_WRITE(ddragon_bankswitch_w)
518
 
        AM_RANGE(0x3809, 0x3809) AM_WRITEONLY AM_BASE_MEMBER(ddragon_state, m_scrollx_lo)
519
 
        AM_RANGE(0x380a, 0x380a) AM_WRITEONLY AM_BASE_MEMBER(ddragon_state, m_scrolly_lo)
 
503
        AM_RANGE(0x3809, 0x3809) AM_WRITEONLY AM_SHARE("scrollx_lo")
 
504
        AM_RANGE(0x380a, 0x380a) AM_WRITEONLY AM_SHARE("scrolly_lo")
520
505
        AM_RANGE(0x380b, 0x380f) AM_WRITE(ddragon_interrupt_w)
521
506
        AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
522
507
        AM_RANGE(0x8000, 0xffff) AM_ROM
523
508
ADDRESS_MAP_END
524
509
 
525
510
 
526
 
static ADDRESS_MAP_START( dd2_map, AS_PROGRAM, 8 )
 
511
static ADDRESS_MAP_START( dd2_map, AS_PROGRAM, 8, ddragon_state )
527
512
        AM_RANGE(0x0000, 0x17ff) AM_RAM
528
 
        AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE(ddragon_fgvideoram_w) AM_BASE_MEMBER(ddragon_state, m_fgvideoram)
529
 
        AM_RANGE(0x2000, 0x2fff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w) AM_BASE_MEMBER(ddragon_state, m_spriteram)
530
 
        AM_RANGE(0x3000, 0x37ff) AM_RAM_WRITE(ddragon_bgvideoram_w) AM_BASE_MEMBER(ddragon_state, m_bgvideoram)
 
513
        AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE(ddragon_fgvideoram_w) AM_SHARE("fgvideoram")
 
514
        AM_RANGE(0x2000, 0x2fff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w) AM_SHARE("spriteram")
 
515
        AM_RANGE(0x3000, 0x37ff) AM_RAM_WRITE(ddragon_bgvideoram_w) AM_SHARE("bgvideoram")
531
516
        AM_RANGE(0x3800, 0x3800) AM_READ_PORT("P1")
532
517
        AM_RANGE(0x3801, 0x3801) AM_READ_PORT("P2")
533
518
        AM_RANGE(0x3802, 0x3802) AM_READ_PORT("EXTRA")
534
519
        AM_RANGE(0x3803, 0x3803) AM_READ_PORT("DSW0")
535
520
        AM_RANGE(0x3804, 0x3804) AM_READ_PORT("DSW1")
536
521
        AM_RANGE(0x3808, 0x3808) AM_WRITE(ddragon_bankswitch_w)
537
 
        AM_RANGE(0x3809, 0x3809) AM_WRITEONLY AM_BASE_MEMBER(ddragon_state, m_scrollx_lo)
538
 
        AM_RANGE(0x380a, 0x380a) AM_WRITEONLY AM_BASE_MEMBER(ddragon_state, m_scrolly_lo)
 
522
        AM_RANGE(0x3809, 0x3809) AM_WRITEONLY AM_SHARE("scrollx_lo")
 
523
        AM_RANGE(0x380a, 0x380a) AM_WRITEONLY AM_SHARE("scrolly_lo")
539
524
        AM_RANGE(0x380b, 0x380f) AM_WRITE(ddragon_interrupt_w)
540
 
        AM_RANGE(0x3c00, 0x3dff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_split1_w) AM_BASE_GENERIC(paletteram)
541
 
        AM_RANGE(0x3e00, 0x3fff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_split2_w) AM_BASE_GENERIC(paletteram2)
 
525
        AM_RANGE(0x3c00, 0x3dff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_byte_split_lo_w) AM_SHARE("paletteram")
 
526
        AM_RANGE(0x3e00, 0x3fff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_byte_split_hi_w) AM_SHARE("paletteram2")
542
527
        AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
543
528
        AM_RANGE(0x8000, 0xffff) AM_ROM
544
529
ADDRESS_MAP_END
551
536
 *
552
537
 *************************************/
553
538
 
554
 
static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8 )
 
539
static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, ddragon_state )
555
540
        AM_RANGE(0x0000, 0x001f) AM_READWRITE(ddragon_hd63701_internal_registers_r, ddragon_hd63701_internal_registers_w)
556
541
        AM_RANGE(0x001f, 0x0fff) AM_RAM
557
542
        AM_RANGE(0x8000, 0x8fff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w)
559
544
ADDRESS_MAP_END
560
545
 
561
546
 
562
 
static ADDRESS_MAP_START( ddragonba_sub_map, AS_PROGRAM, 8 )
 
547
static ADDRESS_MAP_START( ddragonba_sub_map, AS_PROGRAM, 8, ddragon_state )
563
548
        AM_RANGE(0x0000, 0x0fff) AM_RAM
564
549
        AM_RANGE(0x8000, 0x8fff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w)
565
550
        AM_RANGE(0xc000, 0xffff) AM_ROM
566
551
ADDRESS_MAP_END
567
552
 
568
553
 
569
 
static ADDRESS_MAP_START( dd2_sub_map, AS_PROGRAM, 8 )
 
554
static ADDRESS_MAP_START( dd2_sub_map, AS_PROGRAM, 8, ddragon_state )
570
555
        AM_RANGE(0x0000, 0xbfff) AM_ROM
571
556
        AM_RANGE(0xc000, 0xc3ff) AM_READWRITE(ddragon_spriteram_r, ddragon_spriteram_w)
572
557
        AM_RANGE(0xd000, 0xd000) AM_WRITE(ddragon2_sub_irq_ack_w)
574
559
ADDRESS_MAP_END
575
560
 
576
561
/* might not be 100% accurate, check bits written */
577
 
static WRITE8_HANDLER( ddragonba_port_w )
 
562
WRITE8_MEMBER(ddragon_state::ddragonba_port_w)
578
563
{
579
 
        ddragon_state *state = space->machine().driver_data<ddragon_state>();
580
 
        device_set_input_line(state->m_maincpu, M6809_IRQ_LINE, ASSERT_LINE);
581
 
        device_set_input_line(state->m_sub_cpu, state->m_sprite_irq, CLEAR_LINE );
 
564
        device_set_input_line(m_maincpu, M6809_IRQ_LINE, ASSERT_LINE);
 
565
        device_set_input_line(m_sub_cpu, m_sprite_irq, CLEAR_LINE );
582
566
}
583
567
 
584
 
static ADDRESS_MAP_START( ddragonba_sub_portmap, AS_IO, 8 )
 
568
static ADDRESS_MAP_START( ddragonba_sub_portmap, AS_IO, 8, ddragon_state )
585
569
        AM_RANGE(0x0000, 0xffff) AM_WRITE(ddragonba_port_w)
586
570
ADDRESS_MAP_END
587
571
 
593
577
 *
594
578
 *************************************/
595
579
 
596
 
static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8 )
 
580
static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, ddragon_state )
597
581
        AM_RANGE(0x0000, 0x0fff) AM_RAM
598
 
        AM_RANGE(0x1000, 0x1000) AM_READ(soundlatch_r)
 
582
        AM_RANGE(0x1000, 0x1000) AM_READ(soundlatch_byte_r)
599
583
        AM_RANGE(0x1800, 0x1800) AM_READ(dd_adpcm_status_r)
600
 
        AM_RANGE(0x2800, 0x2801) AM_DEVREADWRITE("fmsnd", ym2151_r, ym2151_w)
 
584
        AM_RANGE(0x2800, 0x2801) AM_DEVREADWRITE_LEGACY("fmsnd", ym2151_r, ym2151_w)
601
585
        AM_RANGE(0x3800, 0x3807) AM_WRITE(dd_adpcm_w)
602
586
        AM_RANGE(0x8000, 0xffff) AM_ROM
603
587
ADDRESS_MAP_END
604
588
 
605
589
 
606
 
static ADDRESS_MAP_START( dd2_sound_map, AS_PROGRAM, 8 )
 
590
static ADDRESS_MAP_START( dd2_sound_map, AS_PROGRAM, 8, ddragon_state )
607
591
        AM_RANGE(0x0000, 0x7fff) AM_ROM
608
592
        AM_RANGE(0x8000, 0x87ff) AM_RAM
609
 
        AM_RANGE(0x8800, 0x8801) AM_DEVREADWRITE("fmsnd", ym2151_r, ym2151_w)
610
 
        AM_RANGE(0x9800, 0x9800) AM_DEVREADWRITE_MODERN("oki", okim6295_device, read, write)
611
 
        AM_RANGE(0xA000, 0xA000) AM_READ(soundlatch_r)
 
593
        AM_RANGE(0x8800, 0x8801) AM_DEVREADWRITE_LEGACY("fmsnd", ym2151_r, ym2151_w)
 
594
        AM_RANGE(0x9800, 0x9800) AM_DEVREADWRITE("oki", okim6295_device, read, write)
 
595
        AM_RANGE(0xA000, 0xA000) AM_READ(soundlatch_byte_r)
612
596
ADDRESS_MAP_END
613
597
 
614
598
 
619
603
 *
620
604
 *************************************/
621
605
 
622
 
static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8 )
 
606
static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, ddragon_state )
623
607
        ADDRESS_MAP_GLOBAL_MASK(0x7ff)
624
 
        AM_RANGE(0x0000, 0x0007) AM_RAM_WRITE(darktowr_mcu_w) AM_BASE_MEMBER(ddragon_state, m_darktowr_mcu_ports)
 
608
        AM_RANGE(0x0000, 0x0007) AM_RAM_WRITE(darktowr_mcu_w) AM_SHARE("darktowr_mcu")
625
609
        AM_RANGE(0x0008, 0x007f) AM_RAM
626
610
        AM_RANGE(0x0080, 0x07ff) AM_ROM
627
611
ADDRESS_MAP_END
706
690
        PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
707
691
        PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 )
708
692
        PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
709
 
        PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
710
 
        PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(sub_cpu_busy, NULL)
 
693
        PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
 
694
        PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, ddragon_state,sub_cpu_busy, NULL)
711
695
        PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
712
696
        PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
713
697
        PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
962
946
 
963
947
static const ym2151_interface ym2151_config =
964
948
{
965
 
        irq_handler
 
949
        DEVCB_LINE(irq_handler)
966
950
};
967
951
 
968
952
static const msm5205_interface msm5205_config =
1489
1473
 
1490
1474
ROM_START( ddragonb2 )
1491
1475
        ROM_REGION( 0x30000, "maincpu", 0 )     /* 64k for code + bankswitched memory */
1492
 
        ROM_LOAD( "4.bin",        0x08000, 0x08000, CRC(668dfa19) SHA1(9b2ff1b66eeba0989e4ed850b7df1f5719ba5572) )
1493
 
        ROM_LOAD( "5.bin",        0x10000, 0x08000, CRC(5779705e) SHA1(4b8f22225d10f5414253ce0383bbebd6f720f3af) ) /* banked at 0x4000-0x8000 */
1494
 
        ROM_LOAD( "6.bin",        0x18000, 0x08000, CRC(3bdea613) SHA1(d9038c80646a6ce3ea61da222873237b0383680e) ) /* banked at 0x4000-0x8000 */
1495
 
        ROM_LOAD( "7.bin",        0x20000, 0x08000, CRC(728f87b9) SHA1(d7442be24d41bb9fc021587ef44ae5b830e4503d) ) /* banked at 0x4000-0x8000 */
 
1476
        ROM_LOAD( "b2_4.bin",     0x08000, 0x08000, CRC(668dfa19) SHA1(9b2ff1b66eeba0989e4ed850b7df1f5719ba5572) )
 
1477
        ROM_LOAD( "b2_5.bin",     0x10000, 0x08000, CRC(5779705e) SHA1(4b8f22225d10f5414253ce0383bbebd6f720f3af) ) /* banked at 0x4000-0x8000 */
 
1478
        ROM_LOAD( "b2_6.bin",     0x18000, 0x08000, CRC(3bdea613) SHA1(d9038c80646a6ce3ea61da222873237b0383680e) ) /* banked at 0x4000-0x8000 */
 
1479
        ROM_LOAD( "b2_7.bin",     0x20000, 0x08000, CRC(728f87b9) SHA1(d7442be24d41bb9fc021587ef44ae5b830e4503d) ) /* banked at 0x4000-0x8000 */
1496
1480
 
1497
1481
        ROM_REGION( 0x10000, "sub", 0 ) /* sprite cpu */
1498
1482
        ROM_LOAD( "63701.bin",    0xc000, 0x4000, CRC(f5232d03) SHA1(e2a194e38633592fd6587690b3cb2669d93985c7) )
1501
1485
        ROM_LOAD( "b2_3.bin",     0x08000, 0x08000, CRC(9efa95bb) SHA1(da997d9cc7b9e7b2c70a4b6d30db693086a6f7d8) )
1502
1486
 
1503
1487
        ROM_REGION( 0x08000, "gfx1", 0 )
1504
 
        ROM_LOAD( "8.bin",        0x00000, 0x08000, CRC(7a8b8db4) SHA1(8368182234f9d4d763d4714fd7567a9e31b7ebeb) )      /* chars */
 
1488
        ROM_LOAD( "b2_8.bin",     0x00000, 0x08000, CRC(7a8b8db4) SHA1(8368182234f9d4d763d4714fd7567a9e31b7ebeb) )      /* chars */
1505
1489
 
1506
1490
        ROM_REGION( 0x80000, "gfx2", 0 )
1507
1491
        ROM_LOAD( "11.bin",       0x00000, 0x10000, CRC(574face3) SHA1(481fe574cb79d0159a65ff7486cbc945d50538c5) )      /* sprites */
1537
1521
 */
1538
1522
ROM_START( ddragon6809 )
1539
1523
        ROM_REGION( 0x30000, "maincpu", 0 )     /* 64k for code + bankswitched memory */
1540
 
        ROM_LOAD( "16.bin",   0x08000, 0x08000, CRC(f4c72690) SHA1(c70d032355acf3f7f6586b6e57a94f80e099bf1a) )
1541
 
        ROM_LOAD( "17.bin",   0x10000, 0x08000, CRC(6489d637) SHA1(fd17fd870e9386a3e3bdd56c8d731c73d8c70b88) ) /* banked at 0x4000-0x8000 */
1542
 
        ROM_LOAD( "18.bin",   0x18000, 0x08000, CRC(154d50c4) SHA1(4ffdd29406b6c6b552344f820f83715b1c7727d1) ) /* banked at 0x4000-0x8000 */
1543
 
        ROM_LOAD( "19.bin",   0x20000, 0x08000, CRC(090e2baf) SHA1(29b775c59c7a4d30a33e3d10e736cd1a83baf3bb) ) /* banked at 0x4000-0x8000 */
 
1524
        ROM_LOAD( "6809_16.bin",   0x08000, 0x08000, CRC(f4c72690) SHA1(c70d032355acf3f7f6586b6e57a94f80e099bf1a) )
 
1525
        ROM_LOAD( "6809_17.bin",   0x10000, 0x08000, CRC(6489d637) SHA1(fd17fd870e9386a3e3bdd56c8d731c73d8c70b88) ) /* banked at 0x4000-0x8000 */
 
1526
        ROM_LOAD( "6809_18.bin",   0x18000, 0x08000, CRC(154d50c4) SHA1(4ffdd29406b6c6b552344f820f83715b1c7727d1) ) /* banked at 0x4000-0x8000 */
 
1527
        ROM_LOAD( "6809_19.bin",   0x20000, 0x08000, CRC(090e2baf) SHA1(29b775c59c7a4d30a33e3d10e736cd1a83baf3bb) ) /* banked at 0x4000-0x8000 */
1544
1528
 
1545
1529
        ROM_REGION( 0x10000, "sub", 0 ) /* sprite cpu */
1546
 
        ROM_LOAD( "20.bin",    0x8000, 0x8000, CRC(67e3b4f1) SHA1(4945d76b0694299f2f4739ebfba98da6d96fe4cb) )
 
1530
        ROM_LOAD( "6809_20.bin",   0x8000, 0x8000, CRC(67e3b4f1) SHA1(4945d76b0694299f2f4739ebfba98da6d96fe4cb) )
1547
1531
 
1548
1532
        ROM_REGION( 0x10000, "soundcpu", 0 ) /* audio cpu */
1549
1533
        ROM_LOAD( "21.bin",      0x08000, 0x08000, CRC(4437fc51) SHA1(fffcf2bec50d0b79861904b4abc607206b7794e6) )
1552
1536
        ROM_REGION( 0x08000, "gfx1", ROMREGION_ERASEFF )
1553
1537
 
1554
1538
        ROM_REGION( 0x08000, "chars", 0 )
1555
 
        ROM_LOAD( "13.bin",        0x00000, 0x08000, CRC(b5a54537) SHA1(a6157cde4f9738565008d11a4a6d8576ae3abfef) )     /* chars */
 
1539
        ROM_LOAD( "6809_13.bin",   0x00000, 0x08000, CRC(b5a54537) SHA1(a6157cde4f9738565008d11a4a6d8576ae3abfef) )     /* chars */
1556
1540
 
1557
1541
        ROM_REGION( 0x80000, "gfx2", 0 )
1558
1542
        ROM_LOAD( "22.bin",        0x00000, 0x08000, CRC(fe08ef61) SHA1(50404936934dc61f3553add4d4b918529b3b5ef3) )
1564
1548
        ROM_LOAD( "28.bin",        0x30000, 0x08000, CRC(51b8a217) SHA1(60c067cd7272f856e29cdb64312535236656891a) )
1565
1549
        ROM_LOAD( "29.bin",        0x38000, 0x08000, CRC(e4ec2394) SHA1(43376ce2a07c1fc3053f7ac9b750e944d289105b) )
1566
1550
        ROM_LOAD( "6809_1.bin",    0x40000, 0x08000, CRC(2485a71d) SHA1(3e987a2f3e9a59da5fdc7bb779a43736ca67aac7) )
1567
 
        ROM_LOAD( "2.bin",         0x48000, 0x08000, CRC(6940120d) SHA1(bbe94f095ef983f54658c936f916ba6a72a84ead) )
1568
 
        ROM_LOAD( "3.bin",         0x50000, 0x08000, CRC(c67aac12) SHA1(aab535507e3889bf1bdc2f4fe4828a70a350ba63) )
1569
 
        ROM_LOAD( "4.bin",         0x58000, 0x08000, CRC(941dcd08) SHA1(266dee264f28affe8c3f57fe569929817ae16508) )
1570
 
        ROM_LOAD( "5.bin",         0x60000, 0x08000, CRC(42d36bc3) SHA1(080cbc3ffda8ab26dc65a8e9eaf948c509d064b3) )
1571
 
        ROM_LOAD( "6.bin",         0x68000, 0x08000, CRC(d5d19a8d) SHA1(c4b044dd12d6468c0ad114644f01813d4fe9a673) )
1572
 
        ROM_LOAD( "7.bin",         0x70000, 0x08000, CRC(d4e350cd) SHA1(78ed2baa8c52b766f998091e7ce9e1a2941352e7) )
1573
 
        ROM_LOAD( "8.bin",         0x78000, 0x08000, CRC(204fdb7d) SHA1(f75b1bc6f65e7a33927cd451267fcd7e2aa44f7e) )
 
1551
        ROM_LOAD( "6809_2.bin",    0x48000, 0x08000, CRC(6940120d) SHA1(bbe94f095ef983f54658c936f916ba6a72a84ead) )
 
1552
        ROM_LOAD( "6809_3.bin",    0x50000, 0x08000, CRC(c67aac12) SHA1(aab535507e3889bf1bdc2f4fe4828a70a350ba63) )
 
1553
        ROM_LOAD( "6809_4.bin",    0x58000, 0x08000, CRC(941dcd08) SHA1(266dee264f28affe8c3f57fe569929817ae16508) )
 
1554
        ROM_LOAD( "6809_5.bin",    0x60000, 0x08000, CRC(42d36bc3) SHA1(080cbc3ffda8ab26dc65a8e9eaf948c509d064b3) )
 
1555
        ROM_LOAD( "6809_6.bin",    0x68000, 0x08000, CRC(d5d19a8d) SHA1(c4b044dd12d6468c0ad114644f01813d4fe9a673) )
 
1556
        ROM_LOAD( "6809_7.bin",    0x70000, 0x08000, CRC(d4e350cd) SHA1(78ed2baa8c52b766f998091e7ce9e1a2941352e7) )
 
1557
        ROM_LOAD( "6809_8.bin",    0x78000, 0x08000, CRC(204fdb7d) SHA1(f75b1bc6f65e7a33927cd451267fcd7e2aa44f7e) )
1574
1558
 
1575
1559
        ROM_REGION( 0x40000, "gfx3", 0 )
1576
 
        ROM_LOAD( "9.bin",         0x00000, 0x10000, CRC(736eff0f) SHA1(ae2ec2d5c8ab1db579a08256d874426dc5d889c6) )
 
1560
        ROM_LOAD( "6809_9.bin",    0x00000, 0x10000, CRC(736eff0f) SHA1(ae2ec2d5c8ab1db579a08256d874426dc5d889c6) )
1577
1561
        ROM_LOAD( "6809_10.bin",   0x10000, 0x10000, CRC(a670d088) SHA1(27e7b49645753dd039f104c3e0a7e6513a98710d) )
1578
 
        ROM_LOAD( "11.bin",        0x20000, 0x10000, CRC(4171b70d) SHA1(dc300c9bca6481417e97ad03c973e47389f261c1) )
1579
 
        ROM_LOAD( "12.bin",        0x30000, 0x10000, CRC(5f6a6d6f) SHA1(7d546a226cda81c28e7ccfb4c5daebc65072198d) )
 
1562
        ROM_LOAD( "6809_11.bin",   0x20000, 0x10000, CRC(4171b70d) SHA1(dc300c9bca6481417e97ad03c973e47389f261c1) )
 
1563
        ROM_LOAD( "6809_12.bin",   0x30000, 0x10000, CRC(5f6a6d6f) SHA1(7d546a226cda81c28e7ccfb4c5daebc65072198d) )
1580
1564
 
1581
1565
        ROM_REGION( 0x20000, "adpcm", 0 ) /* adpcm samples  */
1582
 
        ROM_LOAD( "14.bin",        0x00000, 0x08000, CRC(678f8657) SHA1(2652fdc6719d2c889ca87802f6e2cefae59fc2eb) )
1583
 
        ROM_LOAD( "15.bin",        0x10000, 0x08000, CRC(10f21dea) SHA1(739cf649f91490384297a81a2cc9855acb58a1c0) )
 
1566
        ROM_LOAD( "6809_14.bin",   0x00000, 0x08000, CRC(678f8657) SHA1(2652fdc6719d2c889ca87802f6e2cefae59fc2eb) )
 
1567
        ROM_LOAD( "6809_15.bin",   0x10000, 0x08000, CRC(10f21dea) SHA1(739cf649f91490384297a81a2cc9855acb58a1c0) )
1584
1568
ROM_END
1585
1569
 
1586
1570
/*
2023
2007
        state->m_sound_irq = M6809_IRQ_LINE;
2024
2008
        state->m_ym_irq = M6809_FIRQ_LINE;
2025
2009
        state->m_technos_video_hw = 0;
2026
 
        machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x3808, 0x3808, FUNC(darktowr_bankswitch_w));
 
2010
        machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x3808, 0x3808, write8_delegate(FUNC(ddragon_state::darktowr_bankswitch_w),state));
2027
2011
}
2028
2012
 
2029
2013
 
2036
2020
        state->m_sound_irq = M6809_IRQ_LINE;
2037
2021
        state->m_ym_irq = M6809_FIRQ_LINE;
2038
2022
        state->m_technos_video_hw = 0;
2039
 
        machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x3808, 0x3808, FUNC(toffy_bankswitch_w));
 
2023
        machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x3808, 0x3808, write8_delegate(FUNC(ddragon_state::toffy_bankswitch_w),state));
2040
2024
 
2041
2025
        /* the program rom has a simple bitswap encryption */
2042
 
        rom = machine.region("maincpu")->base();
2043
 
        length = machine.region("maincpu")->bytes();
 
2026
        rom = state->memregion("maincpu")->base();
 
2027
        length = state->memregion("maincpu")->bytes();
2044
2028
        for (i = 0; i < length; i++)
2045
2029
                rom[i] = BITSWAP8(rom[i], 6,7,5,4,3,2,1,0);
2046
2030
 
2047
2031
        /* and the fg gfx ... */
2048
 
        rom = machine.region("gfx1")->base();
2049
 
        length = machine.region("gfx1")->bytes();
 
2032
        rom = state->memregion("gfx1")->base();
 
2033
        length = state->memregion("gfx1")->bytes();
2050
2034
        for (i = 0; i < length; i++)
2051
2035
                rom[i] = BITSWAP8(rom[i], 7,6,5,3,4,2,1,0);
2052
2036
 
2053
2037
        /* and the sprites gfx */
2054
 
        rom = machine.region("gfx2")->base();
2055
 
        length = machine.region("gfx2")->bytes();
 
2038
        rom = state->memregion("gfx2")->base();
 
2039
        length = state->memregion("gfx2")->bytes();
2056
2040
        for (i = 0; i < length; i++)
2057
2041
                rom[i] = BITSWAP8(rom[i], 7,6,5,4,3,2,0,1);
2058
2042
 
2059
2043
        /* and the bg gfx */
2060
 
        rom = machine.region("gfx3")->base();
2061
 
        length = machine.region("gfx3")->bytes();
 
2044
        rom = state->memregion("gfx3")->base();
 
2045
        length = state->memregion("gfx3")->bytes();
2062
2046
        for (i = 0; i < length / 2; i++)
2063
2047
        {
2064
2048
                rom[i + 0*length/2] = BITSWAP8(rom[i + 0*length/2], 7,6,1,4,3,2,5,0);
2074
2058
        int i;
2075
2059
        UINT8 *dst,*src;
2076
2060
 
2077
 
        src = machine.region("chars")->base();
2078
 
        dst = machine.region("gfx1")->base();
 
2061
        src = state->memregion("chars")->base();
 
2062
        dst = state->memregion("gfx1")->base();
2079
2063
 
2080
2064
        for (i = 0; i < 0x8000; i++)
2081
2065
        {