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Viewing changes to src/mame/drivers/magic10.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/magic10.c
89
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{
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public:
91
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        magic10_state(const machine_config &mconfig, device_type type, const char *tag)
92
 
                : driver_device(mconfig, type, tag) { }
 
92
                : driver_device(mconfig, type, tag) ,
 
93
                m_layer0_videoram(*this, "layer0_videoram"),
 
94
                m_layer1_videoram(*this, "layer1_videoram"),
 
95
                m_layer2_videoram(*this, "layer2_videoram"),
 
96
                m_vregs(*this, "vregs"){ }
93
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        tilemap_t *m_layer0_tilemap;
95
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        tilemap_t *m_layer1_tilemap;
96
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        tilemap_t *m_layer2_tilemap;
97
 
        UINT16 *m_layer0_videoram;
98
 
        UINT16 *m_layer1_videoram;
99
 
        UINT16 *m_layer2_videoram;
 
101
        required_shared_ptr<UINT16> m_layer0_videoram;
 
102
        required_shared_ptr<UINT16> m_layer1_videoram;
 
103
        required_shared_ptr<UINT16> m_layer2_videoram;
100
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        int m_layer2_offset[2];
101
 
        UINT16 *m_vregs;
 
105
        required_shared_ptr<UINT16> m_vregs;
102
106
        UINT16 m_magic102_ret;
 
107
        DECLARE_WRITE16_MEMBER(layer0_videoram_w);
 
108
        DECLARE_WRITE16_MEMBER(layer1_videoram_w);
 
109
        DECLARE_WRITE16_MEMBER(layer2_videoram_w);
 
110
        DECLARE_WRITE16_MEMBER(paletteram_w);
 
111
        DECLARE_READ16_MEMBER(magic102_r);
 
112
        DECLARE_READ16_MEMBER(hotslot_copro_r);
 
113
        DECLARE_WRITE16_MEMBER(hotslot_copro_w);
 
114
        DECLARE_WRITE16_MEMBER(magic10_out_w);
103
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};
104
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105
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107
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*      Video Hardware      *
108
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***************************/
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110
 
static WRITE16_HANDLER( layer0_videoram_w )
111
 
{
112
 
        magic10_state *state = space->machine().driver_data<magic10_state>();
113
 
        COMBINE_DATA(&state->m_layer0_videoram[offset]);
114
 
        state->m_layer0_tilemap->mark_tile_dirty(offset >> 1);
115
 
}
116
 
 
117
 
static WRITE16_HANDLER( layer1_videoram_w )
118
 
{
119
 
        magic10_state *state = space->machine().driver_data<magic10_state>();
120
 
        COMBINE_DATA(&state->m_layer1_videoram[offset]);
121
 
        state->m_layer1_tilemap->mark_tile_dirty(offset >> 1);
122
 
}
123
 
 
124
 
static WRITE16_HANDLER( layer2_videoram_w )
125
 
{
126
 
        magic10_state *state = space->machine().driver_data<magic10_state>();
127
 
        COMBINE_DATA(&state->m_layer2_videoram[offset]);
128
 
        state->m_layer2_tilemap->mark_tile_dirty(offset >> 1);
129
 
}
130
 
 
131
 
static WRITE16_HANDLER( paletteram_w )
132
 
{
133
 
        data = COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
134
 
        palette_set_color_rgb( space->machine(), offset, pal4bit(data >> 4), pal4bit(data >> 0), pal4bit(data >> 8));
 
122
WRITE16_MEMBER(magic10_state::layer0_videoram_w)
 
123
{
 
124
        COMBINE_DATA(&m_layer0_videoram[offset]);
 
125
        m_layer0_tilemap->mark_tile_dirty(offset >> 1);
 
126
}
 
127
 
 
128
WRITE16_MEMBER(magic10_state::layer1_videoram_w)
 
129
{
 
130
        COMBINE_DATA(&m_layer1_videoram[offset]);
 
131
        m_layer1_tilemap->mark_tile_dirty(offset >> 1);
 
132
}
 
133
 
 
134
WRITE16_MEMBER(magic10_state::layer2_videoram_w)
 
135
{
 
136
        COMBINE_DATA(&m_layer2_videoram[offset]);
 
137
        m_layer2_tilemap->mark_tile_dirty(offset >> 1);
 
138
}
 
139
 
 
140
WRITE16_MEMBER(magic10_state::paletteram_w)
 
141
{
 
142
        data = COMBINE_DATA(&m_generic_paletteram_16[offset]);
 
143
        palette_set_color_rgb( machine(), offset, pal4bit(data >> 4), pal4bit(data >> 0), pal4bit(data >> 8));
135
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}
136
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*       R/W Handlers       *
210
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***************************/
211
220
 
212
 
static READ16_HANDLER( magic102_r )
 
221
READ16_MEMBER(magic10_state::magic102_r)
213
222
{
214
 
        magic10_state *state = space->machine().driver_data<magic10_state>();
215
 
        state->m_magic102_ret ^= 0x20;
216
 
        return state->m_magic102_ret;
 
223
        m_magic102_ret ^= 0x20;
 
224
        return m_magic102_ret;
217
225
}
218
226
 
219
 
static READ16_HANDLER( hotslot_copro_r )
 
227
READ16_MEMBER(magic10_state::hotslot_copro_r)
220
228
{
221
229
        return 0x80;
222
230
}
223
231
 
224
 
static WRITE16_HANDLER( hotslot_copro_w )
 
232
WRITE16_MEMBER(magic10_state::hotslot_copro_w)
225
233
{
226
234
        logerror("Writing to copro: %d \n", data);
227
235
}
228
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229
 
static WRITE16_HANDLER( magic10_out_w )
 
237
WRITE16_MEMBER(magic10_state::magic10_out_w)
230
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{
231
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/*
232
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  ----------------------------------------------
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        output_set_lamp_value(7, (data >> 6) & 1);              /* Lamp 7 - PLAY (BET/TAKE/CANCEL) */
276
284
        output_set_lamp_value(8, (data >> 8) & 1);              /* Lamp 8 - PAYOUT/SUPERGAME */
277
285
 
278
 
        coin_counter_w(space->machine(), 0, data & 0x400);
 
286
        coin_counter_w(machine(), 0, data & 0x400);
279
287
}
280
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281
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/***************************
282
290
*       Memory Maps        *
283
291
***************************/
284
292
 
285
 
static ADDRESS_MAP_START( magic10_map, AS_PROGRAM, 16 )
 
293
static ADDRESS_MAP_START( magic10_map, AS_PROGRAM, 16, magic10_state )
286
294
        AM_RANGE(0x000000, 0x03ffff) AM_ROM
287
 
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer1_videoram)
288
 
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer0_videoram)
289
 
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer2_videoram)
 
295
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_SHARE("layer1_videoram")
 
296
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_SHARE("layer0_videoram")
 
297
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_SHARE("layer2_videoram")
290
298
        AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
291
 
        AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
 
299
        AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
292
300
        AM_RANGE(0x400000, 0x400001) AM_READ_PORT("INPUTS")
293
301
        AM_RANGE(0x400002, 0x400003) AM_READ_PORT("DSW")
294
302
        AM_RANGE(0x400008, 0x400009) AM_WRITE(magic10_out_w)
295
 
        AM_RANGE(0x40000a, 0x40000b) AM_DEVREADWRITE8_MODERN("oki", okim6295_device, read, write, 0x00ff)
 
303
        AM_RANGE(0x40000a, 0x40000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
296
304
        AM_RANGE(0x40000e, 0x40000f) AM_WRITENOP
297
 
        AM_RANGE(0x400080, 0x400087) AM_RAM AM_BASE_MEMBER(magic10_state, m_vregs)
 
305
        AM_RANGE(0x400080, 0x400087) AM_RAM AM_SHARE("vregs")
298
306
        AM_RANGE(0x600000, 0x603fff) AM_RAM
299
307
ADDRESS_MAP_END
300
308
 
301
 
static ADDRESS_MAP_START( magic10a_map, AS_PROGRAM, 16 )
 
309
static ADDRESS_MAP_START( magic10a_map, AS_PROGRAM, 16, magic10_state )
302
310
        AM_RANGE(0x000000, 0x03ffff) AM_ROM
303
 
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer1_videoram)
304
 
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer0_videoram)
305
 
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer2_videoram)
 
311
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_SHARE("layer1_videoram")
 
312
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_SHARE("layer0_videoram")
 
313
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_SHARE("layer2_videoram")
306
314
        AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
307
 
        AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
 
315
        AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
308
316
        AM_RANGE(0x500000, 0x500001) AM_READ_PORT("INPUTS")
309
317
        AM_RANGE(0x500002, 0x500003) AM_READ_PORT("DSW")
310
318
        AM_RANGE(0x500008, 0x500009) AM_WRITE(magic10_out_w)
311
 
        AM_RANGE(0x50000a, 0x50000b) AM_DEVREADWRITE8_MODERN("oki", okim6295_device, read, write, 0x00ff)
 
319
        AM_RANGE(0x50000a, 0x50000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
312
320
        AM_RANGE(0x50000e, 0x50000f) AM_WRITENOP
313
 
        AM_RANGE(0x500080, 0x500087) AM_RAM AM_BASE_MEMBER(magic10_state, m_vregs)      // video registers?
 
321
        AM_RANGE(0x500080, 0x500087) AM_RAM AM_SHARE("vregs")   // video registers?
314
322
        AM_RANGE(0x600000, 0x603fff) AM_RAM
315
323
ADDRESS_MAP_END
316
324
 
317
 
static ADDRESS_MAP_START( magic102_map, AS_PROGRAM, 16 )
 
325
static ADDRESS_MAP_START( magic102_map, AS_PROGRAM, 16, magic10_state )
318
326
        AM_RANGE(0x000000, 0x03ffff) AM_ROM
319
 
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer1_videoram)
320
 
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer0_videoram)
321
 
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer2_videoram)
 
327
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_SHARE("layer1_videoram")
 
328
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_SHARE("layer0_videoram")
 
329
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_SHARE("layer2_videoram")
322
330
        AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
323
 
        AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
 
331
        AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
324
332
        AM_RANGE(0x500000, 0x500001) AM_READ(magic102_r)
325
333
        AM_RANGE(0x500004, 0x500005) AM_READNOP // gives credits
326
334
        AM_RANGE(0x500006, 0x500007) AM_READNOP // gives credits
329
337
        AM_RANGE(0x500002, 0x50001f) AM_READNOP
330
338
        AM_RANGE(0x500002, 0x50001f) AM_WRITENOP
331
339
        AM_RANGE(0x600000, 0x603fff) AM_RAM
332
 
        AM_RANGE(0x700000, 0x700001) AM_DEVREADWRITE8_MODERN("oki", okim6295_device, read, write, 0x00ff)
333
 
        AM_RANGE(0x700080, 0x700087) AM_RAM AM_BASE_MEMBER(magic10_state, m_vregs)      // video registers?
 
340
        AM_RANGE(0x700000, 0x700001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
 
341
        AM_RANGE(0x700080, 0x700087) AM_RAM AM_SHARE("vregs")   // video registers?
334
342
ADDRESS_MAP_END
335
343
 
336
 
static ADDRESS_MAP_START( hotslot_map, AS_PROGRAM, 16 )
 
344
static ADDRESS_MAP_START( hotslot_map, AS_PROGRAM, 16, magic10_state )
337
345
        AM_RANGE(0x000000, 0x03ffff) AM_ROM
338
 
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer1_videoram)
339
 
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer0_videoram)
340
 
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer2_videoram)
 
346
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_SHARE("layer1_videoram")
 
347
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_SHARE("layer0_videoram")
 
348
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_SHARE("layer2_videoram")
341
349
        AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
342
 
        AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
 
350
        AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
343
351
        AM_RANGE(0x500004, 0x500005) AM_READWRITE(hotslot_copro_r, hotslot_copro_w)     // copro comm
344
352
        AM_RANGE(0x500006, 0x500011) AM_RAM
345
353
        AM_RANGE(0x500012, 0x500013) AM_READ_PORT("IN0")
348
356
        AM_RANGE(0x500018, 0x500019) AM_READ_PORT("DSW1")
349
357
        AM_RANGE(0x50001a, 0x50001d) AM_WRITENOP
350
358
        AM_RANGE(0x600000, 0x603fff) AM_RAM
351
 
        AM_RANGE(0x70000a, 0x70000b) AM_DEVREADWRITE8_MODERN("oki", okim6295_device, read, write, 0x00ff)
352
 
        AM_RANGE(0x700080, 0x700087) AM_RAM AM_BASE_MEMBER(magic10_state, m_vregs)
 
359
        AM_RANGE(0x70000a, 0x70000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
 
360
        AM_RANGE(0x700080, 0x700087) AM_RAM AM_SHARE("vregs")
353
361
ADDRESS_MAP_END
354
362
 
355
 
static ADDRESS_MAP_START( sgsafari_map, AS_PROGRAM, 16 )
 
363
static ADDRESS_MAP_START( sgsafari_map, AS_PROGRAM, 16, magic10_state )
356
364
        AM_RANGE(0x000000, 0x03ffff) AM_ROM
357
 
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer1_videoram)
358
 
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer0_videoram)
359
 
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE_MEMBER(magic10_state, m_layer2_videoram)
 
365
        AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_SHARE("layer1_videoram")
 
366
        AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_SHARE("layer0_videoram")
 
367
        AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_SHARE("layer2_videoram")
360
368
        AM_RANGE(0x200000, 0x203fff) AM_RAM AM_SHARE("nvram")
361
 
        AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
 
369
        AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
362
370
        AM_RANGE(0x500002, 0x500003) AM_READ_PORT("DSW1")
363
371
        AM_RANGE(0x500008, 0x500009) AM_WRITE(magic10_out_w)
364
 
        AM_RANGE(0x50000a, 0x50000b) AM_DEVREADWRITE8_MODERN("oki", okim6295_device, read, write, 0x00ff)
 
372
        AM_RANGE(0x50000a, 0x50000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
365
373
        AM_RANGE(0x50000e, 0x50000f) AM_READ_PORT("IN0")
366
 
        AM_RANGE(0x500080, 0x500087) AM_RAM AM_BASE_MEMBER(magic10_state, m_vregs)      // video registers?
 
374
        AM_RANGE(0x500080, 0x500087) AM_RAM AM_SHARE("vregs")   // video registers?
367
375
        AM_RANGE(0x600000, 0x603fff) AM_RAM
368
376
ADDRESS_MAP_END
369
377
/*
419
427
        PORT_DIPSETTING(      0x0800, "Note A: 20 - Note B: 40 - Note C: 100 - Note D: 200" )
420
428
        PORT_DIPSETTING(      0x0400, "Note A: 50 - Note B: 100 - Note C: 500 - Note D: 1000" )
421
429
        PORT_DIPSETTING(      0x0c00, "Note A: 100 - Note B: 200 - Note C: 1000 - Note D: 2000" )
422
 
        PORT_DIPNAME( 0x3000, 0x3000, "Lots At" )                       PORT_CONDITION("DSW", 0xc000, PORTCOND_EQUALS, 0xc000)
 
430
        PORT_DIPNAME( 0x3000, 0x3000, "Lots At" )                       PORT_CONDITION("DSW", 0xc000, EQUALS, 0xc000)
423
431
        PORT_DIPSETTING(      0x0000, "50 200 500 1000 2000" )
424
432
        PORT_DIPSETTING(      0x1000, "100 300 1000 3000 5000" )
425
433
        PORT_DIPSETTING(      0x2000, "200 500 2000 3000 5000" )
426
434
        PORT_DIPSETTING(      0x3000, "500 1000 2000 4000 8000" )
427
 
        PORT_DIPNAME( 0x3000, 0x3000, "1 Ticket Won" )          PORT_CONDITION("DSW", 0xc000, PORTCOND_EQUALS, 0x8000)
 
435
        PORT_DIPNAME( 0x3000, 0x3000, "1 Ticket Won" )          PORT_CONDITION("DSW", 0xc000, EQUALS, 0x8000)
428
436
//  PORT_DIPSETTING(      0x0000, "Every 100 Score" )
429
437
//  PORT_DIPSETTING(      0x1000, "Every 100 Score" )
430
438
//  PORT_DIPSETTING(      0x2000, "Every 100 Score" )
431
439
        PORT_DIPSETTING(      0x3000, "Every 100 Score" )
432
 
        PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unused ) )       PORT_CONDITION("DSW", 0xc000, PORTCOND_EQUALS, 0x4000)
 
440
        PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unused ) )       PORT_CONDITION("DSW", 0xc000, EQUALS, 0x4000)
433
441
        PORT_DIPSETTING(      0x1000, DEF_STR( Off ) )
434
442
        PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
435
 
        PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unused ) )       PORT_CONDITION("DSW", 0xc000, PORTCOND_EQUALS, 0x4000)
 
443
        PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unused ) )       PORT_CONDITION("DSW", 0xc000, EQUALS, 0x4000)
436
444
        PORT_DIPSETTING(      0x2000, DEF_STR( Off ) )
437
445
        PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
438
 
        PORT_DIPNAME( 0x3000, 0x3000, "1 Play Won" )            PORT_CONDITION("DSW", 0xc000, PORTCOND_EQUALS, 0x0000)
 
446
        PORT_DIPNAME( 0x3000, 0x3000, "1 Play Won" )            PORT_CONDITION("DSW", 0xc000, EQUALS, 0x0000)
439
447
//  PORT_DIPSETTING(      0x0000, "Every 10 Score" )
440
448
//  PORT_DIPSETTING(      0x1000, "Every 10 Score" )
441
449
//  PORT_DIPSETTING(      0x2000, "Every 10 Score" )