← Back to branch summary

~ubuntu-branches/debian/sid/mame/sid

« back to all changes in this revision

Viewing changes to src/mame/drivers/topspeed.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

Show diffs side-by-side

added added

removed removed

Lines of Context:
src/mame/drivers/topspeed.c
243
243
#include "topspeed.lh"
244
244
 
245
245
 
246
 
static READ16_HANDLER( sharedram_r )
 
246
READ16_MEMBER(topspeed_state::sharedram_r)
247
247
{
248
 
        topspeed_state *state = space->machine().driver_data<topspeed_state>();
249
 
        return state->m_sharedram[offset];
 
248
        return m_sharedram[offset];
250
249
}
251
250
 
252
 
static WRITE16_HANDLER( sharedram_w )
 
251
WRITE16_MEMBER(topspeed_state::sharedram_w)
253
252
{
254
 
        topspeed_state *state = space->machine().driver_data<topspeed_state>();
255
 
        COMBINE_DATA(&state->m_sharedram[offset]);
 
253
        COMBINE_DATA(&m_sharedram[offset]);
256
254
}
257
255
 
258
256
static void parse_control( running_machine &machine )   /* assumes Z80 sandwiched between 68Ks */
264
262
        device_set_input_line(state->m_subcpu, INPUT_LINE_RESET, (state->m_cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
265
263
}
266
264
 
267
 
static WRITE16_HANDLER( cpua_ctrl_w )
 
265
WRITE16_MEMBER(topspeed_state::cpua_ctrl_w)
268
266
{
269
 
        topspeed_state *state = space->machine().driver_data<topspeed_state>();
270
267
 
271
268
        if ((data & 0xff00) && ((data & 0xff) == 0))
272
269
                data = data >> 8;       /* for Wgp */
273
270
 
274
 
        state->m_cpua_ctrl = data;
275
 
 
276
 
        parse_control(space->machine());
277
 
 
278
 
        logerror("CPU #0 PC %06x: write %04x to cpu control\n", cpu_get_pc(&space->device()), data);
 
271
        m_cpua_ctrl = data;
 
272
 
 
273
        parse_control(machine());
 
274
 
 
275
        logerror("CPU #0 PC %06x: write %04x to cpu control\n", cpu_get_pc(&space.device()), data);
279
276
}
280
277
 
281
278
 
323
320
#define STEER_PORT_TAG   "STEER"
324
321
#define FAKE_PORT_TAG    "FAKE"
325
322
 
326
 
static READ8_HANDLER( topspeed_input_bypass_r )
 
323
READ8_MEMBER(topspeed_state::topspeed_input_bypass_r)
327
324
{
328
 
        topspeed_state *state = space->machine().driver_data<topspeed_state>();
329
 
        UINT8 port = tc0220ioc_port_r(state->m_tc0220ioc, 0);   /* read port number */
 
325
        UINT8 port = tc0220ioc_port_r(m_tc0220ioc, 0);  /* read port number */
330
326
        int steer = 0;
331
 
        int analogue_steer = input_port_read_safe(space->machine(), STEER_PORT_TAG, 0x00);
332
 
        int fake = input_port_read_safe(space->machine(), FAKE_PORT_TAG, 0x00);
 
327
        int analogue_steer = ioport(STEER_PORT_TAG)->read_safe(0x00);
 
328
        int fake = ioport(FAKE_PORT_TAG)->read_safe(0x00);
333
329
 
334
330
        if (!(fake & 0x10))     /* Analogue steer (the real control method) */
335
331
        {
361
357
                        return steer >> 8;
362
358
 
363
359
                default:
364
 
                        return tc0220ioc_portreg_r(state->m_tc0220ioc, offset);
 
360
                        return tc0220ioc_portreg_r(m_tc0220ioc, offset);
365
361
        }
366
362
}
367
363
 
368
364
 
369
 
static READ16_HANDLER( topspeed_motor_r )
 
365
READ16_MEMBER(topspeed_state::topspeed_motor_r)
370
366
{
371
367
        switch (offset)
372
368
        {
373
369
                case 0x0:
374
 
                        return (space->machine().rand() & 0xff);        /* motor status ?? */
 
370
                        return (machine().rand() & 0xff);       /* motor status ?? */
375
371
 
376
372
                case 0x101:
377
373
                        return 0x55;    /* motor cpu status ? */
378
374
 
379
375
                default:
380
 
                        logerror("CPU #0 PC %06x: warning - read from motor cpu %03x\n", cpu_get_pc(&space->device()), offset);
 
376
                        logerror("CPU #0 PC %06x: warning - read from motor cpu %03x\n", cpu_get_pc(&space.device()), offset);
381
377
                        return 0;
382
378
        }
383
379
}
384
380
 
385
 
static WRITE16_HANDLER( topspeed_motor_w )
 
381
WRITE16_MEMBER(topspeed_state::topspeed_motor_w)
386
382
{
387
383
        /* Writes $900000-25 and $900200-219 */
388
 
        logerror("CPU #0 PC %06x: warning - write %04x to motor cpu %03x\n", cpu_get_pc(&space->device()), data, offset);
 
384
        logerror("CPU #0 PC %06x: warning - write %04x to motor cpu %03x\n", cpu_get_pc(&space.device()), data, offset);
389
385
}
390
386
 
391
387
 
396
392
static void reset_sound_region( running_machine &machine )
397
393
{
398
394
        topspeed_state *state = machine.driver_data<topspeed_state>();
399
 
        memory_set_bank(machine,  "bank10", state->m_banknum);
 
395
        state->membank("bank10")->set_entry(state->m_banknum);
400
396
}
401
397
 
402
398
static WRITE8_DEVICE_HANDLER( sound_bankswitch_w )      /* assumes Z80 sandwiched between 68Ks */
416
412
        }
417
413
        else
418
414
        {
419
 
                state->m_adpcm_data = device->machine().region("adpcm")->base()[state->m_adpcm_pos];
 
415
                state->m_adpcm_data = device->machine().root_device().memregion("adpcm")->base()[state->m_adpcm_pos];
420
416
                state->m_adpcm_pos = (state->m_adpcm_pos + 1) & 0x1ffff;
421
417
                msm5205_data_w(device, state->m_adpcm_data >> 4);
422
418
        }
442
438
***********************************************************/
443
439
 
444
440
 
445
 
static ADDRESS_MAP_START( topspeed_map, AS_PROGRAM, 16 )
 
441
static ADDRESS_MAP_START( topspeed_map, AS_PROGRAM, 16, topspeed_state )
446
442
        AM_RANGE(0x000000, 0x0fffff) AM_ROM
447
 
        AM_RANGE(0x400000, 0x40ffff) AM_READWRITE(sharedram_r, sharedram_w) AM_BASE_SIZE_MEMBER(topspeed_state, m_sharedram, m_sharedram_size)
448
 
        AM_RANGE(0x500000, 0x503fff) AM_RAM_WRITE(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
 
443
        AM_RANGE(0x400000, 0x40ffff) AM_READWRITE(sharedram_r, sharedram_w) AM_SHARE("sharedram")
 
444
        AM_RANGE(0x500000, 0x503fff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
449
445
        AM_RANGE(0x600002, 0x600003) AM_WRITE(cpua_ctrl_w)
450
 
        AM_RANGE(0x7e0000, 0x7e0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_port_w, 0x00ff)
451
 
        AM_RANGE(0x7e0002, 0x7e0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
452
 
        AM_RANGE(0x800000, 0x8003ff) AM_RAM AM_BASE_MEMBER(topspeed_state, m_raster_ctrl)
 
446
        AM_RANGE(0x7e0000, 0x7e0001) AM_READNOP AM_DEVWRITE8_LEGACY("tc0140syt", tc0140syt_port_w, 0x00ff)
 
447
        AM_RANGE(0x7e0002, 0x7e0003) AM_DEVREADWRITE8_LEGACY("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)
 
448
        AM_RANGE(0x800000, 0x8003ff) AM_RAM AM_SHARE("raster_ctrl")
453
449
        AM_RANGE(0x800400, 0x80ffff) AM_RAM
454
 
        AM_RANGE(0xa00000, 0xa0ffff) AM_DEVREADWRITE("pc080sn_1", pc080sn_word_r, pc080sn_word_w)
455
 
        AM_RANGE(0xa20000, 0xa20003) AM_DEVWRITE("pc080sn_1", pc080sn_yscroll_word_w)
456
 
        AM_RANGE(0xa40000, 0xa40003) AM_DEVWRITE("pc080sn_1", pc080sn_xscroll_word_w)
457
 
        AM_RANGE(0xa50000, 0xa50003) AM_DEVWRITE("pc080sn_1", pc080sn_ctrl_word_w)
458
 
        AM_RANGE(0xb00000, 0xb0ffff) AM_DEVREADWRITE("pc080sn_2", pc080sn_word_r, pc080sn_word_w)
459
 
        AM_RANGE(0xb20000, 0xb20003) AM_DEVWRITE("pc080sn_2", pc080sn_yscroll_word_w)
460
 
        AM_RANGE(0xb40000, 0xb40003) AM_DEVWRITE("pc080sn_2", pc080sn_xscroll_word_w)
461
 
        AM_RANGE(0xb50000, 0xb50003) AM_DEVWRITE("pc080sn_2", pc080sn_ctrl_word_w)
462
 
        AM_RANGE(0xd00000, 0xd00fff) AM_RAM AM_BASE_SIZE_MEMBER(topspeed_state, m_spriteram, m_spriteram_size)
463
 
        AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_BASE_MEMBER(topspeed_state, m_spritemap)
 
450
        AM_RANGE(0xa00000, 0xa0ffff) AM_DEVREADWRITE_LEGACY("pc080sn_1", pc080sn_word_r, pc080sn_word_w)
 
451
        AM_RANGE(0xa20000, 0xa20003) AM_DEVWRITE_LEGACY("pc080sn_1", pc080sn_yscroll_word_w)
 
452
        AM_RANGE(0xa40000, 0xa40003) AM_DEVWRITE_LEGACY("pc080sn_1", pc080sn_xscroll_word_w)
 
453
        AM_RANGE(0xa50000, 0xa50003) AM_DEVWRITE_LEGACY("pc080sn_1", pc080sn_ctrl_word_w)
 
454
        AM_RANGE(0xb00000, 0xb0ffff) AM_DEVREADWRITE_LEGACY("pc080sn_2", pc080sn_word_r, pc080sn_word_w)
 
455
        AM_RANGE(0xb20000, 0xb20003) AM_DEVWRITE_LEGACY("pc080sn_2", pc080sn_yscroll_word_w)
 
456
        AM_RANGE(0xb40000, 0xb40003) AM_DEVWRITE_LEGACY("pc080sn_2", pc080sn_xscroll_word_w)
 
457
        AM_RANGE(0xb50000, 0xb50003) AM_DEVWRITE_LEGACY("pc080sn_2", pc080sn_ctrl_word_w)
 
458
        AM_RANGE(0xd00000, 0xd00fff) AM_RAM AM_SHARE("spriteram")
 
459
        AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_SHARE("spritemap")
464
460
ADDRESS_MAP_END
465
461
 
466
 
static ADDRESS_MAP_START( topspeed_cpub_map, AS_PROGRAM, 16 )
 
462
static ADDRESS_MAP_START( topspeed_cpub_map, AS_PROGRAM, 16, topspeed_state )
467
463
        AM_RANGE(0x000000, 0x01ffff) AM_ROM
468
 
        AM_RANGE(0x400000, 0X40ffff) AM_READWRITE(sharedram_r, sharedram_w) AM_BASE_MEMBER(topspeed_state, m_sharedram)
469
 
        AM_RANGE(0x880000, 0x880001) AM_READ8(topspeed_input_bypass_r, 0x00ff) AM_DEVWRITE8("tc0220ioc", tc0220ioc_portreg_w, 0x00ff)
470
 
        AM_RANGE(0x880002, 0x880003) AM_DEVREADWRITE8("tc0220ioc", tc0220ioc_port_r, tc0220ioc_port_w, 0x00ff)
 
464
        AM_RANGE(0x400000, 0X40ffff) AM_READWRITE(sharedram_r, sharedram_w) AM_SHARE("sharedram")
 
465
        AM_RANGE(0x880000, 0x880001) AM_READ8(topspeed_input_bypass_r, 0x00ff) AM_DEVWRITE8_LEGACY("tc0220ioc", tc0220ioc_portreg_w, 0x00ff)
 
466
        AM_RANGE(0x880002, 0x880003) AM_DEVREADWRITE8_LEGACY("tc0220ioc", tc0220ioc_port_r, tc0220ioc_port_w, 0x00ff)
471
467
        AM_RANGE(0x900000, 0x9003ff) AM_READWRITE(topspeed_motor_r, topspeed_motor_w)   /* motor CPU */
472
468
ADDRESS_MAP_END
473
469
 
474
470
 
475
471
/***************************************************************************/
476
472
 
477
 
static ADDRESS_MAP_START( z80_map, AS_PROGRAM, 8 )
 
473
static ADDRESS_MAP_START( z80_map, AS_PROGRAM, 8, topspeed_state )
478
474
        AM_RANGE(0x0000, 0x3fff) AM_ROM
479
475
        AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank10")
480
476
        AM_RANGE(0x8000, 0x8fff) AM_RAM
481
 
        AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_r, ym2151_w)
482
 
        AM_RANGE(0xa000, 0xa000) AM_DEVWRITE("tc0140syt", tc0140syt_slave_port_w)
483
 
        AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
484
 
        AM_RANGE(0xb000, 0xb000) AM_DEVWRITE("msm", topspeed_msm5205_address_w)
 
477
        AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
 
478
        AM_RANGE(0xa000, 0xa000) AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_slave_port_w)
 
479
        AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
 
480
        AM_RANGE(0xb000, 0xb000) AM_DEVWRITE_LEGACY("msm", topspeed_msm5205_address_w)
485
481
//  AM_RANGE(0xb400, 0xb400) // msm5205 start? doesn't seem to work right
486
 
        AM_RANGE(0xb800, 0xb800) AM_DEVWRITE("msm", topspeed_msm5205_stop_w)
 
482
        AM_RANGE(0xb800, 0xb800) AM_DEVWRITE_LEGACY("msm", topspeed_msm5205_stop_w)
487
483
//  AM_RANGE(0xc000, 0xc000) // ??
488
484
//  AM_RANGE(0xc400, 0xc400) // ??
489
485
//  AM_RANGE(0xc800, 0xc800) // ??
625
621
 
626
622
static const ym2151_interface ym2151_config =
627
623
{
628
 
        irq_handler,
629
 
        sound_bankswitch_w
 
624
        DEVCB_LINE(irq_handler),
 
625
        DEVCB_HANDLER(sound_bankswitch_w)
630
626
};
631
627
 
632
628
static const msm5205_interface msm5205_config =
650
646
{
651
647
        topspeed_state *state = machine.driver_data<topspeed_state>();
652
648
 
653
 
        memory_configure_bank(machine, "bank10", 0, 4, machine.region("audiocpu")->base() + 0xc000, 0x4000);
 
649
        state->membank("bank10")->configure_entries(0, 4, state->memregion("audiocpu")->base() + 0xc000, 0x4000);
654
650
 
655
651
        state->m_maincpu = machine.device("maincpu");
656
652
        state->m_subcpu = machine.device("sub");