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Viewing changes to src/mame/drivers/bking.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/bking.c
23
23
#include "machine/buggychl.h"
24
24
#include "includes/bking.h"
25
25
 
26
 
static READ8_HANDLER( bking_sndnmi_disable_r )
 
26
READ8_MEMBER(bking_state::bking_sndnmi_disable_r)
27
27
{
28
 
        bking_state *state = space->machine().driver_data<bking_state>();
29
 
        state->m_sound_nmi_enable = 0;
 
28
        m_sound_nmi_enable = 0;
30
29
        return 0;
31
30
}
32
31
 
33
 
static WRITE8_HANDLER( bking_sndnmi_enable_w )
 
32
WRITE8_MEMBER(bking_state::bking_sndnmi_enable_w)
34
33
{
35
 
        bking_state *state = space->machine().driver_data<bking_state>();
36
 
        state->m_sound_nmi_enable = 1;
 
34
        m_sound_nmi_enable = 1;
37
35
}
38
36
 
39
 
static WRITE8_HANDLER( bking_soundlatch_w )
 
37
WRITE8_MEMBER(bking_state::bking_soundlatch_w)
40
38
{
41
 
        bking_state *state = space->machine().driver_data<bking_state>();
42
39
        int i, code = 0;
43
40
 
44
41
        for (i = 0;i < 8;i++)
45
42
                if (data & (1 << i))
46
43
                        code |= 0x80 >> i;
47
44
 
48
 
        soundlatch_w(space, offset, code);
49
 
        if (state->m_sound_nmi_enable)
50
 
                device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
51
 
}
52
 
 
53
 
static WRITE8_HANDLER( bking3_addr_l_w )
54
 
{
55
 
        bking_state *state = space->machine().driver_data<bking_state>();
56
 
        state->m_addr_l = data;
57
 
}
58
 
 
59
 
static WRITE8_HANDLER( bking3_addr_h_w )
60
 
{
61
 
        bking_state *state = space->machine().driver_data<bking_state>();
62
 
        state->m_addr_h = data;
63
 
}
64
 
 
65
 
static READ8_HANDLER( bking3_extrarom_r )
66
 
{
67
 
        bking_state *state = space->machine().driver_data<bking_state>();
68
 
        UINT8 *rom = space->machine().region("user2")->base();
69
 
        return rom[state->m_addr_h * 256 + state->m_addr_l];
 
45
        soundlatch_byte_w(space, offset, code);
 
46
        if (m_sound_nmi_enable)
 
47
                device_set_input_line(m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
 
48
}
 
49
 
 
50
WRITE8_MEMBER(bking_state::bking3_addr_l_w)
 
51
{
 
52
        m_addr_l = data;
 
53
}
 
54
 
 
55
WRITE8_MEMBER(bking_state::bking3_addr_h_w)
 
56
{
 
57
        m_addr_h = data;
 
58
}
 
59
 
 
60
READ8_MEMBER(bking_state::bking3_extrarom_r)
 
61
{
 
62
        UINT8 *rom = memregion("user2")->base();
 
63
        return rom[m_addr_h * 256 + m_addr_l];
70
64
}
71
65
 
72
66
static WRITE8_DEVICE_HANDLER( unk_w )
77
71
*/
78
72
}
79
73
 
80
 
static READ8_HANDLER( bking3_ext_check_r )
 
74
READ8_MEMBER(bking_state::bking3_ext_check_r)
81
75
{
82
76
        return 0x31; //no "bad rom.", no "bad ext."
83
77
}
84
78
 
85
 
static ADDRESS_MAP_START( bking_map, AS_PROGRAM, 8 )
 
79
static ADDRESS_MAP_START( bking_map, AS_PROGRAM, 8, bking_state )
86
80
        AM_RANGE(0x0000, 0x7fff) AM_ROM
87
81
        AM_RANGE(0x8000, 0x83ff) AM_RAM
88
 
        AM_RANGE(0x9000, 0x97ff) AM_RAM_WRITE(bking_playfield_w) AM_BASE_MEMBER(bking_state, m_playfield_ram)
89
 
ADDRESS_MAP_END
90
 
 
91
 
static ADDRESS_MAP_START( bking_io_map, AS_IO, 8 )
92
 
        ADDRESS_MAP_GLOBAL_MASK(0xff)
93
 
        AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(bking_xld1_w)
94
 
        AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1") AM_WRITE(bking_yld1_w)
95
 
        AM_RANGE(0x02, 0x02) AM_READ_PORT("DSWA") AM_WRITE(bking_xld2_w)
96
 
        AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWB") AM_WRITE(bking_yld2_w)
97
 
        AM_RANGE(0x04, 0x04) AM_READ_PORT("DSWC") AM_WRITE(bking_xld3_w)
98
 
        AM_RANGE(0x05, 0x05) AM_READWRITE(bking_input_port_5_r, bking_yld3_w)
99
 
        AM_RANGE(0x06, 0x06) AM_READWRITE(bking_input_port_6_r, bking_msk_w)
100
 
        AM_RANGE(0x07, 0x07) AM_WRITE(watchdog_reset_w)
101
 
        AM_RANGE(0x08, 0x08) AM_WRITE(bking_cont1_w)
102
 
        AM_RANGE(0x09, 0x09) AM_WRITE(bking_cont2_w)
103
 
        AM_RANGE(0x0a, 0x0a) AM_WRITE(bking_cont3_w)
104
 
        AM_RANGE(0x0b, 0x0b) AM_WRITE(bking_soundlatch_w)
105
 
//  AM_RANGE(0x0c, 0x0c) AM_WRITE(bking_eport2_w)   this is not shown to be connected anywhere
106
 
        AM_RANGE(0x0d, 0x0d) AM_WRITE(bking_hitclr_w)
107
 
        AM_RANGE(0x07, 0x1f) AM_READ(bking_pos_r)
108
 
ADDRESS_MAP_END
109
 
 
110
 
static ADDRESS_MAP_START( bking3_io_map, AS_IO, 8 )
111
 
        ADDRESS_MAP_GLOBAL_MASK(0xff)
112
 
        AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(bking_xld1_w)
113
 
        AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1") AM_WRITE(bking_yld1_w)
114
 
        AM_RANGE(0x02, 0x02) AM_READ_PORT("DSWA") AM_WRITE(bking_xld2_w)
115
 
        AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWB") AM_WRITE(bking_yld2_w)
116
 
        AM_RANGE(0x04, 0x04) AM_READ_PORT("DSWC") AM_WRITE(bking_xld3_w)
117
 
        AM_RANGE(0x05, 0x05) AM_READWRITE(bking_input_port_5_r, bking_yld3_w)
118
 
        AM_RANGE(0x06, 0x06) AM_READWRITE(bking_input_port_6_r, bking_msk_w)
119
 
        AM_RANGE(0x07, 0x07) AM_WRITE(watchdog_reset_w)
120
 
        AM_RANGE(0x08, 0x08) AM_WRITE(bking_cont1_w)
121
 
        AM_RANGE(0x09, 0x09) AM_WRITE(bking_cont2_w)
122
 
        AM_RANGE(0x0a, 0x0a) AM_WRITE(bking_cont3_w)
123
 
        AM_RANGE(0x0b, 0x0b) AM_WRITE(bking_soundlatch_w)
124
 
//  AM_RANGE(0x0c, 0x0c) AM_WRITE(bking_eport2_w)   this is not shown to be connected anywhere
125
 
        AM_RANGE(0x0d, 0x0d) AM_WRITE(bking_hitclr_w)
126
 
        AM_RANGE(0x07, 0x1f) AM_READ(bking_pos_r)
127
 
        AM_RANGE(0x2f, 0x2f) AM_DEVREADWRITE("bmcu", buggychl_mcu_r, buggychl_mcu_w)
128
 
        AM_RANGE(0x4f, 0x4f) AM_DEVREADWRITE("bmcu", buggychl_mcu_status_r, unk_w)
 
82
        AM_RANGE(0x9000, 0x97ff) AM_RAM_WRITE(bking_playfield_w) AM_SHARE("playfield_ram")
 
83
ADDRESS_MAP_END
 
84
 
 
85
static ADDRESS_MAP_START( bking_io_map, AS_IO, 8, bking_state )
 
86
        ADDRESS_MAP_GLOBAL_MASK(0xff)
 
87
        AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(bking_xld1_w)
 
88
        AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1") AM_WRITE(bking_yld1_w)
 
89
        AM_RANGE(0x02, 0x02) AM_READ_PORT("DSWA") AM_WRITE(bking_xld2_w)
 
90
        AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWB") AM_WRITE(bking_yld2_w)
 
91
        AM_RANGE(0x04, 0x04) AM_READ_PORT("DSWC") AM_WRITE(bking_xld3_w)
 
92
        AM_RANGE(0x05, 0x05) AM_READWRITE(bking_input_port_5_r, bking_yld3_w)
 
93
        AM_RANGE(0x06, 0x06) AM_READWRITE(bking_input_port_6_r, bking_msk_w)
 
94
        AM_RANGE(0x07, 0x07) AM_WRITE(watchdog_reset_w)
 
95
        AM_RANGE(0x08, 0x08) AM_WRITE(bking_cont1_w)
 
96
        AM_RANGE(0x09, 0x09) AM_WRITE(bking_cont2_w)
 
97
        AM_RANGE(0x0a, 0x0a) AM_WRITE(bking_cont3_w)
 
98
        AM_RANGE(0x0b, 0x0b) AM_WRITE(bking_soundlatch_w)
 
99
//  AM_RANGE(0x0c, 0x0c) AM_WRITE_LEGACY(bking_eport2_w)   this is not shown to be connected anywhere
 
100
        AM_RANGE(0x0d, 0x0d) AM_WRITE(bking_hitclr_w)
 
101
        AM_RANGE(0x07, 0x1f) AM_READ(bking_pos_r)
 
102
ADDRESS_MAP_END
 
103
 
 
104
static ADDRESS_MAP_START( bking3_io_map, AS_IO, 8, bking_state )
 
105
        ADDRESS_MAP_GLOBAL_MASK(0xff)
 
106
        AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(bking_xld1_w)
 
107
        AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1") AM_WRITE(bking_yld1_w)
 
108
        AM_RANGE(0x02, 0x02) AM_READ_PORT("DSWA") AM_WRITE(bking_xld2_w)
 
109
        AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWB") AM_WRITE(bking_yld2_w)
 
110
        AM_RANGE(0x04, 0x04) AM_READ_PORT("DSWC") AM_WRITE(bking_xld3_w)
 
111
        AM_RANGE(0x05, 0x05) AM_READWRITE(bking_input_port_5_r, bking_yld3_w)
 
112
        AM_RANGE(0x06, 0x06) AM_READWRITE(bking_input_port_6_r, bking_msk_w)
 
113
        AM_RANGE(0x07, 0x07) AM_WRITE(watchdog_reset_w)
 
114
        AM_RANGE(0x08, 0x08) AM_WRITE(bking_cont1_w)
 
115
        AM_RANGE(0x09, 0x09) AM_WRITE(bking_cont2_w)
 
116
        AM_RANGE(0x0a, 0x0a) AM_WRITE(bking_cont3_w)
 
117
        AM_RANGE(0x0b, 0x0b) AM_WRITE(bking_soundlatch_w)
 
118
//  AM_RANGE(0x0c, 0x0c) AM_WRITE_LEGACY(bking_eport2_w)   this is not shown to be connected anywhere
 
119
        AM_RANGE(0x0d, 0x0d) AM_WRITE(bking_hitclr_w)
 
120
        AM_RANGE(0x07, 0x1f) AM_READ(bking_pos_r)
 
121
        AM_RANGE(0x2f, 0x2f) AM_DEVREADWRITE_LEGACY("bmcu", buggychl_mcu_r, buggychl_mcu_w)
 
122
        AM_RANGE(0x4f, 0x4f) AM_DEVREADWRITE_LEGACY("bmcu", buggychl_mcu_status_r, unk_w)
129
123
        AM_RANGE(0x60, 0x60) AM_READ(bking3_extrarom_r)
130
124
        AM_RANGE(0x6f, 0x6f) AM_READWRITE(bking3_ext_check_r, bking3_addr_h_w)
131
125
        AM_RANGE(0x8f, 0x8f) AM_WRITE(bking3_addr_l_w)
132
126
ADDRESS_MAP_END
133
127
 
134
 
static ADDRESS_MAP_START( bking_audio_map, AS_PROGRAM, 8 )
 
128
static ADDRESS_MAP_START( bking_audio_map, AS_PROGRAM, 8, bking_state )
135
129
        AM_RANGE(0x0000, 0x1fff) AM_ROM
136
130
        AM_RANGE(0x2000, 0x2fff) AM_ROM //only bking3
137
131
        AM_RANGE(0x4000, 0x43ff) AM_RAM
138
 
        AM_RANGE(0x4400, 0x4401) AM_DEVWRITE("ay1", ay8910_address_data_w)
139
 
        AM_RANGE(0x4401, 0x4401) AM_DEVREAD("ay1", ay8910_r)
140
 
        AM_RANGE(0x4402, 0x4403) AM_DEVWRITE("ay2", ay8910_address_data_w)
141
 
        AM_RANGE(0x4403, 0x4403) AM_DEVREAD("ay2", ay8910_r)
142
 
        AM_RANGE(0x4800, 0x4800) AM_READ(soundlatch_r)
 
132
        AM_RANGE(0x4400, 0x4401) AM_DEVWRITE_LEGACY("ay1", ay8910_address_data_w)
 
133
        AM_RANGE(0x4401, 0x4401) AM_DEVREAD_LEGACY("ay1", ay8910_r)
 
134
        AM_RANGE(0x4402, 0x4403) AM_DEVWRITE_LEGACY("ay2", ay8910_address_data_w)
 
135
        AM_RANGE(0x4403, 0x4403) AM_DEVREAD_LEGACY("ay2", ay8910_r)
 
136
        AM_RANGE(0x4800, 0x4800) AM_READ(soundlatch_byte_r)
143
137
        AM_RANGE(0x4802, 0x4802) AM_READWRITE(bking_sndnmi_disable_r, bking_sndnmi_enable_w)
144
138
        AM_RANGE(0xe000, 0xefff) AM_ROM   /* Space for diagnostic ROM */
145
139
ADDRESS_MAP_END
146
140
 
147
141
#if 0
148
 
static READ8_HANDLER( bking3_68705_port_a_r )
 
142
READ8_MEMBER(bking_state::bking3_68705_port_a_r)
149
143
{
150
 
        bking_state *state = space->machine().driver_data<bking_state>();
151
 
        //printf("port_a_r = %02X\n",(state->m_port_a_out & state->m_ddr_a) | (state->m_port_a_in & ~state->m_ddr_a));
152
 
        return (state->m_port_a_out & state->m_ddr_a) | (state->m_port_a_in & ~state->m_ddr_a);
 
144
        //printf("port_a_r = %02X\n",(m_port_a_out & m_ddr_a) | (m_port_a_in & ~m_ddr_a));
 
145
        return (m_port_a_out & m_ddr_a) | (m_port_a_in & ~m_ddr_a);
153
146
}
154
147
 
155
 
static WRITE8_HANDLER( bking3_68705_port_a_w )
 
148
WRITE8_MEMBER(bking_state::bking3_68705_port_a_w)
156
149
{
157
 
        bking_state *state = space->machine().driver_data<bking_state>();
158
 
        state->m_port_a_out = data;
 
150
        m_port_a_out = data;
159
151
//  printf("port_a_out = %02X\n",data);
160
152
}
161
153
 
162
 
static WRITE8_HANDLER( bking3_68705_ddr_a_w )
163
 
{
164
 
        bking_state *state = space->machine().driver_data<bking_state>();
165
 
        state->m_ddr_a = data;
166
 
}
167
 
 
168
 
static READ8_HANDLER( bking3_68705_port_b_r )
169
 
{
170
 
        bking_state *state = space->machine().driver_data<bking_state>();
171
 
        return (state->m_port_b_out & state->m_ddr_b) | (state->m_port_b_in & ~state->m_ddr_b);
172
 
}
173
 
 
174
 
static WRITE8_HANDLER( bking3_68705_port_b_w )
175
 
{
176
 
        bking_state *state = space->machine().driver_data<bking_state>();
 
154
WRITE8_MEMBER(bking_state::bking3_68705_ddr_a_w)
 
155
{
 
156
        m_ddr_a = data;
 
157
}
 
158
 
 
159
READ8_MEMBER(bking_state::bking3_68705_port_b_r)
 
160
{
 
161
        return (m_port_b_out & m_ddr_b) | (m_port_b_in & ~m_ddr_b);
 
162
}
 
163
 
 
164
WRITE8_MEMBER(bking_state::bking3_68705_port_b_w)
 
165
{
177
166
//  if(data != 0xff)
178
167
//      printf("port_b_out = %02X\n",data);
179
168
 
180
169
        if (~data & 0x02)
181
170
        {
182
 
                state->m_port_a_in = from_main;
183
 
                if (main_sent) cputag_set_input_line(space->machine(), "mcu", 0, CLEAR_LINE);
 
171
                m_port_a_in = from_main;
 
172
                if (main_sent) cputag_set_input_line(machine(), "mcu", 0, CLEAR_LINE);
184
173
                main_sent = 0;
185
174
        }
186
175
 
187
176
        if (~data & 0x04)
188
177
        {
189
178
                /* 68705 is writing data for the Z80 */
190
 
                from_mcu = state->m_port_a_out;
 
179
                from_mcu = m_port_a_out;
191
180
                mcu_sent = 1;
192
181
        }
193
182
 
194
183
        if(data != 0xff && data != 0xfb && data != 0xfd)
195
184
                printf("port_b_w = %X\n",data);
196
185
 
197
 
        state->m_port_b_out = data;
 
186
        m_port_b_out = data;
198
187
}
199
188
 
200
 
static WRITE8_HANDLER( bking3_68705_ddr_b_w )
 
189
WRITE8_MEMBER(bking_state::bking3_68705_ddr_b_w)
201
190
{
202
 
        bking_state *state = space->machine().driver_data<bking_state>();
203
 
        state->m_ddr_b = data;
 
191
        m_ddr_b = data;
204
192
}
205
193
 
206
 
static READ8_HANDLER( bking3_68705_port_c_r )
 
194
READ8_MEMBER(bking_state::bking3_68705_port_c_r)
207
195
{
208
196
        int port_c_in = 0;
209
197
        if (main_sent) port_c_in |= 0x01;
210
198
        if (!mcu_sent) port_c_in |= 0x02;
211
 
//logerror("%04x: 68705 port C read %02x\n",cpu_get_pc(&space->device()),port_c_in);
 
199
//logerror("%04x: 68705 port C read %02x\n",cpu_get_pc(&space.device()),port_c_in);
212
200
        return port_c_in;
213
201
}
214
202
#endif