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Viewing changes to src/mame/drivers/pipeline.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/pipeline.c
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#include "cpu/z80/z80.h"
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#include "machine/z80ctc.h"
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#include "sound/2203intf.h"
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#include "machine/8255ppi.h"
 
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#include "machine/i8255.h"
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#include "cpu/z80/z80daisy.h"
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#include "cpu/m6805/m6805.h"
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{
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public:
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        pipeline_state(const machine_config &mconfig, device_type type, const char *tag)
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                : driver_device(mconfig, type, tag) { }
 
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                : driver_device(mconfig, type, tag) ,
 
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                m_vram1(*this, "vram1"),
 
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                m_vram2(*this, "vram2"){ }
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        tilemap_t *m_tilemap1;
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        tilemap_t *m_tilemap2;
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        UINT8 *m_vram1;
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        UINT8 *m_vram2;
 
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        required_shared_ptr<UINT8> m_vram1;
 
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        required_shared_ptr<UINT8> m_vram2;
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        UINT8 m_vidctrl;
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        UINT8 *m_palram;
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        UINT8 m_toMCU;
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        UINT8 m_fromMCU;
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        UINT8 m_ddrA;
 
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        DECLARE_WRITE8_MEMBER(vram2_w);
 
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        DECLARE_WRITE8_MEMBER(vram1_w);
 
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        DECLARE_WRITE8_MEMBER(mcu_portA_w);
 
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        DECLARE_READ8_MEMBER(mcu_portA_r);
 
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        DECLARE_WRITE8_MEMBER(mcu_ddrA_w);
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};
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        state->m_vidctrl=data;
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}
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static WRITE8_HANDLER(vram2_w)
 
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WRITE8_MEMBER(pipeline_state::vram2_w)
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{
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        pipeline_state *state = space->machine().driver_data<pipeline_state>();
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        if(!(state->m_vidctrl&1))
 
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        if(!(m_vidctrl&1))
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        {
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                state->m_tilemap1->mark_tile_dirty(offset&0x7ff);
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                state->m_vram2[offset]=data;
 
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                m_tilemap1->mark_tile_dirty(offset&0x7ff);
 
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                m_vram2[offset]=data;
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        }
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        else
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        {
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                 state->m_palram[offset]=data;
 
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                 m_palram[offset]=data;
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                 if(offset<0x300)
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                 {
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                        offset&=0xff;
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                        palette_set_color_rgb(space->machine(), offset, pal6bit(state->m_palram[offset]), pal6bit(state->m_palram[offset+0x100]), pal6bit(state->m_palram[offset+0x200]));
 
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                        palette_set_color_rgb(machine(), offset, pal6bit(m_palram[offset]), pal6bit(m_palram[offset+0x100]), pal6bit(m_palram[offset+0x200]));
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                 }
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        }
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}
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static WRITE8_HANDLER(vram1_w)
 
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WRITE8_MEMBER(pipeline_state::vram1_w)
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{
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        pipeline_state *state = space->machine().driver_data<pipeline_state>();
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        state->m_tilemap2->mark_tile_dirty(offset&0x7ff);
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        state->m_vram1[offset]=data;
 
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        m_tilemap2->mark_tile_dirty(offset&0x7ff);
 
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        m_vram1[offset]=data;
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}
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static READ8_DEVICE_HANDLER(protection_r)
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        device->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
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}
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static ADDRESS_MAP_START( cpu0_mem, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpu0_mem, AS_PROGRAM, 8, pipeline_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0x87ff) AM_RAM
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        AM_RANGE(0x8800, 0x97ff) AM_RAM_WRITE(vram1_w) AM_BASE_MEMBER(pipeline_state, m_vram1)
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        AM_RANGE(0x9800, 0xa7ff) AM_RAM_WRITE(vram2_w) AM_BASE_MEMBER(pipeline_state, m_vram2)
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        AM_RANGE(0xb800, 0xb803) AM_DEVREADWRITE("ppi8255_0", ppi8255_r, ppi8255_w)
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        AM_RANGE(0xb810, 0xb813) AM_DEVREADWRITE("ppi8255_1", ppi8255_r, ppi8255_w)
 
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        AM_RANGE(0x8800, 0x97ff) AM_RAM_WRITE(vram1_w) AM_SHARE("vram1")
 
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        AM_RANGE(0x9800, 0xa7ff) AM_RAM_WRITE(vram2_w) AM_SHARE("vram2")
 
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        AM_RANGE(0xb800, 0xb803) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)
 
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        AM_RANGE(0xb810, 0xb813) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
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        AM_RANGE(0xb830, 0xb830) AM_NOP
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        AM_RANGE(0xb840, 0xb840) AM_NOP
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( cpu1_mem, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpu1_mem, AS_PROGRAM, 8, pipeline_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0xc000, 0xc7ff) AM_RAM
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        AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ppi8255_2", ppi8255_r, ppi8255_w)
 
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        AM_RANGE(0xe000, 0xe003) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( sound_port, AS_IO, 8 )
 
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static ADDRESS_MAP_START( sound_port, AS_IO, 8, pipeline_state )
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        ADDRESS_MAP_GLOBAL_MASK(0xff)
205
 
        AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ctc", z80ctc_r, z80ctc_w)
 
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        AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
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        AM_RANGE(0x06, 0x07) AM_NOP
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ADDRESS_MAP_END
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209
 
static WRITE8_HANDLER(mcu_portA_w)
210
 
{
211
 
        pipeline_state *state = space->machine().driver_data<pipeline_state>();
212
 
        state->m_fromMCU=data;
213
 
}
214
 
 
215
 
static READ8_HANDLER(mcu_portA_r)
216
 
{
217
 
        pipeline_state *state = space->machine().driver_data<pipeline_state>();
218
 
        return (state->m_fromMCU&state->m_ddrA)|(state->m_toMCU& ~state->m_ddrA);
219
 
}
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221
 
static WRITE8_HANDLER(mcu_ddrA_w)
222
 
{
223
 
        pipeline_state *state = space->machine().driver_data<pipeline_state>();
224
 
        state->m_ddrA=data;
225
 
}
226
 
 
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static ADDRESS_MAP_START( mcu_mem, AS_PROGRAM, 8 )
 
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WRITE8_MEMBER(pipeline_state::mcu_portA_w)
 
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{
 
216
        m_fromMCU=data;
 
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}
 
218
 
 
219
READ8_MEMBER(pipeline_state::mcu_portA_r)
 
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{
 
221
        return (m_fromMCU&m_ddrA)|(m_toMCU& ~m_ddrA);
 
222
}
 
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WRITE8_MEMBER(pipeline_state::mcu_ddrA_w)
 
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{
 
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        m_ddrA=data;
 
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}
 
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static ADDRESS_MAP_START( mcu_mem, AS_PROGRAM, 8, pipeline_state )
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        AM_RANGE(0x0000, 0x0000) AM_READ(mcu_portA_r) AM_WRITE(mcu_portA_w)
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        AM_RANGE(0x0004, 0x0004) AM_WRITE(mcu_ddrA_w)
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        AM_RANGE(0x0010, 0x007f) AM_RAM
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        { NULL }
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};
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static const ppi8255_interface ppi8255_intf[3] =
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{
329
 
        {
330
 
                DEVCB_INPUT_PORT("P1"),                 /* Port A read */
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                DEVCB_NULL,                                             /* Port B read */
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                DEVCB_NULL,                                             /* Port C read */
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                DEVCB_NULL,                                             /* Port A write */
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                DEVCB_NULL,                                             /* Port B write */  /* related to sound/music : check code at 0x1c0a */
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                DEVCB_HANDLER(vidctrl_w)                /* Port C write */
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        },
337
 
        {
338
 
                DEVCB_INPUT_PORT("DSW1"),               /* Port A read */
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                DEVCB_INPUT_PORT("DSW2"),               /* Port B read */
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                DEVCB_HANDLER(protection_r),    /* Port C read */
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                DEVCB_NULL,                                             /* Port A write */
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                DEVCB_NULL,                                             /* Port B write */
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                DEVCB_HANDLER(protection_w)             /* Port C write */
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        },
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        {
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                DEVCB_NULL,                                             /* Port A read */
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                DEVCB_NULL,                                             /* Port B read */
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                DEVCB_NULL,                                             /* Port C read */
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                DEVCB_NULL,                                             /* Port A write */
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                DEVCB_NULL,                                             /* Port B write */
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                DEVCB_NULL                                              /* Port C write */
352
 
        }
 
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static I8255A_INTERFACE( ppi8255_0_intf )
 
330
{
 
331
        DEVCB_INPUT_PORT("P1"),                         /* Port A read */
 
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        DEVCB_NULL,                                                     /* Port A write */
 
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        DEVCB_NULL,                                                     /* Port B read */
 
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        DEVCB_NULL,                                                     /* Port B write */  // related to sound/music : check code at 0x1c0a
 
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        DEVCB_NULL,                                                     /* Port C read */
 
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        DEVCB_HANDLER(vidctrl_w)                        /* Port C write */
 
337
};
 
338
 
 
339
static I8255A_INTERFACE( ppi8255_1_intf )
 
340
{
 
341
        DEVCB_INPUT_PORT("DSW1"),                       /* Port A read */
 
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        DEVCB_NULL,                                                     /* Port A write */
 
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        DEVCB_INPUT_PORT("DSW2"),                       /* Port B read */
 
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        DEVCB_NULL,                                                     /* Port B write */
 
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        DEVCB_HANDLER(protection_r),            /* Port C read */
 
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        DEVCB_HANDLER(protection_w)                     /* Port C write */
 
347
};
 
348
 
 
349
static I8255A_INTERFACE( ppi8255_2_intf )
 
350
{
 
351
        DEVCB_NULL,                                                     /* Port A read */
 
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        DEVCB_NULL,                                                     /* Port A write */
 
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        DEVCB_NULL,                                                     /* Port B read */
 
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        DEVCB_NULL,                                                     /* Port B write */
 
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        DEVCB_NULL,                                                     /* Port C read */
 
356
        DEVCB_NULL                                                      /* Port C write */
353
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};
354
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static const ym2203_interface ym2203_config =
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static PALETTE_INIT(pipeline)
366
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{
367
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        int r,g,b,i,c;
368
 
        UINT8 *prom1 = &machine.region("proms")->base()[0x000];
369
 
        UINT8 *prom2 = &machine.region("proms")->base()[0x100];
 
372
        UINT8 *prom1 = &machine.root_device().memregion("proms")->base()[0x000];
 
373
        UINT8 *prom2 = &machine.root_device().memregion("proms")->base()[0x100];
370
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371
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        for(i=0;i<0x100;i++)
372
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        {
398
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399
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        MCFG_Z80CTC_ADD( "ctc", 7372800/2 /* same as "audiocpu" */, ctc_intf )
400
404
 
401
 
        MCFG_PPI8255_ADD( "ppi8255_0", ppi8255_intf[0] )
402
 
        MCFG_PPI8255_ADD( "ppi8255_1", ppi8255_intf[1] )
403
 
        MCFG_PPI8255_ADD( "ppi8255_2", ppi8255_intf[2] )
 
405
        MCFG_I8255A_ADD( "ppi8255_0", ppi8255_0_intf )
 
406
        MCFG_I8255A_ADD( "ppi8255_1", ppi8255_1_intf )
 
407
        MCFG_I8255A_ADD( "ppi8255_2", ppi8255_2_intf )
404
408
 
405
409
        /* video hardware */
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        MCFG_SCREEN_ADD("screen", RASTER)