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m79amb_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag) { }
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: driver_device(mconfig, type, tag) ,
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m_videoram(*this, "videoram"),
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m_mask(*this, "mask"){ }
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/* memory pointers */
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required_shared_ptr<UINT8> m_videoram;
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required_shared_ptr<UINT8> m_mask;
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UINT8 m_lut_gun1[0x100];
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UINT8 m_lut_gun2[0x100];
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DECLARE_WRITE8_MEMBER(ramtek_videoram_w);
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DECLARE_READ8_MEMBER(gray5bit_controller0_r);
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DECLARE_READ8_MEMBER(gray5bit_controller1_r);
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DECLARE_WRITE8_MEMBER(m79amb_8002_w);
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static WRITE8_HANDLER( ramtek_videoram_w )
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WRITE8_MEMBER(m79amb_state::ramtek_videoram_w)
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m79amb_state *state = space->machine().driver_data<m79amb_state>();
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state->m_videoram[offset] = data & ~*state->m_mask;
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m_videoram[offset] = data & ~*m_mask;
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static SCREEN_UPDATE_RGB32( ramtek )
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static READ8_HANDLER( gray5bit_controller0_r )
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m79amb_state *state = space->machine().driver_data<m79amb_state>();
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UINT8 port_data = input_port_read(space->machine(), "8004");
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UINT8 gun_pos = input_port_read(space->machine(), "GUN1");
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return (port_data & 0xe0) | state->m_lut_gun1[gun_pos];
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static READ8_HANDLER( gray5bit_controller1_r )
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m79amb_state *state = space->machine().driver_data<m79amb_state>();
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UINT8 port_data = input_port_read(space->machine(), "8005");
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UINT8 gun_pos = input_port_read(space->machine(), "GUN2");
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return (port_data & 0xe0) | state->m_lut_gun2[gun_pos];
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static WRITE8_HANDLER( m79amb_8002_w )
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READ8_MEMBER(m79amb_state::gray5bit_controller0_r)
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UINT8 port_data = ioport("8004")->read();
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UINT8 gun_pos = ioport("GUN1")->read();
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return (port_data & 0xe0) | m_lut_gun1[gun_pos];
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READ8_MEMBER(m79amb_state::gray5bit_controller1_r)
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UINT8 port_data = ioport("8005")->read();
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UINT8 gun_pos = ioport("GUN2")->read();
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return (port_data & 0xe0) | m_lut_gun2[gun_pos];
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WRITE8_MEMBER(m79amb_state::m79amb_8002_w)
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/* D1 may also be watchdog reset */
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/* port goes to 0x7f to turn on explosion lamp */
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output_set_value("EXP_LAMP", data ? 1 : 0);
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static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8 )
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static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, m79amb_state )
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AM_RANGE(0x0000, 0x1fff) AM_ROM
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AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE(ramtek_videoram_w) AM_BASE_MEMBER(m79amb_state, m_videoram)
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AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE(ramtek_videoram_w) AM_SHARE("videoram")
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AM_RANGE(0x6000, 0x63ff) AM_RAM /* ?? */
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AM_RANGE(0x8000, 0x8000) AM_READ_PORT("8000") AM_DEVWRITE("discrete", m79amb_8000_w)
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AM_RANGE(0x8001, 0x8001) AM_WRITEONLY AM_BASE_MEMBER(m79amb_state, m_mask)
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AM_RANGE(0x8000, 0x8000) AM_READ_PORT("8000") AM_DEVWRITE_LEGACY("discrete", m79amb_8000_w)
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AM_RANGE(0x8001, 0x8001) AM_WRITEONLY AM_SHARE("mask")
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AM_RANGE(0x8002, 0x8002) AM_READ_PORT("8002") AM_WRITE(m79amb_8002_w)
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AM_RANGE(0x8003, 0x8003) AM_DEVWRITE("discrete", m79amb_8003_w)
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AM_RANGE(0x8003, 0x8003) AM_DEVWRITE_LEGACY("discrete", m79amb_8003_w)
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AM_RANGE(0x8004, 0x8004) AM_READ(gray5bit_controller0_r)
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AM_RANGE(0x8005, 0x8005) AM_READ(gray5bit_controller1_r)
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AM_RANGE(0xc000, 0xc07f) AM_RAM /* ?? */
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PORT_DIPSETTING( 0xc0, DEF_STR( Free_Play ))
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PORT_START("8002")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_VBLANK )
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_TILT )