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Viewing changes to src/mame/drivers/exzisus.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Emmanuel Kasper, Jordi Mallach
  • Date: 2012-06-05 20:02:23 UTC
  • mfrom: (0.3.1) (0.1.4)
  • Revision ID: package-import@ubuntu.com-20120605200223-gnlpogjrg6oqe9md
Tags: 0.146-1
[ Emmanuel Kasper ]
* New upstream release
* Drop patch to fix man pages section and patches to link with flac 
  and jpeg system lib: all this has been pushed upstream by Cesare Falco
* Add DM-Upload-Allowed: yes field.

[ Jordi Mallach ]
* Create a "gnu" TARGETOS stanza that defines NO_AFFINITY_NP.
* Stop setting TARGETOS to "unix" in d/rules. It should be autodetected,
  and set to the appropriate value.
* mame_manpage_section.patch: Change mame's manpage section to 6 (games),
  in the TH declaration.

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Lines of Context:
src/mame/drivers/exzisus.c
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***************************************************************************/
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static WRITE8_HANDLER( exzisus_cpua_bankswitch_w )
50
 
{
51
 
        exzisus_state *state = space->machine().driver_data<exzisus_state>();
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        UINT8 *RAM = space->machine().region("cpua")->base();
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        if ( (data & 0x0f) != state->m_cpua_bank )
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        {
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                state->m_cpua_bank = data & 0x0f;
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                if (state->m_cpua_bank >= 2)
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                {
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                        memory_set_bankptr(space->machine(),  "bank2", &RAM[ 0x10000 + ( (state->m_cpua_bank - 2) * 0x4000 ) ] );
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                }
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        }
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        flip_screen_set(space->machine(), data & 0x40);
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}
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static WRITE8_HANDLER( exzisus_cpub_bankswitch_w )
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{
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        exzisus_state *state = space->machine().driver_data<exzisus_state>();
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        UINT8 *RAM = space->machine().region("cpub")->base();
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        if ( (data & 0x0f) != state->m_cpub_bank )
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        {
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                state->m_cpub_bank = data & 0x0f;
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                if (state->m_cpub_bank >= 2)
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                {
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                        memory_set_bankptr(space->machine(),  "bank1", &RAM[ 0x10000 + ( (state->m_cpub_bank - 2) * 0x4000 ) ] );
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                }
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        }
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        flip_screen_set(space->machine(), data & 0x40);
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}
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static WRITE8_HANDLER( exzisus_coincounter_w )
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{
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        coin_lockout_w(space->machine(), 0,~data & 0x01);
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        coin_lockout_w(space->machine(), 1,~data & 0x02);
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        coin_counter_w(space->machine(), 0,data & 0x04);
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        coin_counter_w(space->machine(), 1,data & 0x08);
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}
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static READ8_HANDLER( exzisus_sharedram_ab_r )
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{
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        exzisus_state *state = space->machine().driver_data<exzisus_state>();
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        return state->m_sharedram_ab[offset];
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}
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static READ8_HANDLER( exzisus_sharedram_ac_r )
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{
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        exzisus_state *state = space->machine().driver_data<exzisus_state>();
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        return state->m_sharedram_ac[offset];
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}
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static WRITE8_HANDLER( exzisus_sharedram_ab_w )
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{
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        exzisus_state *state = space->machine().driver_data<exzisus_state>();
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        state->m_sharedram_ab[offset] = data;
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}
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static WRITE8_HANDLER( exzisus_sharedram_ac_w )
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{
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        exzisus_state *state = space->machine().driver_data<exzisus_state>();
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        state->m_sharedram_ac[offset] = data;
 
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WRITE8_MEMBER(exzisus_state::exzisus_cpua_bankswitch_w)
 
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{
 
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        UINT8 *RAM = memregion("cpua")->base();
 
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        if ( (data & 0x0f) != m_cpua_bank )
 
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        {
 
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                m_cpua_bank = data & 0x0f;
 
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                if (m_cpua_bank >= 2)
 
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                {
 
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                        membank("bank2")->set_base(&RAM[ 0x10000 + ( (m_cpua_bank - 2) * 0x4000 ) ] );
 
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                }
 
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        }
 
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        flip_screen_set(data & 0x40);
 
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}
 
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WRITE8_MEMBER(exzisus_state::exzisus_cpub_bankswitch_w)
 
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{
 
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        UINT8 *RAM = memregion("cpub")->base();
 
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        if ( (data & 0x0f) != m_cpub_bank )
 
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        {
 
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                m_cpub_bank = data & 0x0f;
 
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                if (m_cpub_bank >= 2)
 
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                {
 
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                        membank("bank1")->set_base(&RAM[ 0x10000 + ( (m_cpub_bank - 2) * 0x4000 ) ] );
 
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                }
 
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        }
 
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        flip_screen_set(data & 0x40);
 
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}
 
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WRITE8_MEMBER(exzisus_state::exzisus_coincounter_w)
 
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{
 
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        coin_lockout_w(machine(), 0,~data & 0x01);
 
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        coin_lockout_w(machine(), 1,~data & 0x02);
 
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        coin_counter_w(machine(), 0,data & 0x04);
 
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        coin_counter_w(machine(), 1,data & 0x08);
 
87
}
 
88
 
 
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READ8_MEMBER(exzisus_state::exzisus_sharedram_ab_r)
 
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{
 
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        return m_sharedram_ab[offset];
 
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}
 
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READ8_MEMBER(exzisus_state::exzisus_sharedram_ac_r)
 
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{
 
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        return m_sharedram_ac[offset];
 
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}
 
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WRITE8_MEMBER(exzisus_state::exzisus_sharedram_ab_w)
 
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{
 
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        m_sharedram_ab[offset] = data;
 
102
}
 
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WRITE8_MEMBER(exzisus_state::exzisus_sharedram_ac_w)
 
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{
 
106
        m_sharedram_ac[offset] = data;
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}
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// is it ok that cpub_reset refers to cpuc?
116
 
static WRITE8_HANDLER( exzisus_cpub_reset_w )
 
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WRITE8_MEMBER(exzisus_state::exzisus_cpub_reset_w)
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{
118
 
        cputag_set_input_line(space->machine(), "cpuc", INPUT_LINE_RESET, PULSE_LINE);
 
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        cputag_set_input_line(machine(), "cpuc", INPUT_LINE_RESET, PULSE_LINE);
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}
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#if 0
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// the RAM check to work
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static DRIVER_INIT( exzisus )
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{
126
 
        UINT8 *RAM = machine.region("cpua")->base();
 
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        UINT8 *RAM = machine.root_device().memregion("cpua")->base();
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        /* Fix WORK RAM error */
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        RAM[0x67fd] = 0x18;
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**************************************************************************/
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static ADDRESS_MAP_START( cpua_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpua_map, AS_PROGRAM, 8, exzisus_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2")
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        AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_1_r, exzisus_objectram_1_w) AM_BASE_MEMBER(exzisus_state, m_objectram1) AM_SIZE_MEMBER(exzisus_state, m_objectram_size1)
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        AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_1_r, exzisus_videoram_1_w) AM_BASE_MEMBER(exzisus_state, m_videoram1)
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        AM_RANGE(0xe000, 0xefff) AM_READWRITE(exzisus_sharedram_ac_r, exzisus_sharedram_ac_w) AM_BASE_MEMBER(exzisus_state, m_sharedram_ac)
 
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        AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_1_r, exzisus_objectram_1_w) AM_SHARE("objectram1")
 
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        AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_1_r, exzisus_videoram_1_w) AM_SHARE("videoram1")
 
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        AM_RANGE(0xe000, 0xefff) AM_READWRITE(exzisus_sharedram_ac_r, exzisus_sharedram_ac_w) AM_SHARE("sharedram_ac")
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        AM_RANGE(0xf400, 0xf400) AM_WRITE(exzisus_cpua_bankswitch_w)
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        AM_RANGE(0xf404, 0xf404) AM_WRITE(exzisus_cpub_reset_w) // ??
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        AM_RANGE(0xf800, 0xffff) AM_READWRITE(exzisus_sharedram_ab_r, exzisus_sharedram_ab_w) AM_BASE_MEMBER(exzisus_state, m_sharedram_ab)
 
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        AM_RANGE(0xf800, 0xffff) AM_READWRITE(exzisus_sharedram_ab_r, exzisus_sharedram_ab_w) AM_SHARE("sharedram_ab")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( cpub_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpub_map, AS_PROGRAM, 8, exzisus_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
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        AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_0_r, exzisus_objectram_0_w) AM_BASE_MEMBER(exzisus_state, m_objectram0) AM_SIZE_MEMBER(exzisus_state, m_objectram_size0)
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        AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_0_r, exzisus_videoram_0_w) AM_BASE_MEMBER(exzisus_state, m_videoram0)
 
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        AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_0_r, exzisus_objectram_0_w) AM_SHARE("objectram0")
 
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        AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_0_r, exzisus_videoram_0_w) AM_SHARE("videoram0")
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        AM_RANGE(0xe000, 0xefff) AM_RAM
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        AM_RANGE(0xf000, 0xf000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_port_w)
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        AM_RANGE(0xf001, 0xf001) AM_DEVREADWRITE("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
 
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        AM_RANGE(0xf000, 0xf000) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_port_w)
 
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        AM_RANGE(0xf001, 0xf001) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_comm_r, tc0140syt_comm_w)
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        AM_RANGE(0xf400, 0xf400) AM_READ_PORT("P1")
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        AM_RANGE(0xf400, 0xf400) AM_WRITE(exzisus_cpub_bankswitch_w)
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        AM_RANGE(0xf401, 0xf401) AM_READ_PORT("P2")
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        AM_RANGE(0xf800, 0xffff) AM_READWRITE(exzisus_sharedram_ab_r, exzisus_sharedram_ab_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( cpuc_map, AS_PROGRAM, 8 )
 
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static ADDRESS_MAP_START( cpuc_map, AS_PROGRAM, 8, exzisus_state )
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0x85ff) AM_READWRITE(exzisus_objectram_1_r, exzisus_objectram_1_w)
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        AM_RANGE(0x8600, 0x9fff) AM_READWRITE(exzisus_videoram_1_r, exzisus_videoram_1_w)
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        AM_RANGE(0xb000, 0xbfff) AM_RAM
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ADDRESS_MAP_END
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181
 
static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8 )
 
175
static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, exzisus_state )
182
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        AM_RANGE(0x0000, 0x7fff) AM_ROM
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        AM_RANGE(0x8000, 0x8fff) AM_RAM
184
 
        AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE("ymsnd", ym2151_r, ym2151_w)
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        AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_slave_port_w)
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        AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
 
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        AM_RANGE(0x9000, 0x9001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
 
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        AM_RANGE(0xa000, 0xa000) AM_READNOP AM_DEVWRITE_LEGACY("tc0140syt", tc0140syt_slave_port_w)
 
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        AM_RANGE(0xa001, 0xa001) AM_DEVREADWRITE_LEGACY("tc0140syt", tc0140syt_slave_comm_r, tc0140syt_slave_comm_w)
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ADDRESS_MAP_END
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189
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266
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static const ym2151_interface ym2151_config =
267
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{
268
 
        irqhandler
 
262
        DEVCB_LINE(irqhandler)
269
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};
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